CN115440605A - Method for constructing storage chip packaging structure and packaging structure - Google Patents
Method for constructing storage chip packaging structure and packaging structure Download PDFInfo
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- CN115440605A CN115440605A CN202211219226.1A CN202211219226A CN115440605A CN 115440605 A CN115440605 A CN 115440605A CN 202211219226 A CN202211219226 A CN 202211219226A CN 115440605 A CN115440605 A CN 115440605A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 230000010354 integration Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to the technical field of semiconductor packaging, and provides a method for constructing a memory chip packaging structure and the packaging structure. The method comprises the following steps: providing a first chip; forming a recess on a first side of the first chip; arranging a control chip at the groove; providing a second chip, wherein a storage area is arranged on the second chip; and stacking the first side of the second chip on the second side of the first chip. According to the invention, the TSV structure is constructed on the chip body, the functional chip and the adapter plate in the traditional packaging structure are combined into a whole, the performance of the chip is improved, meanwhile, the packaging volume is reduced, and the integration level of three-dimensional packaging can be effectively improved by digging a cavity in the back space of the functional chip and embedding the control chip.
Description
Technical Field
The present invention relates generally to the field of semiconductor packaging technology. In particular, the present invention relates to a method for constructing a memory chip package structure and a package structure.
Background
Conventionally, when packaging a memory chip and a control chip, the memory chip and the control chip are usually disposed on the same side or different sides of a package carrier, and the memory chip and the control chip are plastic-packaged by using a plastic packaging material.
However, in the conventional package structure, since both the memory chip and the control chip are disposed on the surface of the package carrier, the volume of the package structure is too large; moreover, because a large amount of plastic packaging materials are used, the heat dissipation of the packaging carrier is influenced, the warping of the packaging carrier is easy to cause, and the reliability of subsequent packaging is influenced; in addition, a Printed Circuit Board (PCB) is generally used as a package carrier in a conventional package structure, but the process node and the size of the PCB are large, so that it is difficult to meet the current package requirement of higher integration density.
Disclosure of Invention
To at least partially solve the above problems in the prior art, the present invention provides a method for constructing a memory chip package structure, comprising the following steps:
providing a first chip;
forming a recess on a first side of the first chip;
arranging a control chip at the groove;
providing a second chip, wherein a storage area is arranged on the second chip; and
stacking the first side of the second chip on the second side of the first chip.
In one embodiment of the present invention, it is provided that the method of constructing a memory chip package structure further includes:
constructing a first through-silicon-via on the first chip;
constructing a second through silicon via on the second chip; and
connecting the second through-silicon via with the first through-silicon via when the second chip is stacked on the first chip.
In one embodiment of the invention, it is provided that the second chip comprises one or more memory regions.
In one embodiment of the invention, it is provided that the number of storage areas is greater than or equal to 4.
In one embodiment of the invention, provision is made for a plurality of second chips to be provided, wherein a plurality of second chips are stacked on top of one another.
The present invention also provides a memory chip package structure constructed according to the method for constructing a memory chip package structure, the structure comprising:
the chip comprises a first chip, a second chip and a third chip, wherein a groove is arranged on a first face of the first chip, and a control chip is arranged at the groove;
a second chip comprising a memory chip, wherein a first side of the second chip is stacked on a second side of the first chip.
In one embodiment of the invention, it is provided that the first chip further comprises a first through silicon via and the second chip further comprises a second through silicon via, wherein the first through silicon via is connected to the second through silicon via.
In one embodiment of the invention, it is provided that the second chip comprises one or more memory areas.
In one embodiment of the invention, it is provided that the number of storage areas is greater than or equal to 4.
In one embodiment of the present invention, it is provided that the memory chip package structure includes:
a plurality of second chips, wherein a plurality of the second chips are stacked on one another.
The invention has at least the following beneficial effects: the invention provides a method for constructing a storage chip packaging structure and the packaging structure. The TSV structure is constructed on the chip body, the functional chip and the adapter plate in the traditional packaging structure are combined into a whole, the performance of the chip is improved, meanwhile, the packaging volume is reduced, and the integration level of three-dimensional packaging can be effectively improved by digging a cavity in the back space of the functional chip and embedding the control chip.
Drawings
To further clarify the advantages and features that may be present in various embodiments of the present invention, a more particular description of various embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 is a flow chart illustrating a method of constructing a memory chip package structure according to an embodiment of the invention.
Fig. 2-5 are block diagrams illustrating a process of constructing a memory chip package structure according to an embodiment of the invention.
Fig. 6 shows a top view of a second chip in an embodiment of the invention.
FIG. 7 is a schematic diagram of a memory chip package structure in one embodiment of the invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, "disposed on" \ 8230 "", "disposed over" \823030 "", and "disposed over" \8230 "", do not exclude the presence of an intermediate therebetween, unless otherwise specified. Furthermore, "arranged on or above" \\8230 ", merely indicates a relative positional relationship between two components, and in certain cases, such as after reversing the product direction, may also be converted to" arranged under or below \8230 ", and vice versa.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario. In addition, features in different embodiments of the invention may be combined with each other, unless otherwise specified. For example, a feature of the second embodiment may be substituted for a corresponding or functionally equivalent or similar feature of the first embodiment, and the resulting embodiments are likewise within the scope of the disclosure or recitation of the present application.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal". By analogy, in the present invention, the terms "perpendicular", "parallel" and the like in the directions of the tables also cover the meanings of "substantially perpendicular", "substantially parallel".
The numbering of the steps of the methods of the present invention does not limit the order of execution of the steps of the methods. Unless specifically stated, the method steps may be performed in a different order.
The invention is further elucidated with reference to the drawings in conjunction with the detailed description.
Fig. 1 is a flow chart illustrating a method for constructing a memory chip package structure according to an embodiment of the invention. As shown in fig. 1, the method may include the steps of:
step 101, providing a first chip 201.
Step 102, forming a groove 301 on a first surface of the first chip 201.
Step 103, arranging a control chip 401 at the groove 301.
Step 104, providing a second chip 501, wherein a storage region 502 is disposed on the second chip 501.
Step 105, stacking the first side of the second chip 501 on the second side of the first chip 201.
Fig. 2-5 are block diagrams illustrating a process of constructing a memory chip package structure according to an embodiment of the invention. The steps of the construction method are described in detail below with reference to fig. 2-5.
As shown in fig. 2, a first chip 201 may be provided in step 101, wherein a first storage region (not shown) may be disposed on a second side of the first chip 201, and a first through silicon via 202 (TSV) may be disposed around the first storage region, and the first through silicon via 202 may penetrate through the first side and the second side of the first chip 201.
As shown in fig. 3, in step 102, a recess 301 may be formed on the first side of the first chip 201 by a photolithography or etching process.
As shown in fig. 4, a control chip 401 may be arranged at the recess 301 in step 103. By utilizing the cavity dug in the back space of the first chip 201 to embed the chip 401, the integration level of three-dimensional direction packaging can be effectively improved.
As shown in fig. 5, a second chip 501 may be provided in step 104, wherein a second storage region 503 is disposed on the second chip 501, and a second through silicon via 502 is disposed around the second storage region 503. Fig. 6 shows a top view of a second chip 501 according to an embodiment of the invention, as shown in fig. 6, the second chip 501 may include a plurality of second storage regions 503, and the number of the second storage regions 503 may be greater than or equal to 4.
FIG. 7 is a schematic diagram of a memory chip package structure in one embodiment of the invention. In step 105, the second chip 501 may be stacked on the first chip 201 to form a package structure shown in fig. 7, wherein a plurality of the second chips 501 may be stacked on the first chip 201 after being stacked on each other, and during the stacking process, the first chip 201 and the second chip may be connected to each other through the first through silicon via 202 and the second through silicon via 502.
As shown in fig. 7, the memory chip package structure may include:
a first chip 201, wherein a first side of the first chip 201 is provided with a groove 301, and a control chip 401 is arranged at the groove 301;
a plurality of second chips 501 including a memory region, wherein a plurality of the second chips 501 are stacked on each other and on the first chip 201, wherein the first chip 201 and the plurality of second chips 501 are connected to each other through a first through-silicon via 202 and a second through-silicon via 502.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various combinations, modifications, and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A method of constructing a memory chip package structure, comprising the steps of:
providing a first chip;
forming a recess on a first side of the first chip;
arranging a control chip at the groove;
providing a second chip, wherein a storage area is arranged on the second chip; and
stacking the first side of the second chip on the second side of the first chip.
2. The method of constructing a memory chip package of claim 1, further comprising:
constructing a first through-silicon-via on the first chip;
constructing a second through-silicon-via on the second chip; and
connecting the second through-silicon via with the first through-silicon via when the second chip is stacked on the first chip.
3. The method of claim 1, wherein the second chip comprises one or more memory regions.
4. The method of claim 3, wherein the number of the storage areas is greater than or equal to 4.
5. The method of claim 1, wherein a plurality of the second chips are provided, wherein a plurality of the second chips are stacked on top of each other.
6. A memory chip package structure constructed in accordance with the method of any one of claims 1-5, the structure comprising:
the chip comprises a first chip, a second chip and a third chip, wherein a groove is arranged on a first face of the first chip, and a control chip is arranged at the groove;
a second chip including a storage region, wherein a first side of the second chip is stacked on a second side of the first chip.
7. The memory chip package structure of claim 6, wherein the first chip further comprises a first through silicon via and the second chip further comprises a second through silicon via, wherein the first through silicon via is connected to the second through silicon via.
8. The memory chip package structure of claim 6, wherein the second chip comprises one or more memory regions.
9. The memory chip package structure of claim 8, wherein the number of the memory regions is greater than or equal to 4.
10. The memory chip package of claim 9, comprising:
a plurality of second chips, wherein a plurality of the second chips are stacked on one another.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211219226.1A CN115440605A (en) | 2022-09-30 | 2022-09-30 | Method for constructing storage chip packaging structure and packaging structure |
| PCT/CN2023/081592 WO2024066226A1 (en) | 2022-09-30 | 2023-03-15 | Method for constructing storage chip packaging structure and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211219226.1A CN115440605A (en) | 2022-09-30 | 2022-09-30 | Method for constructing storage chip packaging structure and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115440605A true CN115440605A (en) | 2022-12-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211219226.1A Pending CN115440605A (en) | 2022-09-30 | 2022-09-30 | Method for constructing storage chip packaging structure and packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115440605A (en) |
| WO (1) | WO2024066226A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066226A1 (en) * | 2022-09-30 | 2024-04-04 | 华进半导体封装先导技术研发中心有限公司 | Method for constructing storage chip packaging structure and packaging structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7973310B2 (en) * | 2008-07-11 | 2011-07-05 | Chipmos Technologies Inc. | Semiconductor package structure and method for manufacturing the same |
| CN110473791A (en) * | 2019-08-30 | 2019-11-19 | 华天科技（西安）有限公司 | It is a kind of that reeded storage class wrapper structure and packaging method are set |
| WO2021146860A1 (en) * | 2020-01-20 | 2021-07-29 | 深圳市汇顶科技股份有限公司 | Stacked chip, manufacturing method, image sensor, and electronic device |
| CN114171399A (en) * | 2021-12-08 | 2022-03-11 | 通富微电子股份有限公司 | Packaging method and packaging structure of multilayer stacked high-bandwidth memory |
| CN115440605A (en) * | 2022-09-30 | 2022-12-06 | 华进半导体封装先导技术研发中心有限公司 | Method for constructing storage chip packaging structure and packaging structure |
-
2022
- 2022-09-30 CN CN202211219226.1A patent/CN115440605A/en active Pending
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2023
- 2023-03-15 WO PCT/CN2023/081592 patent/WO2024066226A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066226A1 (en) * | 2022-09-30 | 2024-04-04 | 华进半导体封装先导技术研发中心有限公司 | Method for constructing storage chip packaging structure and packaging structure |
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| WO2024066226A1 (en) | 2024-04-04 |
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