CN218887123U - Three-dimensional chip - Google Patents
Three-dimensional chip Download PDFInfo
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- CN218887123U CN218887123U CN202122051458.8U CN202122051458U CN218887123U CN 218887123 U CN218887123 U CN 218887123U CN 202122051458 U CN202122051458 U CN 202122051458U CN 218887123 U CN218887123 U CN 218887123U
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Abstract
The utility model provides a three-dimensional chip, include: providing at least two wafers; forming a real hybrid bonding part and a virtual hybrid bonding part between at least two wafers; therefore, a plurality of virtual mixed bonding parts are arranged between the two wafers, so that heat between the two wafers can be transmitted to the substrate through the virtual bonding parts, and the substrate transmits the heat to the outside of the substrate through the Ball Grid Array (BGA), thereby improving the heat dissipation effect of the three-dimensional chip; because the stress can be dispersed simultaneously by the plurality of virtual mixed bonding parts, the stress borne by a single real mixed bonding part is reduced, and the corresponding medium of the real mixed bonding part is avoidedThe stratum corneum is cracked; in addition, the plurality of virtual mixed bonding parts can improve the distribution uniformity of the mixed bonding parts, and SiO is filled between two wafers 2 And meanwhile, the filling of the cavity is avoided, and the overall performance of the device is ensured.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a three-dimensional chip.
Background
Currently, the transistor size of the chip is approaching the physical limit, and the improvement of the chip performance is more dependent on the development of three-dimensional integration technology. The three-dimensional integrated circuit 3DIC with fine pitch and high density can improve the overall performance and space utilization rate of the chip and reduce the manufacturing cost of the chip.
In the prior art, a logic chip and a memory chip are generally subjected to a hybrid bonding process, and stacked to form a metal connection to form a 3DIC. However, heat between chips cannot be effectively transmitted, and the single Hybrid bonding portion bears too much stress, which easily causes the dielectric layer corresponding to the Hybrid bonding portion to crack, thereby affecting the overall performance of the device.
Disclosure of Invention
Aiming at the problems in the prior art, the embodiment of the utility model provides a three-dimensional chip, which is used for solving the problems that in the prior art, when a 3D three-dimensional chip is prepared, the heat between wafers cannot be effectively transmitted, and the stress born by a single mixed bonding part is too large and is easy to crack; filling SiO between the wafers 2 In the process, filling holes exist, and the overall performance of the device is affected.
The utility model provides a three-dimensional chip, three-dimensional chip includes:
at least two wafers;
and a real mixed bonding part and a virtual mixed bonding part are arranged between the wafers.
In the above scheme, the virtual hybrid bonding portion is located between the dielectric layer of one wafer and the dielectric layer of another wafer in the three-dimensional chip.
In the above scheme, if the distribution distance between two adjacent real mixed bonding portions satisfies a preset first distance threshold, a corresponding number of the virtual mixed bonding portions are arranged between the adjacent real mixed bonding portions.
In the foregoing solution, if it is determined that the distribution distance between adjacent real hybrid bonding portions is the second distance threshold, a plurality of the virtual hybrid bonding portions are disposed in the non-real hybrid bonding portion region between adjacent real hybrid bonding portions.
In the above solution, the virtual mixed bonding part pitch is greater than the real mixed bonding part pitch, the virtual mixed bonding part pitch includes a distribution pitch between two adjacent virtual mixed bonding parts, and the real mixed bonding part pitch includes a distribution pitch between two adjacent real mixed bonding parts.
In the above aspect, the virtual hybrid bonding portion includes:
the first bonding part is positioned on a first lamination formed by a metal layer and a dielectric layer of a wafer, and the first bonding part penetrates through the first lamination to be connected with a bottom dielectric layer of the wafer;
the second bonding part is positioned on a second lamination formed by the metal layer and the dielectric layer of the other wafer, and the second bonding part penetrates through the second lamination to be connected with the bottom dielectric layer of the other wafer;
the first key portion is connected with the second key portion.
In the above scheme, if the distribution distance x between two adjacent real hybrid bonding portions satisfies 8<x not more than 15 μm, one virtual hybrid bonding portion is disposed between two adjacent real hybrid bonding portions.
In the above scheme, if the distribution distance x between two adjacent real hybrid bonding portions satisfies 15< -x ≤ 20 μm, at least two virtual hybrid bonding portions are disposed between the adjacent real hybrid bonding portions.
In the above solution, the number of the virtual hybrid bonding portions is greater than the number of the real hybrid bonding portions.
The utility model provides a three-dimensional chip, include: at least two wafers; a real mixed bonding part and a virtual mixed bonding part are arranged between the wafers; therefore, at least two wafers can be electrically connected through the real hybrid bonding part, heat between the two wafers can be transmitted to the substrate through the virtual bonding part and the real hybrid bonding part, and the substrate transmits the heat to the outside of the substrate through the Ball Grid Array (BGA), so that the heat dissipation effect of the three-dimensional chip is improved; meanwhile, the virtual mixed bonding part can disperse stress at the same time, so that the stress borne by a single real mixed bonding part is reduced, and the cracking of the real mixed bonding part is avoided; in addition, the dummy hybrid bonding portion can improve the uniformity of the distribution of the hybrid bonding portion, and SiO is filled between the two wafers 2 And meanwhile, the filling of the cavity is avoided, and the overall performance of the device is ensured.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic view of an overall structure of a three-dimensional chip according to an embodiment of the present invention;
fig. 2 is another schematic overall structure diagram of a three-dimensional chip according to an embodiment of the present invention.
Description of the reference numerals:
1-true hybrid bonding; 2-a virtual hybrid bond; 3-a wafer; 4-another wafer; 5-a third bonding moiety; 6-a bottom metal layer of a wafer; 7-a fourth bonding portion; 8-bottom metal layer of another wafer; 9-a first bond; 10-a second bond; 11-a bottom dielectric layer of a wafer; 12-the bottom dielectric layer of another wafer.
Detailed Description
The method aims to solve the problems that in the prior art, when a 3D chip is prepared, heat among wafers cannot be effectively transmitted, and a single mixed bonding part bears overlarge stress and is easy to crack; filling SiO between the wafers 2 In time, there is a technical problem of filling voids, which further affects the overall performance of the device. The utility model provides a three-dimensional chip.
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required. In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In the above description, details of the techniques such as patterning and etching of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.
The present embodiment provides a three-dimensional chip, as shown in fig. 1, the three-dimensional chip includes:
at least two wafers;
a real mixed bonding part 1 and a virtual mixed bonding part 2 are arranged between the wafers; the virtual mixed bonding part 2 is arranged between two adjacent real mixed bonding parts 1, the real mixed bonding parts 1 are used for signal transmission between two wafers, and the virtual mixed bonding part 2 has no signal transmission; the virtual hybrid bonding portion 2 includes a plurality of portions. The signals transmitted by the true hybrid bond 1 may include: the signal may include: any one of a power signal, a data signal, and a command signal.
Generally, the at least two wafers provided may be wafers with different functions or wafers with the same function. For example, when the number of the wafers is two and the functions of the two wafers are different, one of the wafers may be a storage wafer and the other wafer may be a logic wafer.
Wherein, storage wafer from the bottom up has set gradually: the device comprises a substrate, a device layer, a first laminated layer formed by a metal layer and a dielectric layer, and an aluminum PAD; the metal layer and the dielectric layer both comprise at least one layer, and the position relationship of the metal layer and the dielectric layer is cross lamination. Tungsten is filled between the device layer and the bottom metal layer and used as a barrier layer.
The logic wafer is sequentially provided with from bottom to top: the substrate, the device layer, the second lamination formed by the metal layer and the dielectric layer, and the copper PAD. Similarly, the metal layer and the dielectric layer of the logic wafer each include at least one layer, and the positional relationship between the metal layer and the dielectric layer is cross-laminated. Tungsten is filled between the device layer and the bottom metal layer and used as a barrier layer. The dielectric layer materials in the memory wafer and the logic wafer are dielectric materials such as silicon oxide and silicon nitride.
For convenience of description, the three-dimensional chip is illustrated as including two wafers. With continued reference to fig. 2, the true hybrid bond 1 is located between the metal layer of one wafer 3 and the metal layer of another wafer 4 in the three-dimensional chip. The virtual hybrid bond 2 is located between the dielectric layer of one wafer 3 and the dielectric layer of another wafer 4 in the three-dimensional chip.
Specifically, the true hybrid bonding portion 1 includes:
a third bonding portion 5 located in a first lamination formed by the metal layer and the dielectric layer of the wafer 3, the third bonding portion 5 penetrating through the first lamination and electrically connected with a bottom metal layer 6 of the wafer 3;
and the fourth bonding part 7 is positioned in the second lamination formed by the metal layer and the dielectric layer of the other wafer 4, and the fourth bonding part 7 penetrates through the second lamination to be electrically connected with the bottom metal layer 8 of the other wafer 4.
For any wafer, when the front surface of the wafer faces upward, the bottom metal layer is the metal layer located at the lowest part of the stack layer, and can also be understood as the first metal layer of the wafer.
The front surface of the wafer is the side on which the device layer is formed, and the material of the third bonding portion and the fourth bonding portion may be a conductive material, such as copper, aluminum, tungsten, etc., and in this embodiment, copper is preferred.
In practical application, the number of the real hybrid bonding parts 1 is small, the distribution is not uniform, and the heat dissipation effect among wafers cannot be ensured; simultaneously filling SiO between two wafers 2 In the process, filling holes exist, so that stress distribution is not uniform, stress between wafers is concentrated on a small number of real hybrid bonding parts 1, and a dielectric layer corresponding to the real hybrid bonding parts is cracked. Therefore, in this embodiment, a plurality of dummy hybrid bonding portions 2 are formed between two wafers.
The virtual hybrid bond 2 includes:
the first bonding part 9 is positioned in a first lamination formed by the metal layer and the dielectric layer of the wafer 3, and the first bonding part 9 penetrates through the first lamination to be connected with the dielectric layer of the wafer 3;
and a second bonding part 10, which is located in a second lamination formed by the metal layer and the dielectric layer of the other wafer 4, wherein the second bonding part 10 penetrates through the second lamination to be connected with the dielectric layer of the other wafer 4.
The first key portion 9 is connected to the second key portion 10.
The dielectric layer connected to the first bonding portion 9 may be any one of the dielectric layers in the first stack, and the dielectric layer connected to the second bonding portion 10 may be any one of the dielectric layers in the second stack. However, since the metal layer connected to the third bonding portion 5 is the bottom metal layer in the first stacked layer, and the metal layer connected to the fourth bonding portion 7 is the bottom metal layer in the second stacked layer, for convenience of manufacturing process, in the third embodiment, when the first bonding portion 9 and the second bonding portion 10 are disposed, the first bonding portion 9 penetrates through the first stacked layer to be connected with the bottom dielectric layer 11 of one wafer 3, and the second bonding portion 10 penetrates through the second stacked layer to be connected with the bottom dielectric layer 12 of another wafer 4.
Here, when the front surface of the wafer faces upward, the bottom dielectric layer is the dielectric layer located at the lowest part of the stack, and may also be understood as the first dielectric layer of the wafer.
When two wafers are bonded, the front surface of one wafer 3 faces upwards, the front surface of the other wafer 4 faces downwards, when the first bonding part 9 and the second bonding part 10 are aligned, the third bonding part 5 and the fourth bonding part 7 are ensured to be aligned and contacted, the electrical connection of the third bonding part 5 and the fourth bonding part 7 is realized, and the connection of the first bonding part 9 and the second bonding part 10 is realized.
It will be appreciated that the virtual hybrid bond 2 is located between the dielectric layers, without electrical connection properties, and the virtual hybrid bond 2 does not have any signal transmission, thus avoiding signal interference problems.
Further, the distribution positions of the virtual hybrid bonds 2 may be determined according to the distribution pitch of the real hybrid bonds 1.
In an alternative embodiment, if the distribution distance between two adjacent real hybrid bonds 1 satisfies the first distance threshold, a corresponding number of distribution positions of the virtual hybrid bonds 2 are set between two adjacent real hybrid bonds 1.
For example, if it is determined that the distribution distance x between two adjacent real hybrid bonding portions satisfies 8<x ≤ 15 μm, a distribution position of a virtual hybrid bonding portion is set between two adjacent real hybrid bonding portions; the real hybrid bond is adjacent to the virtual hybrid bond.
Referring to fig. 1, if the distribution distance between two adjacent real hybrid bonding portions is small in a certain region, and 8<x is less than or equal to 15 μm, a distribution position of a virtual hybrid bonding portion may be set between the adjacent real hybrid bonding portions in the region, so that the virtual hybrid bonding portion is adjacent to the real hybrid bonding portion.
And if the distribution spacing x of the adjacent real mixed bonding parts is determined to meet the condition that the number of the woven fabrics is less than or equal to 15 and x is less than or equal to 20 mu m, setting the distribution positions of at least two virtual mixed bonding parts between the adjacent real mixed bonding parts.
Referring to fig. 2, if the distribution distance between two adjacent real hybrid bonds in a certain region is large and satisfies 15< x ≦ 20 μm, the distribution positions of at least two virtual hybrid bonds may be set between the adjacent real hybrid bonds in the region so that the at least two virtual hybrid bonds are located between the adjacent real hybrid bonds.
In practical applications, it may also occur that some regions (such as the left region and the right region of the wafer) have relatively dense real hybrid bonds 1, and the middle region is not provided with the real hybrid bonds 1, and in an alternative embodiment, if it is determined that the distribution distance between the adjacent real hybrid bond 1 regions is the second distance threshold, a plurality of virtual hybrid bonds 2 are provided in the non-real hybrid bond region between the adjacent real hybrid bond 1 regions. The second distance threshold is greater than 100 μm.
The real mixed bonding part area is an area where the real mixed bonding parts 1 are distributed densely, and the non-real mixed bonding part area is an area where the real mixed bonding parts 1 are not distributed.
It should be noted that in the present embodiment, the pitch of the virtual hybrid bonding portions 2 is greater than the pitch of the real hybrid bonding portions 1, the pitch of the virtual hybrid bonding portions 2 is the distribution pitch between two adjacent virtual hybrid bonding portions 2, and the pitch of the real hybrid bonding portions 1 is the distribution pitch between two adjacent real hybrid bonding portions 1. In general, the distribution pitch of the virtual hybrid bonding portions 2 is 1.8 to 2.2 times the distribution pitch of the real hybrid bonding portions 1.
And the number of virtual hybrid bonds 2 is greater than the number of real hybrid bonds 1, the ratio between the number of virtual hybrid bonds 2 and the number of real hybrid bonds 1 being from 900.
In the embodiment, at least two wafers can be electrically connected through the real hybrid bonding part, and a plurality of virtual hybrid bonding parts are arranged between the two wafers, so that heat between the two wafers can be transmitted to the substrate through the virtual hybrid bonding parts and the real hybrid bonding part, and the substrate transmits the heat to the outside of the substrate through the Ball Grid Array (BGA), thereby improving the heat dissipation effect of the three-dimensional chip; meanwhile, the stress can be dispersed simultaneously by the plurality of virtual mixed bonding parts, so that the stress borne by a single real mixed bonding part is reduced, and the cracking of a dielectric layer corresponding to the real mixed bonding part is avoided; in addition, the plurality of virtual mixed bonding parts can improve the distribution uniformity of the mixed bonding parts, and SiO is filled between two wafers 2 In the process, the filling of the cavity is avoided, and the overall performance of the device is ensured;and because the virtual mixed bonding part is positioned between the dielectric layers and has no electrical connection property, the problem of signal interference caused by interconnection with the metal layer can be avoided.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention, and any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A three-dimensional chip, comprising:
at least two wafers;
and a real mixed bonding part and a virtual mixed bonding part are arranged between the wafers.
2. The three-dimensional chip of claim 1, wherein the virtual hybrid bond is located between a dielectric layer of one wafer and a dielectric layer of another wafer in the three-dimensional chip.
3. The three-dimensional chip according to claim 1, wherein a corresponding number of the virtual hybrid bonding portions are disposed between two adjacent real hybrid bonding portions if a distribution pitch between the two adjacent real hybrid bonding portions satisfies a preset first distance threshold.
4. The three-dimensional chip according to claim 1, wherein a plurality of the virtual hybrid bonds are disposed in the non-real hybrid bond regions between adjacent real hybrid bond regions if it is determined that the distribution pitch between the adjacent real hybrid bond regions is the second distance threshold.
5. The three-dimensional chip according to claim 1, wherein a virtual hybrid bond pitch is larger than a real hybrid bond pitch, the virtual hybrid bond pitch comprising a distribution pitch between two adjacent virtual hybrid bonds, the real hybrid bond pitch comprising a distribution pitch between two adjacent real hybrid bonds.
6. The three-dimensional chip of claim 2, wherein the virtual hybrid bond comprises:
the first bonding part is positioned on a first lamination formed by a metal layer and a dielectric layer of a wafer, and the first bonding part penetrates through the first lamination to be connected with a bottom dielectric layer of the wafer;
the second bonding part is positioned on a second lamination formed by the metal layer and the dielectric layer of the other wafer, and the second bonding part penetrates through the second lamination to be connected with the bottom dielectric layer of the other wafer;
the first key portion is connected with the second key portion.
7. The three-dimensional chip according to claim 3, wherein one virtual hybrid bonding portion is disposed between two adjacent real hybrid bonding portions if a distribution pitch x between the two adjacent real hybrid bonding portions satisfies 8<x ≤ 15 μm.
8. The three-dimensional chip according to claim 3, wherein at least two virtual hybrid bonding portions are disposed between two adjacent real hybrid bonding portions if a distribution pitch x between the two adjacent real hybrid bonding portions satisfies 15-straw-bundle x ≦ 20 μm.
9. The three-dimensional chip according to claim 1, wherein the number of virtual hybrid bonds is greater than the number of real hybrid bonds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122051458.8U CN218887123U (en) | 2021-08-27 | 2021-08-27 | Three-dimensional chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122051458.8U CN218887123U (en) | 2021-08-27 | 2021-08-27 | Three-dimensional chip |
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| CN218887123U true CN218887123U (en) | 2023-04-18 |
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| CN202122051458.8U Active CN218887123U (en) | 2021-08-27 | 2021-08-27 | Three-dimensional chip |
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