CN209785939U - Memory device - Google Patents

Abstract

The utility model relates to a memory, the memory includes: the first base comprises a first substrate, a storage array formed on the front surface of the first substrate and a first dielectric layer covering the storage array; the second base comprises a second substrate, a logic circuit formed on the front surface of the second substrate and a second dielectric layer covering the logic circuit; the metal heat dissipation line is formed in the first dielectric layer and/or the second dielectric layer; the first substrate and the second substrate are stacked and bonded. The storage density of the memory is increased.

Description

Memory device

Technical Field

The utility model relates to the field of semiconductor technology, especially, relate to a memory.

Background

DRAM (Dynamic Random Access Memory) technology belongs to an important Memory technology of integrated circuits, and in order to improve the density and capacity of DRAM memories, DRAM processes are increasingly complex, and the size of devices is continuously reduced, so that the negative effects of the devices are also increasingly greater.

The existing methods for improving the density and capacity of the DRAM are to form a logic device and a memory device on a wafer at the same time, which necessitates continuous reduction of the device size on a limited wafer area, increases the process complexity, and has negative effects caused by the reduction of the device size.

How to further increase the density and capacity of DRAM and avoid the negative effect is a problem that needs to be solved at present.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that a memory is provided, the storage density of memory is improved.

In order to solve the above problem, the utility model provides a memory, include: the first base comprises a first substrate, a storage array formed on the front surface of the first substrate and a first dielectric layer covering the storage array; the second base comprises a second substrate, a logic circuit formed on the front surface of the second substrate and a second dielectric layer covering the logic circuit; the metal heat dissipation line is formed in the first dielectric layer and/or the second dielectric layer; the first substrate and the second substrate are stacked and bonded.

Optionally, the memory array is a DRAM memory array.

Optionally, an interconnection structure is formed in each of the first dielectric layer and the second dielectric layer, and the interconnection structure includes a plurality of layers of interconnection lines.

Optionally, the metal heat dissipation line and the at least one layer of interconnection line are located in the same layer.

Optionally, at least one end of the metal heat dissipation line extends to the edge of the memory, and is isolated from the outside of the memory by a protective layer, and the protective layer covers the end of the metal heat dissipation line.

Optionally, the surfaces of the first dielectric layer and the second dielectric layer are bonded oppositely.

Optionally, the method further includes: and the deep through hole connecting part penetrates through the second substrate and is connected with the interconnection structure in the first substrate.

Optionally, the method further includes: the welding pad is positioned on the back surface of the second substrate and connected with the deep through hole connecting part, and the protective layer covers the back surface of the second substrate and is flush with the surface of the welding pad.

Optionally, the back surface of the first substrate and the back surface of the second substrate are bonded and connected oppositely; or the first dielectric layer is in opposite bonding connection with the back surface of the second substrate; or the second dielectric layer is oppositely bonded and connected with the back surface of the first substrate.

The utility model discloses a storage array and logic circuit of memory form respectively in two bases, and the rethread piles up the bonding mode, pile up storage array and logic circuit's base to can improve the memory storage density in the unit area.

Furthermore, a metal heat dissipation line is formed in the dielectric layer of at least one substrate, and heat is dissipated outwards through the metal heat dissipation line, so that the problem that the heat inside the memory is too large due to substrate stacking is solved.

Furthermore, the metal heat dissipation wire can be formed simultaneously with the interconnection wire in the interconnection structure in the substrate, so that additional process steps are not required, and the process cost is not increased; and the positions of the metal heat dissipation wires can be set according to the distribution density of the interconnection wires, so that the metal distribution uniformity in the metal layer is improved, the etching load effect is improved, and the uniformity of chemical mechanical polishing is improved.

Drawings

Fig. 1 to 5 are schematic structural diagrams illustrating a process of forming a memory according to an embodiment of the present invention.

Detailed Description

The following describes in detail a specific embodiment of the memory and the forming method thereof according to the present invention with reference to the accompanying drawings.

Please refer to fig. 1 to 5, which are schematic structural diagrams illustrating a formation process of a memory according to an embodiment of the present invention.

Referring to fig. 1, a first substrate 100 is provided, where the first substrate 100 includes a first substrate 110, a memory array formed on a front surface of the first substrate 110, and a first dielectric layer 120 covering the memory array.

The first substrate 110 is a semiconductor substrate, such as a monocrystalline silicon substrate, a silicon germanium substrate, a silicon on insulator substrate, or the like. The first substrate 110 has a Shallow Trench Isolation (STI) therein.

In this specific embodiment, the memory array is a DRAM memory array, and the DRAM memory array is composed of a plurality of DRAM memory cells.

The DRAM memory cell includes: an access transistor 102 formed on the substrate 110, and a capacitor 103 connected to a source 1021 of the access transistor 102.

An interconnection structure including a plurality of layers of interconnection lines and conductive pillars between the interconnection lines is formed in the first dielectric layer 120. In this embodiment, the interconnect structure includes a first layer of interconnect lines, which includes a bit line 121 and a word line 122, the bit line 121 is connected to the drain 1022 of the access transistor 102 through a conductive pillar 123, and the word line 122 is connected to the gate 1023 of the access transistor 102 through another conductive pillar 123; the capacitor 103 is connected to the source 1021 of the access transistor 102 through another conductive pillar 123.

The interconnect structure further includes a top interconnect line 124 connected to the bit line 121, the word line 122, and the upper plate of the capacitor 103 through conductive pillars 123, respectively.

In other embodiments of the present invention, the interconnect structure further includes three or more layers of interconnect lines, and each layer of interconnect lines is connected to each other through the conductive pillar.

the first dielectric layer 120 covers the entire memory array and the interconnect structure, and the first dielectric layer 120 may be a stacked structure including multiple sub-dielectric layers. In this embodiment, the material of the first dielectric layer 120 is silicon oxide.

A metal heat dissipation line 125 is further formed in the first dielectric layer 120. In this embodiment, the metal heat dissipation line 125 is located at the same layer as the top layer interconnection line 124, so that the metal heat dissipation line 125 can be formed at the same time as the top layer interconnection line 124 without adding an additional process step. The material of the metal heat dissipation line 125 is the same as that of the top layer interconnection line 124, and may be copper, silver, tungsten, or the like. The metal heat dissipation wires 125 are not electrically connected to the interconnect structure, and therefore, are electrically floating and do not cause parasitic capacitance.

The formation process of the top layer interconnection line 124 and the metal heat dissipation line 125 includes: forming a metal layer, and etching the metal layer to form a top interconnection line 124 and a metal heat dissipation line 125; a dielectric material layer covering the top interconnection line 124 and the metal heat dissipation line 125 is formed, and a chemical mechanical polishing process is used to planarize the dielectric material layer. The metal heat dissipation lines 125 may be formed at the positions where the density of the top layer interconnection lines 124 is small, so that the metal density distribution in the sub-dielectric layer where the top layer interconnection lines 124 and the metal heat dissipation lines 125 are located is uniform, and the problems of etching load and non-uniformity of the chemical mechanical polishing process caused by non-uniform metal distribution can be improved.

Referring to fig. 2A, a top view of the metal heat dissipation wire 125 is shown. In this embodiment, a plurality of metal heat dissipation lines 125 located in the same layer are formed in the first dielectric layer 120, and each of the metal heat dissipation lines 125 is in a long strip shape, and both ends of each of the metal heat dissipation lines extend to the edge of the first dielectric layer 120 and are exposed outside the first dielectric layer 120, so as to facilitate heat dissipation to the outside. In other embodiments, only one end of the metal heat dissipation line 125 may extend to the edge of the first dielectric layer 120.

In other embodiments, the metal heat dissipation wire 125 may also be curved to increase the length of the metal heat dissipation wire 125 and increase the heat dissipation area of the metal heat dissipation wire 125. The critical parameters such as the size of the metal heat dissipation line 125 and the distance between the metal heat dissipation line and the adjacent top interconnection line 124 satisfy the design rule of the memory formation process.

in other specific embodiments, when forming the interconnection lines of other layers of the interconnection structure, metal heat dissipation lines may be formed, so that metal heat dissipation lines are formed in the sub-dielectric layers where the at least two layers of interconnection lines are located, so as to increase the number of the metal heat dissipation lines and improve the heat dissipation effect.

The closer to the memory array, the greater the heat generated by the memory, so that the metal heat dissipation line 125 can be formed when forming the first layer of interconnect lines of the interconnect structure, and the metal heat dissipation line 125 is formed to be located in the same layer as the bit line 121 and the word line 122 and to be closer to the memory cell.

Please refer to fig. 2B, which is a schematic top view of a metal heat dissipation wire 125 according to another embodiment of the present invention. In this specific embodiment, the end of the metal heat dissipation line 125 is not directly exposed to the outside of the first dielectric layer 120, the end of the metal heat dissipation line 125 is covered with a protection layer 126, that is, the metal heat dissipation line is isolated from the outside of the memory by a protection layer 126, and the protection layer 126 is used to protect the metal heat dissipation line 125, so as to prevent the metal heat dissipation line 125 from being directly exposed to the air and being oxidized or corroded by water vapor in the air.

The protective layer 126 may be formed when forming a dielectric material covering the metal heat sink wires 125.

Referring to fig. 3, a second substrate 200 is provided, where the second substrate 200 includes a second substrate 210, a logic circuit formed on a front surface of the second substrate 210, and a second dielectric layer 220 covering the logic circuit.

The second substrate 210 is a semiconductor substrate, such as a monocrystalline silicon substrate, a silicon germanium substrate, a silicon on insulator substrate, or the like. The second substrate 210 has a shallow trench isolation structure STI therein.

The logic circuit mainly includes transistors, and in fig. 3, only a part of the transistors are illustrated as the logic circuit.

The second dielectric layer 220 is made of silicon oxide, an interconnection structure is formed in the second dielectric layer 220 and includes an interconnection line 221 and a conductive pillar 222, and the interconnection line 221 is correspondingly connected to a source, a drain and a gate of a transistor through the conductive pillar 222 to connect the transistors into a logic circuit.

In this embodiment, the interconnect structure in the second dielectric layer 220 includes only one layer of interconnect line, and in other embodiments, the interconnect structure may further include two or more layers of interconnect lines, where the layers of interconnect lines are connected by the conductive pillar.

A metal heat dissipation line 223 is further formed in the second dielectric layer 220. The metal heat dissipation line 223 can be formed at the same time when the interconnection line 221 is formed, and the metal heat dissipation line 223 is used for heat dissipation, and can also improve the metal distribution uniformity in a dielectric layer where the interconnection line 221 is located, and solve the problems of etching load effect and uneven chemical mechanical polishing caused by uneven metal distribution. At least one end of the metal heat dissipation line 223 extends to the edge of the second dielectric layer 220, and is exposed outside the memory or isolated from the outside of the memory by a protection layer 126.

In other embodiments, a metal heat sink line may be formed only within the first dielectric layer 120 or only within the second dielectric layer 120.

Referring to fig. 4, the first substrate 100 and the second substrate 200 are stacked and bonded.

In this embodiment, the first dielectric layer 120 and the second dielectric layer 220 are bonded to each other. The surfaces of the first dielectric layer 120 and the second dielectric layer 220 are modified into hydrophilic through hydrogen-containing plasma, hydrogen bonds are generated under certain temperature and pressure, bonding is completed, and a bonding interface is Si-O-Si bond bonding.

In this embodiment, when bonding the first substrate 100 and the second substrate 200, it is necessary to bring the first dielectric layer 120 into surface contact with the second dielectric layer 220 in an inert gas atmosphere, apply pressure to the first substrate 100 and the second substrate 200 to press the first substrate 100 and the second substrate 200, and heat the substrates at a temperature of 200 ℃ to 400 ℃ for 2h to 4 h. For example, the heating temperature may be 200 ℃, 250 ℃, 300 ℃, 350 ℃ or 400 ℃, and the heating time may be 2 hours, 3 hours or 4 hours. In this embodiment, by applying an external force to the first substrate 100 and the second substrate 200, the first substrate 100 and the second substrate 200 can be brought into close contact, and the bonding effect is good.

Before bonding, the back surface of the second substrate 210 of the second base 200 may be thinned. Since the logic circuit is formed in the second base 200, the size of the device in the logic circuit is generally large, and the influence on the device in the logic circuit is small in the process of thinning the back surface of the second substrate 210 by grinding and the like.

Referring to fig. 5, a deep via connection 310 is formed through the second substrate 200 and connected to the interconnect structure in the first substrate 100.

The deep via connection 310 penetrates through the second substrate 200 and simultaneously connects the top interconnection line 124 in the first dielectric layer 120 and the top interconnection line 221 in the second dielectric layer 220, thereby electrically connecting the memory array and the logic circuit. The method for forming the deep via connection part 310 includes: forming a deep via penetrating through the second substrate 200 to the top layer interconnect line 124, filling a metal material in the deep via, and planarizing to form the deep via connection portion 310.

In this embodiment, a pad 320 connected to the deep via connection 310 and a protection layer 330 flush with the surface of the pad 320 are formed on the back surface of the second substrate 210.

In this embodiment, it is preferable that the deep via connection part 310 is formed to penetrate the second substrate 200. Since the density of logic circuit devices in the second substrate 200 is generally lower than that of the memory array in the first substrate 100, the size of the deep via connection 310 can be increased, and the process difficulty of forming the deep via connection 310 can be reduced.

In other embodiments, a deep via connection 310 may be formed through the first substrate 100.

The front surface of the first base 100 is the surface of the first dielectric layer 120, the front surface of the second base 200 is the surface of the second dielectric layer 220, and the back surface of the first base 100 is the other side surface of the first substrate 110 opposite to the first dielectric layer 120, that is, the back surface of the first substrate 110; the back surface of the second base 200 is the other side surface of the second substrate 210 opposite to the second dielectric layer 220, that is, the back surface of the second substrate 210. In other specific embodiments, the bonding between the first substrate 100 and the second substrate 200 may also be achieved by bonding the back surfaces of the first substrate 100 and the second substrate 200 to each other; or the first dielectric layer 120 is bonded and connected with the back surface of the second substrate 200; or the second dielectric layer 220 is bonded to the back surface of the first substrate 100.

In other specific embodiments, the surfaces of the first dielectric layer 120 and the second dielectric layer 220 may both expose a part of the surface of the interconnect structure, when the first substrate 100 and the second substrate 200 are bonded and connected, a hybrid bonding process is adopted, the surfaces of the interconnect structure are bonded and connected by using metal, the first dielectric layer 120 and the second dielectric layer 220 are bonded and connected by using dielectric layers, and when the first substrate 100 and the second substrate 200 are bonded, the electrical connection between the interconnect structures in the first substrate 100 and the second substrate 200 is realized, so that the electrical connection between the logic circuit and the memory array is realized.

According to the forming method of the memory, the memory array and the logic circuit of the memory are respectively formed in the two substrates, and the substrates of the memory array and the logic circuit are stacked in a stacking bonding mode, so that the memory density of the memory in a unit area can be improved. Furthermore, a metal radiating line is formed in the dielectric layer of at least one substrate, and the metal radiating line radiates outwards, so that the problem of overlarge heat inside the memory caused by substrate stacking is avoided.

Furthermore, the metal heat dissipation wire can be formed simultaneously with the interconnection wire in the interconnection structure in the substrate, so that additional process steps are not needed, and the process cost is not increased; and the positions of the metal heat dissipation wires can be set according to the distribution density of the interconnection wires, so that the metal distribution uniformity in the metal layer is improved, the etching load effect is improved, and the uniformity of chemical mechanical polishing is improved.

The utility model discloses a concrete implementation way still provides the memory that adopts above-mentioned method to form.

Please refer to fig. 5, which is a schematic structural diagram of a memory according to an embodiment of the present invention.

The memory includes: a first substrate 100, where the first substrate 100 includes a first substrate 110, a memory array formed on a front surface of the first substrate 110, and a first dielectric layer 120 covering the memory array; a second substrate 200, wherein the second substrate 200 includes a second substrate 210, a logic circuit formed on a front surface of the second substrate 210, and a second dielectric layer 220 covering the logic circuit.

The first substrate 110 is a semiconductor substrate, such as a monocrystalline silicon substrate, a silicon germanium substrate, a silicon on insulator substrate, or the like. The first substrate 110 has a shallow trench isolation structure STI therein.

In this specific embodiment, the memory array is a DRAM memory array, and the DRAM memory array is composed of a plurality of DRAM memory cells. The DRAM memory cell includes: an access transistor 102 formed on the first substrate 110, and a capacitor 103 connected to a source 1021 of the access transistor 102.

An interconnection structure is formed in the first dielectric layer 120, and the interconnection structure includes a plurality of layers of interconnection lines and conductive pillars between the interconnection lines. In this embodiment, the interconnect structure includes a first layer of interconnect lines, which includes a bit line 121 and a word line 122, the bit line 121 is connected to the drain 1022 of the access transistor 102 through a conductive pillar 123, and the word line 122 is connected to the gate 1023 of the access transistor 102 through the conductive pillar 123; the capacitor 103 is connected to the source 1021 of the access transistor 102 through a conductive pillar 123.

The interconnect structure in the first dielectric layer 120 further includes a top layer interconnect 124 connected to the bit line 121, the word line 122 and the upper plate of the capacitor 103 through the conductive pillar 123, respectively. In other embodiments of the present invention, the interconnect structure further includes three or more layers of interconnect lines, and each layer of interconnect lines is connected to each other through the conductive pillar.

The second substrate 210 is a semiconductor substrate, such as a monocrystalline silicon substrate, a silicon germanium substrate, a silicon on insulator substrate, or the like. The second substrate 210 has a shallow trench isolation structure STI therein. The logic circuit mainly includes transistors, and in fig. 5, only a part of the transistors are illustrated as the logic circuit.

The second dielectric layer 220 is made of silicon oxide, an interconnection structure is formed in the second dielectric layer 220 and includes an interconnection line 221 and a conductive pillar 222, and the interconnection line 221 is correspondingly connected to a source, a drain and a gate of a transistor through the conductive pillar 222 to connect the transistors into a logic circuit. In this embodiment, the interconnect structure in the second dielectric layer 220 includes only one layer of interconnect line, and in other embodiments, the interconnect structure may further include two or more layers of interconnect lines, where the layers of interconnect lines are connected by the conductive pillar.

The first substrate 100 and the second substrate 200 are stacked and bonded, and in this embodiment, the first dielectric layer 110 and the second dielectric layer 210 are bonded on the surface. In other embodiments, other bonding methods may be used between the first substrate 100 and the second substrate 200. For example, the bonding between the first substrate 100 and the second substrate 200 may also be achieved by bonding the back surfaces of the first substrate 100 and the second substrate 200 to each other; or the first dielectric layer 120 is bonded and connected with the back surface of the second substrate 200; or the second dielectric layer 220 is bonded to the back surface of the first substrate 100.

The memory further comprises a metal heat dissipation line located in the first dielectric layer 110 and/or the second dielectric layer 220. In this embodiment, a metal heat dissipation line 125 is formed in the first dielectric layer 110, and the metal heat dissipation line 125 and the top interconnection line 124 in the first dielectric layer 110 are located in the same layer; a metal heat dissipation line 223 is formed in the second dielectric layer 210, and the metal heat dissipation line 223 and the top interconnection line 221 in the second dielectric layer 210 are located at the same layer.

At least one end of the metal heat dissipation wires 223 and 125 extends to the edge of the memory to be exposed outside the memory to dissipate heat inside the memory to the outside. Preferably, in order to protect the metal heat dissipation wires 223 and 125, the ends of the metal heat dissipation wires 223 and 125 may be isolated from the outside of the memory by a protective layer covering the ends of the metal heat dissipation wires. The protective layer can be a silicon oxide layer or a silicon nitride layer, and the thickness of the protective layer is smaller so as to avoid influencing the heat dissipation efficiency of the metal heat dissipation wire.

The memory further includes a deep via connection 310 penetrating the second substrate 200 and connected to an interconnect structure in the first substrate 100. The deep via connection 310 connects the top level interconnect 124 in the first dielectric layer 120 and the top level interconnect 221 in the second dielectric layer 220 at the same time, thereby electrically connecting the memory array and the logic circuit.

The memory further includes a pad 320 on the back surface of the second substrate 210 connected to the deep via connection 310 and a protection layer 330 flush with the surface of the pad 320.

The memory array and the logic circuit of the memory are respectively formed in the two substrates, and the two substrates are connected in a stacking bonding mode, so that the memory density in a unit area can be improved. Furthermore, a metal radiating line is formed in the dielectric layer of at least one substrate, and the metal radiating line radiates outwards, so that the problem of overlarge heat inside the memory caused by substrate stacking is avoided.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.

Claims (9)

1. A memory, comprising:

The first base comprises a first substrate, a storage array formed on the front surface of the first substrate and a first dielectric layer covering the storage array;

The second base comprises a second substrate, a logic circuit formed on the front surface of the second substrate and a second dielectric layer covering the logic circuit;

The metal heat dissipation line is formed in the first dielectric layer and/or the second dielectric layer;

The first substrate and the second substrate are stacked and bonded.

2. the memory of claim 1, wherein the memory array is a DRAM memory array.

3. The memory of claim 1, wherein the first dielectric layer and the second dielectric layer each have an interconnect structure formed therein, the interconnect structure comprising a number of layers of interconnect lines.

4. The memory of claim 3, wherein the metal heat sink wire is located in the same layer as at least one layer of the interconnect wire.

5. The memory of claim 1, wherein at least one end of the metal heat spreader line extends to an edge of the memory and is separated from an exterior of the memory by a protective layer, the protective layer covering an end of the metal heat spreader line.

6. The memory of claim 1, wherein the first dielectric layer and the second dielectric layer are bonded with their surfaces facing each other.

7. The memory of claim 1, further comprising: and the deep through hole connecting part penetrates through the second substrate and is connected with the interconnection structure in the first substrate.

8. the memory of claim 7, further comprising: the welding pad is positioned on the back surface of the second substrate and connected with the deep through hole connecting part, and the protective layer covers the back surface of the second substrate and is flush with the surface of the welding pad.

9. The memory of claim 1, wherein the first substrate backside and the second substrate backside are bonded together; or the first dielectric layer is in opposite bonding connection with the back surface of the second substrate; or the second dielectric layer is oppositely bonded and connected with the back surface of the first substrate.