CN102122309B - Structural optimization method for large-array infrared detector containing bottom filling glue - Google Patents
Structural optimization method for large-array infrared detector containing bottom filling glue Download PDFInfo
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- CN102122309B CN102122309B CN201010591889A CN201010591889A CN102122309B CN 102122309 B CN102122309 B CN 102122309B CN 201010591889 A CN201010591889 A CN 201010591889A CN 201010591889 A CN201010591889 A CN 201010591889A CN 102122309 B CN102122309 B CN 102122309B
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Abstract
The invention relates to a structural optimization method for a large-array infrared detector containing bottom filling glue. By adopting the small-array equivalent large-array method, the requirement of device structure analysis on a simulation platform is reduced, the efficiency and the accuracy of the structure analysis are improved, and the designed detector has stronger structural stability and longer fatigue life.
Description
Technical field
The present invention relates to the infrared focal plane detector structural design, particularly a kind ofly contain the large area array infrared detector structural optimization method of filling glue in the end.
Background technology
The infrared focus plane Detection Techniques have the spectral response wide waveband, can work double tides etc. advantage and be widely used in that missile warning, information are scouted, damage recruitment evaluation and military and civilian fields such as farming, woods resource exploration.
Infrared focal plane detector is blended together through the indium post is interconnected by photosensitive element array chip and silicon sensing circuit by face-down bonding technique usually.The indium post not only provides the electricity of the photosensitive element array chip silicon sensing circuit input end corresponding with it to be communicated with, and also plays the mechanical support effect simultaneously.In order to improve the signal to noise ratio (S/N ratio) of infrared focal plane detector, infrared focal plane detector works in liquid nitrogen temperature usually.
In order to improve resolution; Require the array scale of detector increasing; The size of corresponding photosensitive element array chip also increases thereupon, because the difference of adjacent materials thermal expansivity, when liquid nitrogen temperature is worked; The thermal stress that is produced by thermal mismatching between them can cause indium post electrical connection inefficacy, and perhaps photosensitive element array chip is cracked, has had a strong impact on the life-span and the yield rate of infrared focal plane detector.Be electrically connected to lose efficacy for the indium post, solution comparatively commonly used is the epoxide-resin glue that filling contains the certain proportion silicon powder in the slit between infrared photosensitive element array chip and the silicon sensing circuit, is referred to as the end to fill glue.Fill glue and not only fill up the slit between infrared photosensitive element array chip and the silicon sensing circuit at the end, and surround the indium post array that connects photosensitive unit and silicon sensing circuit.The electrical connection that the end adding of filling glue has improved the indium post was lost efficacy; But its relatively large thermal expansivity; Add constraint to photosensitive element array chip; Cause that thermal stress sharply increases in the photosensitive element array chip, strengthened the cracked probability of photosensitive element array chip, seriously restricted the yield rate of large area array infrared detector.As shown in Figure 1, this detector manufacturing process is following: after making photosensitive element array chip 3 and silicon sensing circuit 1, mask respectively, on photosensitive element array chip 3 and silicon sensing circuit 1, deposit the indium thin layer respectively, thickness is the 3-15 micron; Float glue, peel off the indium post, form indium colonnade battle array 2, glue, photosensitive element array chip 3 attenuates in curing back, the ARC 4 of growing are filled in flip chip bonding, the filling end.
In the structural design of detector, need usually through analyzing the reliability of stress/strain assessment panel detector structure.The finite element analogy method is usually used in the structural stress analysis of the less flip chip bonding device of array scale.In order to improve the resolution of infrared focal plane detector, require the array scale of detector increasing, the quantity of corresponding photosensitive unit and indium post also is multiplied.The unit number of correspondingly in analytic process, dividing also sharply increases, and structure optimization speed reduces greatly, can not satisfy quick design requirement.
For instance, for the infrared focal plane detector of 128 * 128 scales, the quantity of indium post is 16384; If carrying out grid with 200 unit, divides on the indium post; The unit number of indium post will reach 3,280,000, even if by the symmetry of panel detector structure, adopt 1/8 structure to carry out modeling analysis; The unit number of being divided also will reach 1,600,000, and this does not also comprise the unit number of photosensitive element array chip and silicon sensing circuit.So many unit number requires very high to emulation platform, computation process is very slow, can not practical requirement.
Summary of the invention
The object of the present invention is to provide a kind of structural optimization method of large area array infrared detector, modeling unit is many in analyzing in order to solution large area array infrared detector structural stress, and the speed of finding the solution is slow, data storage takes up room greatly, aftertreatment many problems consuming time.
Be to realize above-mentioned purpose, scheme of the present invention is: a kind ofly contain the large area array infrared detector structural optimization method of filling glue in the end, it is characterized in that step is following:
A) the array scale
of the big face battle array infrared focal plane detector of basis; Confirm a less detector array scale
; Here
(n=1; 2,3 ...);
B) according to thermal expansion mismatch displacement formula between adjacent materials:
; And then set up the finite element model that is equivalent to
array scale infrared focal plane detector: photosensitive element array and indium post, the end in step a) said
the array scale panel detector structure, filled the thermal expansivity of glue difference increases
doubly, the distance of indium post weld spacing symcenter axle is
of
array scale in
array scale panel detector structure here; According to the symmetry of device architecture, adopt 1/8 structure to carry out modeling here;
In the following formula:
is the thermal expansion mismatch displacement; L is the distance of indium post weld spacing symcenter axle in the planar array detector;
and
is respectively the thermal expansivity of adjacent materials in the planar array detector; Adjacent materials is meant that said photosensitive element array and indium post, the end fill glue, and
is the cooling scope;
C)
the array scale detector finite element model to obtaining in the step b); Set the corresponding structure parameter, comprise the thickness of diameter, height and the photosensitive element array chip of indium post; Set material parameter and material analysis model;
D) carry out mesh of finite element and divide, adopt free grid dividing here;
E) confirm boundary condition and original state;
F) find the solution the structural stress of said
array scale detector, write down maximum stress and stress distribution on the photosensitive element array chip;
G) structural parameters of setting set-up procedure c); The thickness of the height of the diameter of indium post or indium post or photosensitive element array chip; Repeating step d) to f); Draw said
structural stress of array scale infrared focal plane detector and the relation between the structural parameters; Confirm the structural parameters that the minimum stress value is corresponding, promptly obtain the structure optimized parameter of
big battle array infrared focal plane detector of array scale.
The optimization method that adopts the present invention to propose has reduced the requirement of device architecture analysis to emulation platform, has improved the efficient and the accuracy rate of structure analysis, makes the panel detector structure stability of design stronger, fatigue lifetime is higher.
Further; In the step b); The difference of the said expansion coefficient that photosensitive element array and indium post, the end in
array scale detector model is filled glue increases
doubly; Be the thermal expansivity of fixing photosensitive element array chip, changing the end simultaneously fills the thermal expansivity of glue and indium post; Or fixedly fill the thermal expansivity of glue and indium post and change the thermal expansivity of photosensitive element array chip at the end.
Further, in the step a), n≤8.
Further, in the step a), n≤6.
Further, said photosensitive element array chip is indium antimonide (InSb) chip or mercury cadmium telluride (HgCdTe) chip or indium gallium arsenic (InGaAs) chip or indium arsenic antimony (InAsSb) chip or indium arsenic/gallium antimony (InAs/GaSb) chip or gallium arsenide/potassium arsenic aluminate (GaAs/AlGaAs) chip.
Description of drawings
Fig. 1 is the infrared focal plane detector structural representation.
Embodiment
Do further detailed explanation in the face of the present invention down.
Embodiment one
Photosensitive element array chip is indium antimonide (InSb) chip or mercury cadmium telluride (HgCdTe) chip or indium gallium arsenic (InGaAs) chip or indium arsenic antimony (InAsSb) chip or indium arsenic/gallium antimony (InAs/GaSb) chip or gallium arsenide/potassium arsenic aluminate (GaAs/AlGaAs) chip.Infrared focal plane detector to 64 * 64 array scales carries out structure optimization, and optimization step is following:
1. according to the array scale 64 * 64 of infrared focal plane detector to be optimized, confirm a less detector array scale; Can adopt 16 * 16 or 32 * 32, the more approaching array scale to be optimized of selected array scale, Optimization result is accurate more.Consider the optimal speed factor, we select 16 * 16 for use here.
2. according to the thermal expansion mismatch displacement formula:
, use the detector of face battle array equivalence 64 * 64 array scales of 16 * 16 array scales here.The difference that the thermal expansivity of glue is filled at adjacent materials with above-mentioned 16 * 16 battle array infrared focal plane detector models---photosensitive element array and indium post, the end increases by 3 times; And then foundation is equivalent to the infrared focal plane detector structural finite element model of 64 * 64 array scales; According to the symmetry of device architecture, adopt 1/8 structure to carry out modeling.Said 16 * 16 differences with the expansion coefficient of the adjacent materials in the array scale detector model increase by 3 times, are the thermal expansivity of fixing photosensitive element array chip, change the end simultaneously to fill the thermal expansivity of glue and indium post; Or fixedly fill the thermal expansivity of glue and indium post and change the thermal expansivity of photosensitive element array chip at the end.
In the following formula:
Be the thermal expansion mismatch displacement,
LBe the distance at indium post weld spacing face battle array center in the big planar array detector,
With
Be respectively the thermal expansivity of adjacent materials in the big planar array detector,
Be the cooling scope.Can know that according to following formula under the prerequisite that thermal shock cooling scope is confirmed, the thermal expansion mismatch displacement is proportional to the product of difference of distance and the adjacent materials thermal expansivity at weld spacing face battle array center.Concerning big planar array detector structural stress is analyzed; Photosensitive first number increases, and correspondingly increased the distance of weld spacing from the symcenter axle, and the difference of the thermal expansivity of adjacent materials remains unchanged; In order to obtain same effect; Also can reduce the size of detector and change thermal expansivity poor of adjacent materials, make generally that under above-mentioned two kinds of situation the product of the distance of weld spacing symcenter axle and the difference of adjacent materials thermal expansivity remains unchanged.
3. the finite element model that is equivalent to 64 * 64 array scales to obtaining in the step 2 in order to carry out structure optimization, needs to set relevant structural parameters, comprises the thickness of diameter, height and the photosensitive element array chip of indium post; Here the diameter of choosing the indium post is 30 microns, highly is 20 microns, and photosensitive element array chip thickness is 10 microns; Set material parameter and material analysis model: photosensitive element array chip and silicon sensing circuit material are regarded as the linear elasticity material, and the ess-strain behavior of indium post is described with the Anand model, and glue is filled with viscoelasticity MAXWELL model description in the end.
4. bring the said structure parameter into; Apply boundary condition and starting condition; Here boundary condition refers to locate to apply in the face of the title condition at the plane of symmetry (face ABCD and AEFD in like Fig. 1), and the lower surface central point (like D point among Fig. 1) to the silicon sensing circuit applies zero degree of freedom constraint simultaneously; Starting condition is that the temperature of entire device is a room temperature, and the temperature when cooling finishes is 77K.Carry out transient analysis and draw stress value and stress distribution on the photosensitive element array chip.Here utilize ANSYS software to carry out the structural stress analysis, concrete steps comprise: 1, set up working document name and work title, 2, the definition unit type; 3, definition material property parameter; 4, create geometric model, divide grid, 5, load and find the solution, 6, check solving result.
5. according to the structural parameters of setting described in existing machining precision, the difference set-up procedure 3; Comprise the diameter of indium post or the thickness of indium post height or photosensitive element array chip; During adjustment, only change structural parameters in indium column diameter or the height or the thickness of photosensitive element array chip, keep remaining structural parameters constant; Repeating step 4; Can draw the structural stress of 64 * 64 equivalent array scale infrared focal plane detectors and the relation between each structural parameters, confirm the structural parameters that the minimum stress value is corresponding, be the optimum structure parameter of these 64 * 64 battle array infrared focal plane detectors.
Infrared focal plane detector with 16 * 16 array scales equivalence, 64 * 64 array scales; Here the difference that the thermal expansivity of glue is filled at the adjacent materials of being selected for use---photosensitive element array and indium post, the end has increased by 3 times; Promptly be increased to 111.84e-6 by original 27.96e-6; Obviously compare with 64 * 64 battle array scales, 16 * 16 battle array scale size dimensions have reduced 3/4.Compare with the planar array detector structural stress analytic process that adopts the actual array scale; Method modeling area proposed by the invention has reduced 93.75%; Correspondingly unit number also sharply reduces; The face battle array scale of analyzing consuming time, memory data output and 16 * 16 is consistent, and does not increase with face battle array scale.
Embodiment two
Embodiment two, and the infrared focal plane detector of 128 * 128 array scales is carried out structure optimization, and is identical with embodiment one, simulates with the face battle array of 16 * 16 scales, and step is identical, repeats no more.
Planar array detector with structural simulation 128 * 128 scales of 16 * 16 scales: the difference that the thermal expansivity of glue is filled at the adjacent materials of being selected for use here---photosensitive element array and indium post, the end has increased by 7 times, promptly is increased to 223.68e-6 by original 27.96e-6.Aforementioned calculation utilizes structure simulation software ANSYS on workstation, to carry out.Compare with the planar array detector structural stress analytic process that adopts the actual array scale; Method modeling area proposed by the invention has reduced 98.4%; Correspondingly unit number also sharply reduces; The face battle array scale of analyzing consuming time, memory data output and 16 * 16 is consistent, and does not increase with face battle array scale.
Claims (5)
1. one kind contains the large area array infrared detector structural optimization method of filling glue in the end, it is characterized in that step is following:
A) according to the array scale M * M of big face battle array infrared focal plane detector, confirm a less detector array scale m * m, m=M/ (2n) here, n=1,2,3
B) according to thermal expansion mismatch displacement formula between adjacent materials: Δ y=L (α
1-α
2) Δ T; And then set up the finite element model that is equivalent to M * M array scale infrared focal plane detector: photosensitive element array and indium post in the said m of step a) * m array scale panel detector structure, the difference of filling the thermal expansivity of primer are increased 2n-1 doubly, and the distance of indium post weld spacing symcenter axle is 1/ (2n) of M * M array scale in m * m array scale panel detector structure here; According to the symmetry of device architecture, adopt 1/8 structure to carry out modeling here;
In the following formula: Δ y is the thermal expansion mismatch displacement, and L is the distance of indium post weld spacing symcenter axle in the planar array detector, α
1And α
2Be respectively the thermal expansivity of adjacent materials in the planar array detector, adjacent materials is meant said photosensitive element array and indium post, fills primer, and Δ T is the cooling scope;
C) m * m array scale detector finite element model to obtaining in the step b) is set the corresponding structure parameter, comprises the thickness of diameter, height and the photosensitive element array chip of indium post; Set material parameter and material analysis model;
D) carry out mesh of finite element and divide, adopt free grid dividing here;
E) confirm boundary condition and starting condition; Here boundary condition refers to apply in the face of the title condition at plane of symmetry place, and the lower surface central point to the silicon sensing circuit applies zero degree of freedom constraint simultaneously; Starting condition is that the temperature of entire device is a room temperature;
F) find the solution the structural stress of said m * m array scale detector, write down maximum stress and stress distribution on the photosensitive element array chip;
G) structural parameters of setting set-up procedure c); The thickness of the height of the diameter of indium post or indium post or photosensitive element array chip; Repeating step d) to f); Draw said m * structural stress of m array scale infrared focal plane detector and the relation between the structural parameters, confirm the structural parameters that the minimum stress value is corresponding, promptly obtain the structure optimized parameter of M * big battle array infrared focal plane detector of M array scale.
2. structural optimization method according to claim 1; It is characterized in that; In the step b); Said photosensitive element array and indium post in m * m array scale detector model, the difference of filling the expansion coefficient of primer being increased 2n-1 doubly, is the thermal expansivity of fixing photosensitive element array chip, changes the end simultaneously to fill the thermal expansivity of glue and indium post; Or fixedly fill the thermal expansivity of glue and indium post and change the thermal expansivity of photosensitive element array chip at the end.
3. structural optimization method according to claim 1 is characterized in that, in the step a), and n≤8.
4. structural optimization method according to claim 1 is characterized in that, in the step a), and n≤6.
5. according to claim 1 or 2 or 3 or 4 described optimization methods; It is characterized in that said photosensitive element array chip is indium antimonide (InSb) chip or mercury cadmium telluride (HgCdTe) chip or indium gallium arsenic (InGaAs) chip or indium arsenic antimony (InAsSb) chip or indium arsenic/gallium antimony (InAs/GaSb) chip or gallium arsenide/potassium arsenic aluminate (GaAs/AlGaAs) chip.
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| CN102682147B (en) * | 2011-12-22 | 2014-06-25 | 河南科技大学 | Structural modeling and structural optimization method for infrared area-array detector |
| CN102997998A (en) * | 2012-11-26 | 2013-03-27 | 河南科技大学 | Weak-deformation infrared focal plane detector |
| CN103633107B (en) * | 2013-12-16 | 2016-05-11 | 中国电子科技集团公司第四十四研究所 | Focus planardetector mounting structure |
| CN103761133B (en) * | 2014-01-22 | 2017-01-04 | 电子科技大学 | A kind of loading method based on ANSYS laminate structure primary stress |
| CN105651726A (en) * | 2015-12-01 | 2016-06-08 | 中国科学院上海技术物理研究所 | Method for optimizing curing temperature of low temperature underfill of infrared focal plane device |
| CN106505127A (en) * | 2016-10-26 | 2017-03-15 | 中国科学院半导体研究所 | The method for solving stress between quantum trap infrared detector array and reading circuit |
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| CN101183690A (en) * | 2007-12-13 | 2008-05-21 | 上海集成电路研发中心有限公司 | Infrared detector and method of producing the same |
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| CN101183690A (en) * | 2007-12-13 | 2008-05-21 | 上海集成电路研发中心有限公司 | Infrared detector and method of producing the same |
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| 刘士龙等.固化残余应力对倒装焊底充胶可靠性的影响.《电子工艺技术》.2002,第23卷(第6期),249-252. * |
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