CN102122309B - Structural optimization method for large-array infrared detector containing bottom filling glue - Google Patents

Structural optimization method for large-array infrared detector containing bottom filling glue Download PDF

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CN102122309B
CN102122309B CN201010591889A CN201010591889A CN102122309B CN 102122309 B CN102122309 B CN 102122309B CN 201010591889 A CN201010591889 A CN 201010591889A CN 201010591889 A CN201010591889 A CN 201010591889A CN 102122309 B CN102122309 B CN 102122309B
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indium
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孟庆端
张立文
张晓玲
普杰信
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Henan University of Science and Technology
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Abstract

本发明涉及一种含底充胶的大面阵红外探测器结构优化方法,采用小面阵等效大面阵的方法,降低了器件结构分析对仿真平台的要求,提高了结构分析的效率与准确率,使设计的探测器结构稳定性更强、疲劳寿命更高。

Figure 201010591889

The invention relates to a method for optimizing the structure of a large-area infrared detector with bottom-filling glue. The method of using a small-area array equivalent to a large-area array reduces the requirement for a device structure analysis on a simulation platform, and improves the efficiency and efficiency of structural analysis. The accuracy rate makes the designed detector more structurally stable and has a higher fatigue life.

Figure 201010591889

Description

A kind ofly contain the large area array infrared detector structural optimization method of filling glue in the end
Technical field
The present invention relates to the infrared focal plane detector structural design, particularly a kind ofly contain the large area array infrared detector structural optimization method of filling glue in the end.
Background technology
The infrared focus plane Detection Techniques have the spectral response wide waveband, can work double tides etc. advantage and be widely used in that missile warning, information are scouted, damage recruitment evaluation and military and civilian fields such as farming, woods resource exploration.
Infrared focal plane detector is blended together through the indium post is interconnected by photosensitive element array chip and silicon sensing circuit by face-down bonding technique usually.The indium post not only provides the electricity of the photosensitive element array chip silicon sensing circuit input end corresponding with it to be communicated with, and also plays the mechanical support effect simultaneously.In order to improve the signal to noise ratio (S/N ratio) of infrared focal plane detector, infrared focal plane detector works in liquid nitrogen temperature usually.
In order to improve resolution; Require the array scale of detector increasing; The size of corresponding photosensitive element array chip also increases thereupon, because the difference of adjacent materials thermal expansivity, when liquid nitrogen temperature is worked; The thermal stress that is produced by thermal mismatching between them can cause indium post electrical connection inefficacy, and perhaps photosensitive element array chip is cracked, has had a strong impact on the life-span and the yield rate of infrared focal plane detector.Be electrically connected to lose efficacy for the indium post, solution comparatively commonly used is the epoxide-resin glue that filling contains the certain proportion silicon powder in the slit between infrared photosensitive element array chip and the silicon sensing circuit, is referred to as the end to fill glue.Fill glue and not only fill up the slit between infrared photosensitive element array chip and the silicon sensing circuit at the end, and surround the indium post array that connects photosensitive unit and silicon sensing circuit.The electrical connection that the end adding of filling glue has improved the indium post was lost efficacy; But its relatively large thermal expansivity; Add constraint to photosensitive element array chip; Cause that thermal stress sharply increases in the photosensitive element array chip, strengthened the cracked probability of photosensitive element array chip, seriously restricted the yield rate of large area array infrared detector.As shown in Figure 1, this detector manufacturing process is following: after making photosensitive element array chip 3 and silicon sensing circuit 1, mask respectively, on photosensitive element array chip 3 and silicon sensing circuit 1, deposit the indium thin layer respectively, thickness is the 3-15 micron; Float glue, peel off the indium post, form indium colonnade battle array 2, glue, photosensitive element array chip 3 attenuates in curing back, the ARC 4 of growing are filled in flip chip bonding, the filling end.
In the structural design of detector, need usually through analyzing the reliability of stress/strain assessment panel detector structure.The finite element analogy method is usually used in the structural stress analysis of the less flip chip bonding device of array scale.In order to improve the resolution of infrared focal plane detector, require the array scale of detector increasing, the quantity of corresponding photosensitive unit and indium post also is multiplied.The unit number of correspondingly in analytic process, dividing also sharply increases, and structure optimization speed reduces greatly, can not satisfy quick design requirement.
For instance, for the infrared focal plane detector of 128 * 128 scales, the quantity of indium post is 16384; If carrying out grid with 200 unit, divides on the indium post; The unit number of indium post will reach 3,280,000, even if by the symmetry of panel detector structure, adopt 1/8 structure to carry out modeling analysis; The unit number of being divided also will reach 1,600,000, and this does not also comprise the unit number of photosensitive element array chip and silicon sensing circuit.So many unit number requires very high to emulation platform, computation process is very slow, can not practical requirement.
Summary of the invention
The object of the present invention is to provide a kind of structural optimization method of large area array infrared detector, modeling unit is many in analyzing in order to solution large area array infrared detector structural stress, and the speed of finding the solution is slow, data storage takes up room greatly, aftertreatment many problems consuming time.
Be to realize above-mentioned purpose, scheme of the present invention is: a kind ofly contain the large area array infrared detector structural optimization method of filling glue in the end, it is characterized in that step is following:
A) the array scale
Figure 669041DEST_PATH_IMAGE001
of the big face battle array infrared focal plane detector of basis; Confirm a less detector array scale
Figure 59571DEST_PATH_IMAGE002
; Here
Figure 137248DEST_PATH_IMAGE003
(n=1; 2,3 ...);
B) according to thermal expansion mismatch displacement formula between adjacent materials:
Figure 904216DEST_PATH_IMAGE004
; And then set up the finite element model that is equivalent to
Figure 383739DEST_PATH_IMAGE001
array scale infrared focal plane detector: photosensitive element array and indium post, the end in step a) said
Figure 945170DEST_PATH_IMAGE002
the array scale panel detector structure, filled the thermal expansivity of glue difference increases
Figure 41302DEST_PATH_IMAGE005
doubly, the distance of indium post weld spacing symcenter axle is
Figure 819268DEST_PATH_IMAGE006
of
Figure 86935DEST_PATH_IMAGE001
array scale in
Figure 221748DEST_PATH_IMAGE002
array scale panel detector structure here; According to the symmetry of device architecture, adopt 1/8 structure to carry out modeling here;
In the following formula: is the thermal expansion mismatch displacement; L is the distance of indium post weld spacing symcenter axle in the planar array detector;
Figure 121253DEST_PATH_IMAGE008
and is respectively the thermal expansivity of adjacent materials in the planar array detector; Adjacent materials is meant that said photosensitive element array and indium post, the end fill glue, and
Figure 478603DEST_PATH_IMAGE010
is the cooling scope;
C) the array scale detector finite element model to obtaining in the step b); Set the corresponding structure parameter, comprise the thickness of diameter, height and the photosensitive element array chip of indium post; Set material parameter and material analysis model;
D) carry out mesh of finite element and divide, adopt free grid dividing here;
E) confirm boundary condition and original state;
F) find the solution the structural stress of said
Figure 196209DEST_PATH_IMAGE002
array scale detector, write down maximum stress and stress distribution on the photosensitive element array chip;
G) structural parameters of setting set-up procedure c); The thickness of the height of the diameter of indium post or indium post or photosensitive element array chip; Repeating step d) to f); Draw said
Figure 504830DEST_PATH_IMAGE002
structural stress of array scale infrared focal plane detector and the relation between the structural parameters; Confirm the structural parameters that the minimum stress value is corresponding, promptly obtain the structure optimized parameter of
Figure 578966DEST_PATH_IMAGE001
big battle array infrared focal plane detector of array scale.
The optimization method that adopts the present invention to propose has reduced the requirement of device architecture analysis to emulation platform, has improved the efficient and the accuracy rate of structure analysis, makes the panel detector structure stability of design stronger, fatigue lifetime is higher.
Further; In the step b); The difference of the said expansion coefficient that photosensitive element array and indium post, the end in
Figure 871407DEST_PATH_IMAGE002
array scale detector model is filled glue increases
Figure 197346DEST_PATH_IMAGE005
doubly; Be the thermal expansivity of fixing photosensitive element array chip, changing the end simultaneously fills the thermal expansivity of glue and indium post; Or fixedly fill the thermal expansivity of glue and indium post and change the thermal expansivity of photosensitive element array chip at the end.
Further, in the step a), n≤8.
Further, in the step a), n≤6.
Further, said photosensitive element array chip is indium antimonide (InSb) chip or mercury cadmium telluride (HgCdTe) chip or indium gallium arsenic (InGaAs) chip or indium arsenic antimony (InAsSb) chip or indium arsenic/gallium antimony (InAs/GaSb) chip or gallium arsenide/potassium arsenic aluminate (GaAs/AlGaAs) chip.
Description of drawings
Fig. 1 is the infrared focal plane detector structural representation.
Embodiment
Do further detailed explanation in the face of the present invention down.
Embodiment one
Photosensitive element array chip is indium antimonide (InSb) chip or mercury cadmium telluride (HgCdTe) chip or indium gallium arsenic (InGaAs) chip or indium arsenic antimony (InAsSb) chip or indium arsenic/gallium antimony (InAs/GaSb) chip or gallium arsenide/potassium arsenic aluminate (GaAs/AlGaAs) chip.Infrared focal plane detector to 64 * 64 array scales carries out structure optimization, and optimization step is following:
1. according to the array scale 64 * 64 of infrared focal plane detector to be optimized, confirm a less detector array scale; Can adopt 16 * 16 or 32 * 32, the more approaching array scale to be optimized of selected array scale, Optimization result is accurate more.Consider the optimal speed factor, we select 16 * 16 for use here.
2. according to the thermal expansion mismatch displacement formula:
Figure 485108DEST_PATH_IMAGE011
, use the detector of face battle array equivalence 64 * 64 array scales of 16 * 16 array scales here.The difference that the thermal expansivity of glue is filled at adjacent materials with above-mentioned 16 * 16 battle array infrared focal plane detector models---photosensitive element array and indium post, the end increases by 3 times; And then foundation is equivalent to the infrared focal plane detector structural finite element model of 64 * 64 array scales; According to the symmetry of device architecture, adopt 1/8 structure to carry out modeling.Said 16 * 16 differences with the expansion coefficient of the adjacent materials in the array scale detector model increase by 3 times, are the thermal expansivity of fixing photosensitive element array chip, change the end simultaneously to fill the thermal expansivity of glue and indium post; Or fixedly fill the thermal expansivity of glue and indium post and change the thermal expansivity of photosensitive element array chip at the end.
In the following formula:
Figure 136669DEST_PATH_IMAGE012
Be the thermal expansion mismatch displacement, LBe the distance at indium post weld spacing face battle array center in the big planar array detector,
Figure 650827DEST_PATH_IMAGE008
With
Figure 46036DEST_PATH_IMAGE009
Be respectively the thermal expansivity of adjacent materials in the big planar array detector,
Figure 188304DEST_PATH_IMAGE010
Be the cooling scope.Can know that according to following formula under the prerequisite that thermal shock cooling scope is confirmed, the thermal expansion mismatch displacement is proportional to the product of difference of distance and the adjacent materials thermal expansivity at weld spacing face battle array center.Concerning big planar array detector structural stress is analyzed; Photosensitive first number increases, and correspondingly increased the distance of weld spacing from the symcenter axle, and the difference of the thermal expansivity of adjacent materials remains unchanged; In order to obtain same effect; Also can reduce the size of detector and change thermal expansivity poor of adjacent materials, make generally that under above-mentioned two kinds of situation the product of the distance of weld spacing symcenter axle and the difference of adjacent materials thermal expansivity remains unchanged.
3. the finite element model that is equivalent to 64 * 64 array scales to obtaining in the step 2 in order to carry out structure optimization, needs to set relevant structural parameters, comprises the thickness of diameter, height and the photosensitive element array chip of indium post; Here the diameter of choosing the indium post is 30 microns, highly is 20 microns, and photosensitive element array chip thickness is 10 microns; Set material parameter and material analysis model: photosensitive element array chip and silicon sensing circuit material are regarded as the linear elasticity material, and the ess-strain behavior of indium post is described with the Anand model, and glue is filled with viscoelasticity MAXWELL model description in the end.
4. bring the said structure parameter into; Apply boundary condition and starting condition; Here boundary condition refers to locate to apply in the face of the title condition at the plane of symmetry (face ABCD and AEFD in like Fig. 1), and the lower surface central point (like D point among Fig. 1) to the silicon sensing circuit applies zero degree of freedom constraint simultaneously; Starting condition is that the temperature of entire device is a room temperature, and the temperature when cooling finishes is 77K.Carry out transient analysis and draw stress value and stress distribution on the photosensitive element array chip.Here utilize ANSYS software to carry out the structural stress analysis, concrete steps comprise: 1, set up working document name and work title, 2, the definition unit type; 3, definition material property parameter; 4, create geometric model, divide grid, 5, load and find the solution, 6, check solving result.
5. according to the structural parameters of setting described in existing machining precision, the difference set-up procedure 3; Comprise the diameter of indium post or the thickness of indium post height or photosensitive element array chip; During adjustment, only change structural parameters in indium column diameter or the height or the thickness of photosensitive element array chip, keep remaining structural parameters constant; Repeating step 4; Can draw the structural stress of 64 * 64 equivalent array scale infrared focal plane detectors and the relation between each structural parameters, confirm the structural parameters that the minimum stress value is corresponding, be the optimum structure parameter of these 64 * 64 battle array infrared focal plane detectors.
Infrared focal plane detector with 16 * 16 array scales equivalence, 64 * 64 array scales; Here the difference that the thermal expansivity of glue is filled at the adjacent materials of being selected for use---photosensitive element array and indium post, the end has increased by 3 times; Promptly be increased to 111.84e-6 by original 27.96e-6; Obviously compare with 64 * 64 battle array scales, 16 * 16 battle array scale size dimensions have reduced 3/4.Compare with the planar array detector structural stress analytic process that adopts the actual array scale; Method modeling area proposed by the invention has reduced 93.75%; Correspondingly unit number also sharply reduces; The face battle array scale of analyzing consuming time, memory data output and 16 * 16 is consistent, and does not increase with face battle array scale.
Embodiment two
Embodiment two, and the infrared focal plane detector of 128 * 128 array scales is carried out structure optimization, and is identical with embodiment one, simulates with the face battle array of 16 * 16 scales, and step is identical, repeats no more.
Planar array detector with structural simulation 128 * 128 scales of 16 * 16 scales: the difference that the thermal expansivity of glue is filled at the adjacent materials of being selected for use here---photosensitive element array and indium post, the end has increased by 7 times, promptly is increased to 223.68e-6 by original 27.96e-6.Aforementioned calculation utilizes structure simulation software ANSYS on workstation, to carry out.Compare with the planar array detector structural stress analytic process that adopts the actual array scale; Method modeling area proposed by the invention has reduced 98.4%; Correspondingly unit number also sharply reduces; The face battle array scale of analyzing consuming time, memory data output and 16 * 16 is consistent, and does not increase with face battle array scale.

Claims (5)

1.一种含底充胶的大面阵红外探测器结构优化方法,其特征在于,步骤如下:1. A method for optimizing the structure of a large area array infrared detector with bottom filling, characterized in that the steps are as follows: a)根据大面阵红外焦平面探测器的阵列规模M×M,确定一个较小的探测器阵列规模m×m,这里m=M/(2n),n=1,2,3…;a) According to the array size M×M of the large area array infrared focal plane detector, determine a smaller detector array size m×m, where m=M/(2n), n=1,2,3…; b)根据相邻材料间热膨胀失配位移公式:Δy=L(α12)ΔT,进而建立起等效于M×M阵列规模红外焦平面探测器的有限元模型:将步骤a)所述m×m阵列规模探测器结构中光敏元阵列与铟柱、充底胶的热膨胀系数之差增加2n-1倍,这里m×m阵列规模探测器结构中铟柱焊点距对称中心轴的距离为M×M阵列规模的1/(2n);根据器件结构的对称性,这里采用1/8结构进行建模;b) According to the thermal expansion mismatch displacement formula between adjacent materials: Δy=L(α 12 )ΔT, and then establish a finite element model equivalent to an M×M array-scale infrared focal plane detector: Step a) In the m×m array-scale detector structure, the difference between the thermal expansion coefficient of the photosensitive element array, the indium column, and the bottom glue is increased by 2n-1 times, where the indium column solder joints in the m×m array-scale detector structure are separated from the symmetry central axis The distance is 1/(2n) of the M×M array scale; according to the symmetry of the device structure, a 1/8 structure is used here for modeling; 上式中:Δy为热膨胀失配位移,L为面阵探测器中铟柱焊点距对称中心轴的距离,α1和α2分别为面阵探测器中相邻材料的热膨胀系数,相邻材料是指所述光敏元阵列与铟柱、充底胶,ΔT为降温范围;In the above formula: Δy is the thermal expansion mismatch displacement, L is the distance between the indium column solder joint in the area array detector and the symmetry central axis, α 1 and α 2 are the thermal expansion coefficients of the adjacent materials in the area array detector, and the adjacent The material refers to the photosensitive element array, the indium column, and the bottom glue, and ΔT is the cooling range; c)对步骤b)中得到的m×m阵列规模探测器有限元模型,设定相应的结构参数,包括铟柱的直径、高度和光敏元阵列芯片的厚度;设定材料参数和材料分析模型;c) For the m×m array-scale detector finite element model obtained in step b), set corresponding structural parameters, including the diameter and height of the indium column and the thickness of the photosensitive element array chip; set material parameters and material analysis model ; d)进行有限元网络划分,这里采用自由网格划分;d) Carry out finite element network division, adopt free grid division here; e)确定边界条件和初始条件;这里边界条件指在对称面处施加面对称条件,同时对硅读出电路的下表面中心点施加零自由度约束;初始条件为整个器件的温度为室温;e) Determining boundary conditions and initial conditions; boundary conditions here refer to imposing surface symmetry conditions at the symmetry plane, and simultaneously applying a zero degree of freedom constraint to the center point of the lower surface of the silicon readout circuit; the initial conditions are that the temperature of the entire device is room temperature; f)求解所述m×m阵列规模探测器的结构应力,记录光敏元阵列芯片上的最大应力和应力分布;f) solving the structural stress of the m×m array-scale detector, and recording the maximum stress and stress distribution on the photosensitive element array chip; g)调整步骤c)中所述设定的结构参数,铟柱的直径、或铟柱的高度、或光敏元阵列芯片的厚度,重复步骤d)到f),得出所述m×m阵列规模红外焦平面探测器的结构应力与结构参数之间的关系,确定最小应力值对应的结构参数,即得到M×M阵列规模大面阵红外焦平面探测器的结构最优参数。g) Adjust the structural parameters set in step c), the diameter of the indium column, or the height of the indium column, or the thickness of the photosensitive element array chip, and repeat steps d) to f) to obtain the m×m array The relationship between the structural stress and the structural parameters of the large-scale infrared focal plane detector is determined, and the structural parameters corresponding to the minimum stress value are determined, that is, the optimal structural parameters of the M×M array large-scale infrared focal plane detector are obtained. 2.根据权利要求1所述的结构优化方法,其特征在于,步骤b)中,所述将m×m阵列规模探测器模型中光敏元阵列与铟柱、充底胶的膨胀系数之差增加2n-1倍,是固定光敏元阵列芯片的热膨胀系数,同时改变底充胶和铟柱的热膨胀系数;或者是固定底充胶和铟柱的热膨胀系数而改变光敏元阵列芯片的热膨胀系数。2. The structure optimization method according to claim 1, characterized in that, in step b), the difference between the expansion coefficients of the photosensitive element array, the indium column, and the bottom glue in the m×m array scale detector model is increased 2n-1 times is to fix the thermal expansion coefficient of the photosensitive element array chip and change the thermal expansion coefficient of the underfill glue and the indium column at the same time; or fix the thermal expansion coefficient of the underfill glue and the indium column and change the thermal expansion coefficient of the photosensitive element array chip. 3.根据权利要求1所述的结构优化方法,其特征在于,步骤a)中,n≤8。3. The structure optimization method according to claim 1, characterized in that, in step a), n≤8. 4.根据权利要求1所述的结构优化方法,其特征在于,步骤a)中,n≤6。4. The structure optimization method according to claim 1, characterized in that, in step a), n≤6. 5.根据权利要求1或2或3或4所述的优化方法,其特征在于,所述光敏元阵列芯片为锑化铟(InSb)芯片或碲镉汞(HgCdTe)芯片或铟镓砷(InGaAs)芯片或铟砷锑(InAsSb)芯片或铟砷/镓锑(InAs/GaSb)芯片或镓砷/铝镓砷(GaAs/AlGaAs)芯片。5. The optimization method according to claim 1 or 2 or 3 or 4, wherein the photosensitive element array chip is an indium antimonide (InSb) chip or a mercury cadmium telluride (HgCdTe) chip or an indium gallium arsenide (InGaAs ) chips or indium arsenic antimony (InAsSb) chips or indium arsenic/gallium antimony (InAs/GaSb) chips or gallium arsenic/aluminum gallium arsenic (GaAs/AlGaAs) chips.
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CN102682147B (en) * 2011-12-22 2014-06-25 河南科技大学 Structural modeling and structural optimization method for infrared area-array detector
CN102997998A (en) * 2012-11-26 2013-03-27 河南科技大学 Weak-deformation infrared focal plane detector
CN103633107B (en) * 2013-12-16 2016-05-11 中国电子科技集团公司第四十四研究所 Focus planardetector mounting structure
CN103761133B (en) * 2014-01-22 2017-01-04 电子科技大学 A kind of loading method based on ANSYS laminate structure primary stress
CN105651726A (en) * 2015-12-01 2016-06-08 中国科学院上海技术物理研究所 Method for optimizing curing temperature of low temperature underfill of infrared focal plane device
CN106505127A (en) * 2016-10-26 2017-03-15 中国科学院半导体研究所 Method for Solving Stress Between Quantum Well Infrared Detector Array and Readout Circuit

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