CN101937907A - Chip stacking package structure and manufacture method thereof - Google Patents
Chip stacking package structure and manufacture method thereof Download PDFInfo
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- CN101937907A CN101937907A CN200910151818.2A CN200910151818A CN101937907A CN 101937907 A CN101937907 A CN 101937907A CN 200910151818 A CN200910151818 A CN 200910151818A CN 101937907 A CN101937907 A CN 101937907A
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- chip
- radiator structure
- groove
- chipset
- stack package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a chip stacking package structure. The structure comprises a plurality of chip groups, a radiating device, a substrate, a circuit board and a plurality of solder balls, wherein the chip groups are stacked together, and each chip group comprises a radiation structure and a chip; the radiating structure comprises a chip accommodating groove, a plurality of through holes which are distributed in the chip accommodating groove and an extending part which extends outward from the chip accommodating groove; the chips are arranged in the chip accommodating groove, and are provided with a plurality of bumps; each bump is correspondingly arranged in one through hole of the radiating structure; the extending part of the radiating structure of each chip group is contacted with the extending part of the radiating structure of the adjacent chip group; the radiation device is positioned on the top of the chip group; the substrate is positioned at the bottom of the chip group; the circuit board is positioned under the substrate; and the solder balls are positioned between the circuit board and the substrate. The invention also provides a method for manufacturing the chip stacking package structure.
Description
Technical field
The present invention relates to a kind of chip stack package structure and preparation method thereof.
Background technology
In information society now, the user pursues high-speed, high-quality, polyfunctional electronic product.With regard to product appearance, the design of electronic product is to stride forward towards light, thin, short, little trend.In order to achieve the above object, recently develop and a kind of multi-core encapsulation module, just the chip with a plurality of difference in functionalitys or identical function is packaged on the same carrier (carrier) in the lump, and carrier for example is substrate or lead frame, and sees through carrier and external circuit electric connection.Therefore, multi-core encapsulation module has transmission speed faster, shorter transmission path and better electrical characteristic, and further dwindle the size and the area of chip-packaging structure, thereby make multicore sheet encapsulation technology be widely used among the various electronic products, and become following main product.
Chip stack package structure (stacked-chip packaging structure) promptly is to utilize multicore sheet encapsulation technology that a plurality of chips or passive component are disposed on the same carrier in the mode of piling up.Figure 1A illustrates known utilize perforation and projection and does the profile of the chip stack package structure of interconnection, and Figure 1B illustrates the surface temperature distribution figure of the chip stack package structure of Figure 1A.Please be simultaneously with reference to Figure 1A and Figure 1B, known chip-stacked mode mainly is that a plurality of chips 110 are stacked, and these chips 110 are disposed on the substrate 120, these chips 110 can see through a plurality of perforation 140 and projections 130 that are disposed at therebetween and electrically connect mutually.
Yet, when chip 110 in when running, if produce on the specific region of chip 110 when hot, the most of chip 110 that sees through of heat energy itself carries out heatsink transverse, because the heat-sinking capability of air between chip 110 and the chip 110 and projection 130 is relatively poor, therefore form bigger thermal resistance in vertical direction.Just on chip 110, produce easily the higher focus (hot spot) of temperature, and focus is easy to generate problems of excessive heat and damage chip 110 and produce thermal stress at projection 130, so that influence the reliability of chip stack package structure 100.
Summary of the invention
The invention provides a kind of chip stack package structure, the radiator structure of its chipset can be used for the multiple heat dissipation path of vertical heat transfer and horizontal heat conduction.
The present invention proposes a kind of chip stack package structure and comprises a plurality of chipsets, heat abstractor, substrate, circuit board and a plurality of soldered ball, and wherein chipset is stacked each other, and each chipset comprises radiator structure and chip.Radiator structure has chip and puts groove, is distributed in the interior a plurality of perforations of chip storing groove and puts the outward extending extension of groove from chip.Chip is arranged at chip and puts in the groove, has a plurality of projections on the chip, and each projection correspondence is arranged in the wherein perforation of radiator structure.The extension of the radiator structure of each chipset contacts with the extension of the radiator structure of the chipset of adjacency.Heat abstractor is positioned at the top of chipset.Substrate is positioned at the bottom of chipset.Circuit board is positioned at the below of substrate.Soldered ball is between circuit board and substrate.
The present invention proposes a kind of chip stack package structure and comprises first chipset, at least one second chipset, heat abstractor, substrate, bottom radiator structure, circuit board and a plurality of soldered ball.First chipset comprises first radiator structure and first chip.First radiator structure has first chip and puts groove and put outward extending first extension of groove from first chip.First chip is arranged at first chip and puts in the groove.Second chipset is stacked in the below of first chipset, wherein each second chipset comprises second radiator structure and at least one second chip, and second radiator structure has second chip and puts groove, is distributed in the interior a plurality of perforations of second chip storing groove and puts outward extending second extension of groove from second chip.Second chip is arranged at second chip and puts in the groove, has a plurality of projections at least one second chip, and each projection correspondence is arranged in the wherein perforation of second radiator structure.First extension of first radiator structure contacts with second extension of second radiator structure of at least one second chipset of adjacency.Heat abstractor is positioned at the top of first chipset.Substrate is positioned at the bottom of at least one second chipset.The bottom radiator structure is between substrate and at least one second chipset.Circuit board is positioned at the below of substrate.Soldered ball is between circuit board and substrate.
It is as described below that the present invention proposes a kind of manufacture method of chip stack package structure.At first, provide wafer, have a plurality of chips, perforation and many interlaced precut roads on the wafer.Then, provide radiator structure, it has main body, many interlaced strip projected parts portions and a plurality of groove, and the bottom of groove has a plurality of perforations.Then, on the chip of wafer, form a plurality of projections.Afterwards, radiator structure and wafer set are lumped together, wherein the strip projected parts portion of radiator structure is positioned at the precut road on the wafer, and the projection on the chip penetrates the perforation of radiator structure.Then, wafer is carried out polish process, so that the strip projected parts portion of radiator structure comes out.Then, precut certainly road carries out cutting process, to form a plurality of chipsets.Afterwards, chipset is stacked.Then, with the chipset configuration that is stacked on substrate.
Based on above-mentioned, radiator structure of the present invention has conductive structure and the peripheral extension between each chip, therefore, the focus diffusion that each chip can be produced owing to heating is inhomogeneous, extension is horizontal to conduct heat and vertical heat transfer and the heat that entire chip produces also can see through.Thus, radiator structure can come the thermal diffusion that chip produced and conduct to the heat abstractor of chipset top and the substrate of chipset below effectively.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A illustrates the profile of known chip stack package structure, and Figure 1B illustrates the surface temperature distribution figure of the chip stack package structure of Figure 1A.
Fig. 2 A illustrates the profile of the chip stack package structure of the embodiment of the invention, and Fig. 2 B illustrates the vertical view of the radiator structure of Fig. 2 A.
Fig. 3 illustrates the surface temperature distribution figure of the chip stack package structure of Fig. 2 A.
Fig. 4 and Fig. 5 illustrate two kinds of variation structures of the chip stack package structure of Fig. 2 A respectively.
Fig. 6 illustrates the profile of the chip stack package structure of the embodiment of the invention.
Fig. 7 A～Fig. 7 E illustrates the process section of the chip stack package structure of the embodiment of the invention.
Description of reference numerals
110,214,712: chip
120,230,640,740: substrate
130,216,626, A: projection
140,212b, 622b, 712a, 726b: perforation
200,400,500,600: chip stack package structure
210,730: chipset
212,720: radiator structure
212a: chip is put groove
212c: extension
212d, 212e, 622d, 622e, 716: surface
212f: interlayer portion
214a: conductive channel
214b: through hole
214c: electric conducting material
220,630: heat abstractor
240,660: circuit board
242: ground mat
243: the wiring board perforation
244: copper foil layer
250,670: soldered ball
262,264,682,684,750: adhesion coating
270,690,760: padded coaming
410: the bottom radiator structure
412: substrate is put groove
414: opening
416: the outer edge
418a, 418b: a side
420: knitting layer
510: encapsulating structure
512,612: the first radiator structures
512a, 612a: first chip is put groove
512b: first perforation
512c, 612b: first extension
514,614: the first chips
516: the first substrates
610: the first chipsets
620: the second chipsets
622: the second radiator structures
622a: second chip is put groove
622c: second extension
624: the second chips
650: the bottom radiator structure
710: wafer
714: precut road
720a: radiator structure unit
722: main body
724: strip projected parts portion
726: groove
726a, B: bottom
G: gap
T: top
Embodiment
Fig. 2 A illustrates the profile of the chip stack package structure of the embodiment of the invention, and Fig. 2 B illustrates the vertical view of the radiator structure of Fig. 2 A.Fig. 3 illustrates the surface temperature distribution figure of the chip stack package structure of Fig. 2 A.
Please be simultaneously with reference to Fig. 2 A and Fig. 2 B, the chip stack package structure 200 of present embodiment comprises a plurality of chipsets 210, heat abstractor 220, substrate 230, circuit board 240 and a plurality of soldered ball 250.Chipset 210 is stacked each other, and each chipset 210 comprises radiator structure 212 and chip 214.
Radiator structure 212 has chip and puts groove 212a, is distributed in the interior a plurality of perforation 212b of chip storing groove 212a and puts the outward extending extension 212c of groove 212a from chip.In the present embodiment, the material of radiator structure 212 for example is a ceramic material, as aluminium oxide, aluminium nitride and carborundum etc., or metal material such as copper, aluminium etc., or semi-conducting material such as silicon etc.Chip 214 is arranged at chip and puts in the groove 212a, has a plurality of projections 216 on the chip 214, and each projection 216 correspondence is arranged in the wherein perforation 212b of radiator structure 212.Specifically, in the present embodiment, 214 designs with circuit and element (not illustrating) on the chip, and chip 214 optionally has a plurality of conductive channel 214a, and so-called conductive channel 214a is made of the electric conducting material 214c that is formed on the through hole 214b in the chip 214 and fill in the through hole 214b.Projection 216 on the chip 214 can be electrically connected to conductive channel 214a, can see through projection 216 between the chipset 210 and electrically connect mutually with conductive channel 214a.In the present embodiment, it is design upwards that chip is put groove 212a, therefore, and before above-mentioned each chip 214 not being stacked, be earlier chip 214 to be placed in chip respectively to put within the groove 212a, just can directly the radiator structure 212 that is equiped with chip 214 be stacked.
In the present embodiment, relative two surperficial 212d, the 212e of radiator structure 212 are last can respectively to dispose adhesion coating 262 and adhesion coating 264, to two adjacent chips 214, and then strengthen the bond strength between the chipset 210 and the reliability of chip stack package structure 200 with jointing radiating structure 212.More specifically, adhesion coating 262,264 lays respectively at upper surface 212d and the lower surface 212e of the 212f of interlayer portion, and can also more be arranged at the surface of extension 212c.Adhesion coating 262,264 is preferably selected sticky material with high-termal conductivity matter.In addition, in the present embodiment, padded coaming 270 can be set in perforation 212b, it is filled in the inwall and the clearance G between the projection 216 of perforation 212b, and to reduce the stress of projection 216, the material of padded coaming 270 for example is a polymer.
The extension 212c of the radiator structure 212 of each chipset 210 contacts with the extension 212c of the radiator structure 212 of the chipset 210 of adjacency.Heat abstractor 220 is positioned at the top T of chipset 210, and heat abstractor 220 for example is the heat dissipation metal fin.Substrate 230 is positioned at the bottom B of chipset 210.Circuit board 240 is positioned at the below of substrate 230.Soldered ball 250 is between circuit board 240 and substrate 230, to electrically connect circuit board 240 and substrate 230.Circuit board 240 has ground mat (or power source pad) 242, perforation 243 and copper foil layer 244 or the like element, and it is the element on the general known circuit board.
It should be noted that, radiator structure 212 is except having the 212f of interlayer portion between the chip 214, also has the extension 212c that is positioned at each chip 214 periphery, therefore, the heat that chip 214 produces can see through the horizontal heat conduction of the 212f of interlayer portion to this extension 212c, also can see through extension 212c vertical heat transfer.Thus, radiator structure 212 heat conduction that can effectively chip 214 be produced is to the heat abstractor 220 of chipset 210 tops and the substrate 230 of chipset 210 belows.Please refer to Fig. 3, as shown in Figure 3, when chip 214 adstante febres, the Temperature Distribution of chip stack package structure 200 quite evenly and not produces focus, and hence one can see that, and radiator structure 212 can reach the effect of the heat that even dispersed chip 214 produced really.
Fig. 4 and Fig. 5 illustrate two kinds of variation structures of the chip stack package structure of Fig. 2 A respectively.Please earlier with reference to Fig. 4, in the present embodiment, chip stack package structure 400 is similar to the chip stack package structure 200 shown in Fig. 2 A, the difference part is that chip stack package structure 400 also comprises bottom radiator structure 410, and it has substrate and puts groove 412, is distributed in substrate and puts a plurality of openings 414 in the groove 412 and put groove 412 outward extending outer edges 416 from substrate.Similarly, also can respectively dispose adhesion coating 262 and adhesion coating 264 on relative two surperficial 212d, the 212e of radiator structure 212, to two adjacent chips 214, and then strengthen the bond strength between the chipset 210 and the reliability of chip stack package structure 400 with jointing radiating structure 212.
More specifically, the outer edge 416 of bottom radiator structure 410 contacts with the extension 212c of the radiator structure 212 of chipset 210.Thus, the heat that produced of chip 214 can see through radiator structure 212 and conduct to substrate 230 and circuit board 240 with bottom radiator structure 410.In the present embodiment, bottom radiator structure 410 can be connected with the ground mat (or power source pad) 242 of circuit board 240, or sees through wiring board perforation 243, connects copper foil layer 244, is beneficial to the heat that chip 214 is produced is conducted in the external environment by circuit board 240.In addition, in the present embodiment, can between bottom radiator structure 410 and circuit board 240 knitting layer 420 be set, to circuit board 240, the material of knitting layer 420 can be the material with high thermal conductivity coefficient with engage base radiator structure 410.
According to another embodiment, please refer to Fig. 5, the chip stack package structure 500 of Fig. 5 is similar to the chip stack package structure 400 of Fig. 4, and the difference part is that chip stack package structure 500 also comprises the encapsulating structure 510 between circuit board 240 and substrate 230.In the present embodiment, encapsulating structure 510 comprises first radiator structure 512, first chip 514 and first substrate 516.It should be noted that in other embodiments the quantity of first radiator structure 512 and first chip 514 also can be a plurality of.Similarly, also can respectively dispose adhesion coating 262 and adhesion coating 264 on relative two surperficial 212d, the 212e of radiator structure 212, to two adjacent chips 214, and then strengthen the bond strength between the chipset 210 and the reliability of chip stack package structure 200 with jointing radiating structure 212.This adhesion coating 264 all belongs to it for heat-conducting glue etc. and equivalent link thereof.
In the chip stack package structure of above-mentioned Fig. 2 A, Fig. 4 and Fig. 5, chip putting groove 212a is design upwards, so the invention is not restricted to this.In other embodiment, the chip putting groove also can be downward design.
Fig. 6 illustrates the profile of the chip stack package structure of another embodiment of the present invention.Please refer to Fig. 6, the chip stack package structure 600 of present embodiment comprises first chipset 610, a plurality of second chipset 620, heat abstractor 630, substrate 640, bottom radiator structure 650, circuit board 660 and a plurality of soldered ball 670.
The first extension 612b of first radiator structure 612 contacts with the second extension 622c of second radiator structure 622 of second chipset 620 of adjacency.In the present embodiment, in the present embodiment, the material of radiator structure 212 for example is a ceramic material, as aluminium oxide, aluminium nitride and carborundum etc., or metal material such as copper, aluminium etc., or semi-conducting material such as silicon etc.First and second radiator structure 612,622 can be same material or different materials.
In the present embodiment, relative two surperficial 622d, the 622e of second radiator structure 622 are last can respectively to dispose adhesion coating 682 and adhesion coating 684, engaging second radiator structure 622 to 2 second adjacent chips 624 or on the first adjacent chip 614 and second chip 624, and then strengthen the bond strength between first and second chipset 610,620 and the reliability of chip stack package structure 600.In addition, in the present embodiment, padded coaming 690 can be set in perforation 622b, it is filled in the inwall and the clearance G between the projection 626 of perforation 622b, and to reduce the stress of projection 626, the material of padded coaming 690 for example is a polymer.
In other embodiments, chip stack package structure also can comprise another encapsulating structure (not illustrating), shown in the encapsulating structure of Fig. 5, it is between circuit board 660 and substrate 640, and chip stack package structure 600 is similar to the chip stack package structure 500 of Fig. 5 to the juncture of another encapsulating structure.
Fig. 7 A～Fig. 7 E illustrates the process section of the chip stack package structure of the embodiment of the invention.
At first, please refer to Fig. 7 A, wafer 710 is provided, have a plurality of chips 712 and many interlaced precut roads 714 on the wafer 710.Particularly, these precut roads 714 mark off these chips 712.On chip, have a plurality of perforation 712a, in the present embodiment, also can on the surface 716 of wafer 710, form adhesion coating 750.
Then, please referring again to Fig. 7 A, provide radiator structure 720, it has main body 722, many interlaced strip projected parts portions 724 and a plurality of groove 726, and the bottom 726a of groove 726 has a plurality of perforation 726b.Specifically, the Cutting Road 714 on the strip projected parts portion 724 corresponding wafers 710 of radiator structure 720, thereby the pattern of strip projected parts portion 724 is to design according to the position at Cutting Road 714 places with distributing.Chip 712 on the groove 726 corresponding wafers 710 of radiator structure 720, thereby groove 726 patterns are to design according to the position at chip 712 places.The perforation 726b of the bottom 726a of groove 726 designs according to the follow-up position that forms projection on chip 712.
Then, please refer to Fig. 7 B, on the chip 712 of wafer 710, form a plurality of projection A.Afterwards, radiator structure 720 and wafer 710 are combined, so that the strip projected parts portion 724 of radiator structure 720 is disposed in the precut road 714 on the wafer 710, each chip 712 correspondence is arranged in the wherein groove 726 of radiator structure 720, and the projection A on the chip 712 penetrates among the perforation 726b of radiator structure 720.Then, in the present embodiment, optionally in perforation 726b, insert padded coaming 760.
Then, please refer to Fig. 7 C, wafer 710 is carried out polish process, so that the strip projected parts portion 724 of radiator structure 720 comes out.Particularly, polish process is that the surface 718 (back side) of wafer 710 is ground, and till exposing strip projected parts portion 724, wherein surface 718 is with respect to surface 716 with the thickness that reduces wafer 710.
Then, please refer to Fig. 7 D-1, Fig. 7 D-2, precut certainly road 714 carries out cutting process, to form a plurality of chipsets 730.Particularly, when carrying out cutting process, be the strip projected parts portion 724 that cutting is arranged in precut road 714, to cut apart 720 one-tenth a plurality of radiator structures unit 720a of radiator structure, each chipset 730 all has radiator structure unit 720a.Afterwards, please refer to Fig. 7 E, chipset 730 is stacked, and the radiator structure unit 720a that adjacent chipset 730 is had contacts.Then, the chipset 730 that is stacked is disposed on the substrate 740.Afterwards, can on the chipset 730 of the top, design heat abstractor (shown in Fig. 2 A), and soldered ball and circuit board (shown in Fig. 2 A) or the like element is set in the below of substrate 740.
In sum, radiator structure of the present invention has conductive structure and the peripheral extension that is positioned at each chip chamber, so have a plurality of heat dissipation path, therefore the heat of chip generation not only can be carried out horizontal heat conduction through the conductive structure between chip of radiator structure and the extension of chip periphery, and also the conductive structure and the extension that can see through between each chip carry out vertical heat transfer.Thus, radiator structure can be effectively with heat conduction that chip produced to the heat abstractor of chipset top and the substrate of chipset below, even be transmitted to the circuit board of substrate below, thereby can effectively avoid producing on the chip focus.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.
Claims (21)
1. chip stack package structure comprises:
A plurality of chipsets are stacked each other, and each chipset comprises:
Radiator structure, its have chip put groove, be distributed in this chip put a plurality of perforations in groove, the interlayer portion between a plurality of perforations and certainly this chip put the outward extending extension of groove;
Chip is arranged at this chip and puts in the groove, has a plurality of projections on this chip, and each projection correspondence is arranged in the wherein perforation of this radiator structure,
Wherein, the extension of the radiator structure of each chipset contacts with the extension of the radiator structure of this chipset of adjacency;
Heat abstractor is positioned at the top of a plurality of chipsets;
Substrate is positioned at the bottom of this chipset;
Circuit board is positioned at the below of this substrate; And
A plurality of soldered balls are between this circuit board and this substrate.
2. chip stack package structure as claimed in claim 1 also comprises:
The bottom radiator structure, its have substrate put groove, be distributed in this substrate put in groove a plurality of openings and certainly this substrate put the outward extending outer edge of groove,
Wherein, this substrate is arranged at this substrate and puts in the groove, each soldered ball correspondence is arranged in the wherein opening of this bottom radiator structure, and the outer edge of this bottom radiator structure contacts with the extension of the radiator structure of this chipset of adjacency, and opposite side contacts with this circuit board.
3. chip stack package structure as claimed in claim 2 also comprises knitting layer, between this bottom radiator structure and this circuit board, to engage this bottom radiator structure to this circuit board.
4. chip stack package structure as claimed in claim 2 also comprises another encapsulating structure, between this circuit board and this substrate.
5. chip stack package structure as claimed in claim 4, wherein said encapsulating structure comprises:
At least one first radiator structure, its have first chip put groove, be distributed in this first put in chip groove a plurality of first perforations and certainly this first chip put outward extending first extension of groove;
At least one first chip is arranged in this first placement chip groove accordingly; And
First substrate is positioned at the bottom of this first chip,
Wherein, first extension of this first radiator structure contacts with the extension of the radiator structure of this chipset of adjacency.
6. chip stack package structure as claimed in claim 1 also comprises padded coaming, and it is arranged in a plurality of perforations, with the inwall that fills up a plurality of perforations and the gap between a plurality of projection.
7. chip stack package structure as claimed in claim 6, wherein the material of this padded coaming comprises polymer.
8. chip stack package structure as claimed in claim 1, wherein the material of this radiator structure comprises pottery, metal or semiconductor, and wherein pottery comprises aluminium oxide or aluminium nitride, and metal comprises copper or aluminium, and semiconductor comprises silicon.
9. chip stack package structure as claimed in claim 1, wherein each chipset also comprises at least one adhesion coating, its surface that is positioned at the upper surface of this interlayer portion of this radiator structure and lower surface and this extension at least one of them.
10. chip stack package structure as claimed in claim 1, wherein this chip has a plurality of through holes, and is filled with electric conducting material in a plurality of through hole, and constituting a plurality of conductive channels, and a plurality of conductive channel sees through a plurality of projections and adjacent chip electric connection.
11. a chip stack package structure comprises:
First chipset, it comprises:
First radiator structure, its have first chip put groove and certainly this first chip put outward extending first extension of groove;
First chip is arranged at this first chip and puts in the groove;
At least one second chipset is stacked in the below of this first chipset, and wherein this second chipset comprises:
Second radiator structure, its have second chip put groove, be distributed in this second chip put a plurality of perforations in groove, the interlayer portion between a plurality of perforations and certainly this second chip put outward extending second extension of groove;
Second chip is arranged at this second chip and puts in the groove, has a plurality of projections on this second chip, and each projection correspondence is arranged in the wherein perforation of this second radiator structure,
Wherein, first extension of this first radiator structure contacts with this second extension of this second radiator structure of this second chipset of adjacency;
Heat abstractor is positioned at the top of this first chipset;
Substrate is positioned at the bottom of this second chipset;
The bottom radiator structure is between this substrate and this second chipset;
Circuit board is positioned at the below of this substrate; And
A plurality of soldered balls are between this circuit board and this substrate.
12. chip stack package structure as claimed in claim 11 also comprises knitting layer, between this bottom radiator structure and this circuit board, to engage this bottom radiator structure to this circuit board.
13. chip stack package structure as claimed in claim 11 also comprises another encapsulating structure, between this circuit board and this substrate.
14. chip stack package structure as claimed in claim 11 also comprises padded coaming, is arranged in a plurality of perforations, with the inwall that fills up a plurality of perforations and the gap between a plurality of projection.
15. chip stack package structure as claimed in claim 14, wherein the material of this padded coaming comprises polymer.
16. chip stack package structure as claimed in claim 11, wherein the material of this radiator structure comprises pottery, metal or semiconductor, and wherein pottery comprises aluminium oxide or aluminium nitride, and metal comprises copper or aluminium, and semiconductor comprises silicon.
17. chip stack package structure as claimed in claim 11, wherein each second chipset also comprises at least one adhesion coating, the surface that is positioned at the upper surface of this interlayer portion and lower surface and this extension at least one of them.
18. chip stack package structure as claimed in claim 11, wherein this second chip has a plurality of through holes, and is filled with electric conducting material in a plurality of through hole, and constituting a plurality of conductive channels, and a plurality of conductive channel sees through a plurality of projections and adjacent chip electric connection.
19. the manufacture method of a chip stack package structure comprises:
Wafer is provided, has a plurality of chips, a plurality of through hole on this wafer and fill in electric conducting material in a plurality of through holes to constitute a plurality of conductive channels and many interlaced precut roads;
Radiator structure is provided, and it has main body, many interlaced strip projected parts portions and a plurality of groove, and the bottom of this groove has a plurality of perforations;
On a plurality of conductive channels of a plurality of chips of this wafer, form a plurality of projections;
This radiator structure and this wafer set are lumped together, and wherein a plurality of strip projected parts portion of this radiator structure is positioned at a plurality of precut road on this wafer, and a plurality of projections on a plurality of chip penetrate a plurality of perforations of this radiator structure;
This wafer is carried out polish process, so that a plurality of strip projected parts portion of this radiator structure comes out;
Carry out cutting process from a plurality of precut roads, to form a plurality of chipsets;
A plurality of chipsets are stacked; And
With a plurality of chipset configuration of being stacked on substrate.
20. the manufacture method of chip stack package structure as claimed in claim 19 also is included in a plurality of perforations after wherein this radiator structure and this wafer set being lumped together and inserts padded coaming.
21. the manufacture method of chip stack package structure as claimed in claim 20 before wherein this radiator structure and this wafer set being lumped together, also is included at least one surface of this radiator structure or this wafer and forms adhesion coating.
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| CN200910151818.2A CN101937907B (en) | 2009-06-29 | 2009-06-29 | Chip stacking package structure and manufacture method thereof |
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| CN102522380A (en) * | 2011-12-21 | 2012-06-27 | 华为技术有限公司 | PoP packaging structure |
| WO2012159533A1 (en) * | 2011-05-26 | 2012-11-29 | Huawei Technologies Co., Ltd. | Thermally enhanced stacked package and method |
| CN103378026A (en) * | 2012-04-16 | 2013-10-30 | 北京大学 | Three-dimensional packaging method having heat radiation function |
| CN103560117A (en) * | 2013-10-31 | 2014-02-05 | 中国科学院微电子研究所 | Heat dissipation structure for PoP encapsulation |
| CN103956346A (en) * | 2014-03-24 | 2014-07-30 | 中山新诺科技股份有限公司 | Heat dissipation method for manufacturing 3D packaging chip |
| CN104701292A (en) * | 2013-12-06 | 2015-06-10 | 上海北京大学微电子研究院 | Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages |
| CN107343376A (en) * | 2016-05-02 | 2017-11-10 | 意法半导体(格勒诺布尔2)公司 | Electronic equipment with electronic chip and radiator |
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| CN108520867A (en) * | 2018-04-19 | 2018-09-11 | 苏州通富超威半导体有限公司 | Encapsulating structure and welding method |
| CN111029304A (en) * | 2019-11-22 | 2020-04-17 | 中国电子科技集团公司第十三研究所 | Anti-vibration three-dimensional stacked circuit structure and preparation method thereof |
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| CN104701292A (en) * | 2013-12-06 | 2015-06-10 | 上海北京大学微电子研究院 | Method for collaboratively and optimally designing high-speed IC-QFN (integrated circuit-quad flat no-lead) packages |
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| CN107343376A (en) * | 2016-05-02 | 2017-11-10 | 意法半导体(格勒诺布尔2)公司 | Electronic equipment with electronic chip and radiator |
| CN107343376B (en) * | 2016-05-02 | 2019-12-17 | 意法半导体(格勒诺布尔2)公司 | electronic device with electronic chip and heat sink |
| CN107993988A (en) * | 2017-11-13 | 2018-05-04 | 芯原微电子(上海)有限公司 | A kind of laminated packaging structure and preparation method thereof |
| CN108520867A (en) * | 2018-04-19 | 2018-09-11 | 苏州通富超威半导体有限公司 | Encapsulating structure and welding method |
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| CN111029304B (en) * | 2019-11-22 | 2021-09-14 | 中国电子科技集团公司第十三研究所 | Anti-vibration three-dimensional stacked circuit structure and preparation method thereof |
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| WO2023029518A1 (en) * | 2021-09-06 | 2023-03-09 | 长鑫存储技术有限公司 | Semiconductor structure |
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