WO2023029518A1

WO2023029518A1 - Semiconductor structure

Info

Publication number: WO2023029518A1
Application number: PCT/CN2022/088429
Authority: WO
Inventors: 寗树梁; 何军; 刘杰; 应战
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-09-06
Filing date: 2022-04-22
Publication date: 2023-03-09
Also published as: CN115775778A

Abstract

Embodiments of the present disclosure relate to a semiconductor structure. The structure comprises: a first wafer, which is internally provided with a plurality of first chips; a second wafer, which is internally provided with a plurality of second chips, a first surface of the second wafer being connected to a first surface of the first wafer, and the second chips being electrically connected to the first chips; and a heat dissipation device, which is internally provided with a heat dissipation pipe, the heat dissipation device making contact with the second surface of the second wafer, and the second surface of the second wafer being oppositely arranged to the first surface of the second wafer. Heat generated in the working process of the first chips and the second chips can be dissipated by means of the heat dissipation pipe, thereby reducing the overall temperature of the semiconductor structure and prolonging the service life of the semiconductor structure.

Description

semiconductor structure

Cross References to Related Applications

This disclosure claims the priority of the Chinese patent application with the application number 202111039932.3 and the application name "Semiconductor Structure" filed with the China Patent Office on September 06, 2021, the entire content of which is incorporated by reference in this disclosure.

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure.

Background technique

With the advent of the era of 5G communication and artificial intelligence (AI), the amount of data to be transmitted, stored, and high-speed interactively processed by chips used in semiconductor devices in such related fields is very large, and a lot of heat will be generated during the working process of chips. This further affects the operation and lifespan of the semiconductor device, and how to quickly dissipate the heat generated during the operation of the semiconductor device has become an urgent problem to be solved.

Contents of the invention

According to various embodiments of the present disclosure, a semiconductor structure is provided.

According to some embodiments, the present disclosure provides a semiconductor structure, including a first wafer, a second wafer, and a heat dissipation device. The first wafer has a plurality of first chips; the second wafer has a plurality of second chips, and the second wafer has a plurality of second chips. The first surface of the second wafer is connected to the first surface of the first wafer, and the second chip is electrically connected to the first chip; a heat dissipation pipeline is arranged in the heat dissipation device; the heat dissipation device is in contact with the second surface of the second wafer , the second surface of the second wafer is opposite to the first surface of the second wafer.

According to some embodiments, the semiconductor structure further includes a first TSV and a connection device, the first TSV is located in the first wafer, one end of the first TSV is electrically connected to the first chip, and the first TSV The other end extends to the second surface of the first wafer, and the second surface of the first wafer is opposite to the first surface of the first wafer; the connection device is located on the second surface of the first wafer, and is connected to at least one first wafer. a TSV contact.

According to some embodiments, the semiconductor structure further includes a second through-silicon via, the second through-silicon via penetrates the first wafer and the second wafer along the direction in which the first wafer and the second wafer overlap, and is connected with the heat dissipation device. surfaces in contact.

According to some embodiments, the number of connection devices is not less than two, and the heat dissipated by the connection devices is proportional to the number of adjacent second TSVs.

According to some embodiments, the semiconductor structure further includes a heat conduction device, the heat conduction device is respectively in contact with the sidewalls of the first wafer and the second wafer, and is used for conducting heat from the first wafer to the second wafer.

According to some embodiments, the orthographic projection of the cooling pipe on the second wafer surrounds each second chip.

According to some embodiments, the surface of the heat dissipation device in contact with the second wafer is provided with several vacuum adsorption holes spaced apart from the heat dissipation pipeline, and the heat dissipation device is in adsorption contact with the second surface of the second wafer through the vacuum adsorption holes.

According to some embodiments, the heat dissipation pipeline is arranged around the vacuum suction hole.

According to some embodiments, the first chip includes a logic chip and the second chip includes a memory chip, or the first chip includes a memory chip and the second chip includes a logic chip.

According to some embodiments, the functional surface of the first chip is located on the first surface of the first wafer, and the functional surface of the second chip is located on the first surface of the second wafer.

According to some embodiments, the functional surface of the first chip is located on the second surface of the first wafer, and the functional surface of the second chip is located on the first surface of the second wafer.

According to some embodiments, the first surface of the first wafer is bonded to the first surface of the second wafer using a conductive bump bonding process or a fusion bonding process.

According to some embodiments, the surface of the heat dissipation device in contact with the second wafer is provided with a groove, the heat dissipation pipeline is located in the groove, and the heat dissipation pipeline is in contact with the second surface of the second wafer.

According to some embodiments, cooling liquid is contained in the heat dissipation pipeline, one end of the heat dissipation pipeline is an input end of the cooling liquid, and the other end of the heat dissipation pipeline is an output end of the cooling liquid.

According to some embodiments, the heat sink includes a metal plate, and the orthographic projection of the second wafer on the heat sink is located in a central area of the heat sink.

Embodiments of the present disclosure may/at least have the following advantages:

In the semiconductor structure provided by the embodiment of the present disclosure, the first surface of the second wafer is connected to the first surface of the first wafer, and the first chip in the first wafer and the second chip in the second wafer Electrically connected, the second surface of the second wafer is in contact with the heat sink, and the heat sink is provided with a heat dissipation pipeline, through which the heat generated during the working process of the first chip and the second chip can be dissipated, reducing the The overall temperature of the semiconductor structure increases the service life of the semiconductor structure.

To sum up, the semiconductor structure provided by the embodiment of the present disclosure can optimize the heat dissipation of the semiconductor structure and achieve the purpose of quickly reducing the temperature of the semiconductor structure.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description, drawings, and claims.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For Those of ordinary skill in the art can also obtain the drawings of other embodiments according to these drawings without any creative effort.

FIG. 1 is a schematic structural view of a semiconductor structure in the first embodiment;

FIG. 2 is a schematic structural view of a semiconductor structure in a second embodiment;

FIG. 3 is a schematic structural view of a semiconductor structure in a third embodiment;

FIG. 4 is a schematic structural view of a semiconductor structure in a fourth embodiment;

FIG. 5 is a schematic top view of a heat dissipation device in an embodiment;

FIG. 6 is a schematic structural view of the semiconductor structure in the fifth embodiment;

FIG. 7 is a schematic structural diagram of the semiconductor structure in the sixth embodiment.

Detailed ways

In order to facilitate understanding of the embodiments of the present disclosure, the embodiments of the present disclosure will be described more fully below with reference to the relevant drawings. Preferred embodiments of embodiments of the present disclosure are shown in the accompanying drawings. However, embodiments of the present disclosure may be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure content of the embodiments of the present disclosure more thorough and comprehensive.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the disclosure belong. The terms used herein in the description of the embodiments of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the embodiments of the present disclosure, it should be understood that the orientations or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner" and "outer" are based on the drawings The method or positional relationship shown is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as Limitations on Embodiments of the Disclosure.

It can be understood that the terms "first", "second", etc. used in the present disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first wafer could be termed a second wafer, and, similarly, a second wafer could be termed a first wafer, without departing from the scope of the present disclosure. Both the first wafer and the second wafer are wafers, but they are not the same wafer.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

FIG. 1 is a schematic structural diagram of a semiconductor structure in the first embodiment. As shown in FIG. 1, in this embodiment, a semiconductor structure is provided, including: a first wafer 100, a second wafer 200, and a heat dissipation device 300; There are several first chips 102 in the first wafer 100, that is, several first chips 102 are formed in the first wafer 100; There are several second chips 202; the first surface of the second wafer 200 is connected to the first surface of the first wafer 100, and the second chip 102 is electrically connected to the first chip 202; a heat dissipation pipe is provided in the heat dissipation device 300 Road 302, the heat dissipation device 300 is in contact with the second surface of the second wafer 200, the heat generated during the working process of the first chip 102 and the second chip 202 can be conducted to the surface of the heat dissipation device 300 in contact with the second wafer 200, and then Dissipated through the heat dissipation pipeline 302, the second surface of the second wafer 200 is opposite to the first surface of the second wafer 200, that is, the second surface of the second wafer 200 is that the second wafer 200 is away from the first wafer. A surface of a circle 100.

In the above semiconductor structure, the first surface of the second wafer 200 is connected to the first surface of the first wafer 100, and the first chip 102 in the first wafer 100 and the second chip 202 in the second wafer 200 Electrically connected, the second surface of the second wafer 200 is in contact with the heat sink 300, and the heat sink 300 is provided with a heat dissipation pipeline 302, through which the first chip 102 and the second chip 202 can be operated. The generated heat is dissipated to reduce the overall temperature of the semiconductor structure and increase the service life of the semiconductor structure.

Continuing to refer to FIG. 1, in one of the embodiments, the connection between the first side of the first wafer 100 and the first side of the second wafer 200 is through a fusion bonding process or a hybrid bonding process (Fusion bondingor hybrid Bonding) bonding is achieved.

Continuing to refer to FIG. 1, in one implementation, the functional surface of the first chip 102 is located on the first surface of the first wafer 100, and the functional surface of the second chip 202 is located on the first surface of the second wafer 200, specifically, The first wafer 100 includes a substrate and a functional structure on the substrate (the functional surface of the first chip 102), wherein the surface where the functional structure is located is the first surface of the first wafer 100, and the substrate does not form a functional structure The second surface of the first wafer 100 on the surface of the same, the second wafer 200 includes a substrate and a functional structure (the functional surface of the second chip 202) on the substrate, wherein the surface where the functional structure is located is The first surface of the second wafer 200 and the second surface of the second wafer 200 on which the surface of the substrate does not form a functional structure.

FIG. 2 is a schematic structural view of the wafer-level packaging structure in the second embodiment. As shown in FIG. The bump bonding process is bonded together, that is, the first surface of the first wafer 100 and the first surface of the second wafer 200 are connected together by a conductive bump bonding process, and the first wafer 100 There is a conductive bump 402 between the first surface of the wafer 200 and the first surface of the second wafer 200. Exemplarily, the material of the conductive bump 402 includes metallic nickel, metallic tin, metallic copper, metallic gold, and the like.

In one of the embodiments, the conductive bump 402 includes a main conductive bump for electrically connecting the first chip 102 and the second chip 202 and a secondary conductive bump for auxiliary support, that is, the two ends of the conductive bump 402 are respectively The main conductive bump that is in electrical contact with the first chip 102 and the second chip 202 and connects and transmits the signals in the first chip 102 and the second chip 202, that is, the main conductive bump is used to electrically connect the first chip 102 and the second chip 202. The second chip 202, the remaining conductive bumps 402 are sub-conductive bumps, and the sub-conductive bumps can transfer heat from the first wafer while reducing the deformation between the first wafer 100 and the second wafer 200 due to suspension. 100 is conducted to the second wafer 200, and then dissipated through the heat dissipation pipeline 302 to further reduce the overall temperature of the semiconductor structure. It can be understood that the size of the main conductive bump may be different from that of the secondary conductive bump, or at least part of the size of the main conductive bump may be the same as that of the secondary conductive bump.

Continuing to refer to FIG. 2 , in one embodiment, the semiconductor structure further includes: a first TSV 104 and a connecting device 106 ; the first TSV 104 is located in the first wafer 100 , and one end of the first TSV 104 Electrically connected to the first chip 102, the other end of the first TSV 104 extends to the second surface of the first wafer 100, and the second surface of the first wafer 100 is opposite to the first surface of the first wafer 100 ; The first through-silicon via 104 is a conductive structure filled in the through-hole in the first wafer 100. Exemplarily, the material of the first through-silicon via 104 includes metal titanium, metal nickel, metal copper, metal tungsten, polysilicon , metal silver, metal aluminum and other metal materials, etc., lead the pads of the first chip 102 (functional end of the first chip 102 ) to the second surface of the first wafer 100 through the first TSV 104 . The connection device 106 is located on the second surface of the first wafer 100 and is in contact with at least one first TSV 104, that is, the connection end of the connection device 106 is electrically connected to the corresponding pad on the first chip 102. In this way The connection device 106 , the first chip 102 and the second chip 202 are electrically connected, and then different signals are sent to the first chip 102 and the second chip 202 through the connection device 106 .

FIG. 3 is a schematic structural view of the semiconductor structure in the third embodiment. As shown in FIG. 3, in one embodiment, the semiconductor structure further includes: a second through-silicon via 404, and the second through-silicon via 404 is along the first wafer 100 and the second wafer 200 overlap through the first wafer 100 and the second wafer 200, and are in contact with the surface of the heat sink 300, and the heat can be directly transferred from the first wafer through the second silicon via 404. 100. The second wafer 200 and the connection device 106 (when there is a connection device 106) are conducted to the surface of the heat sink 300, and then radiated out through the heat dissipation pipeline 302 to further reduce the overall temperature of the semiconductor structure. The first wafer The direction in which the 100 and the second wafer 200 are stacked is parallel to the direction connecting the first surface of the first wafer 100 and the second surface of the first wafer 100 .

In one embodiment, the second TSV 404 is a thermal conduction structure filled in a through hole passing through the first wafer 100 and the second wafer 200, and the material of the thermal conduction structure includes a solid thermal conduction material (such as a metal material) or Liquid heat conduction material (such as water), heat can be conducted from the first wafer 100, the second wafer 200, the connection device 106 (when there is the connection device 106) to the surface of the heat sink 300 through the solid heat conduction material or the liquid heat conduction material , and then dissipated through the heat dissipation pipeline 302. In other embodiments, the second TSV 404 is a through-hole structure penetrating the first wafer 100 and the second wafer 200, and the heat can be transferred from the first wafer 100, the second wafer 200 through the sidewall and the bottom of the through-hole structure. The second wafer 200 and the connection device 106 (when there is a connection device 106 ) are conducted to the surface of the heat dissipation device 300 , and then dissipated through the heat dissipation pipeline 302 .

In one embodiment, the number of connection devices 106 is not less than two, and the heat dissipated by the connection devices 106 is proportional to the number of adjacent second TSVs 404 . Specifically, the number of second TSVs 404 near the connection device 106 with high power (more heat dissipation) is greater than the number of second TSVs 404 near the connection device 106 with low power (less heat dissipation), and this setting can increase The speed at which heat (the heat dissipated by the connection device 106 and the heat conducted to the connection device 106 ) is conducted from the connection device 106 to the surface of the heat sink 300 achieves the purpose of rapidly reducing the overall temperature of the semiconductor structure.

FIG. 4 is a schematic structural view of the semiconductor structure in the fourth embodiment. As shown in FIG. 4, in one embodiment, the semiconductor structure further includes: a heat conduction device 406, and the heat conduction device 406 is connected to the first wafer 100 and the second wafer 100 respectively. The sidewalls of the circle 200 are in contact with each other for conducting heat from the first wafer 100 to the second wafer 200, and the speed at which heat is conducted from the first wafer 100 to the second wafer 200 can be increased by setting the heat conduction device 406, Further, the speed of heat conduction to the surface of the heat sink 300 is increased, so as to achieve the purpose of rapidly reducing the overall temperature of the semiconductor structure.

Continuing to refer to FIG. 4 , in one embodiment, the surface of the heat sink 300 in contact with the second wafer 200 is in contact with the bottom of the heat conduction device 406 at the same time, along the direction in which the first wafer 100 and the second wafer 200 are stacked , the side of the heat conduction device 406 close to the heat sink 300 is the bottom of the heat conduction device 406 . Through this arrangement, the heat is directly conducted from the first wafer 100 and the second wafer 200 to the surface of the heat sink 300 , so as to further increase the speed of heat conduction to the surface of the heat sink 300 and further reduce the overall temperature of the package structure. The heat conduction device 406 is made of heat conduction material. Exemplarily, the material of the heat conduction device 406 includes metallic silver, metallic copper, metallic aluminum, aluminum oxide, aluminum alloy, thermally conductive tape, graphite, diamond, silicon, and the like.

In one embodiment, the heat conduction device 406 is in contact with the sidewall of the heat dissipation device 300 while being in contact with the sidewalls of the first wafer 100 and the second wafer 200 respectively. Through this setting, the heat is directly conducted from the first wafer 100 and the second wafer 200 to the sidewall of the heat sink 300 , so as to further increase the speed of heat conduction to the heat sink 300 and further reduce the overall temperature of the semiconductor structure. The heat conduction device 406 is made of heat conduction material. Exemplarily, the material of the heat conduction device 406 includes metallic silver, metallic copper, metallic aluminum, aluminum oxide, aluminum alloy, thermally conductive tape, graphite, diamond, silicon, and the like.

In one embodiment, the materials of the heat conducting device 406 and the second TSV 404 are different. In other embodiments, the heat conduction device 406 and the second TSV 404 are made of the same material. In this case, the production cost of the semiconductor structure can be reduced by forming the heat conduction device 406 and the second TSV 404 at the same time.

In one of the embodiments, the orthographic projection of the heat dissipation pipeline 302 on the second wafer 200 surrounds each second chip 202, that is, the scribing lane on the second wafer 202 is at least partially connected with the heat dissipation pipeline 302 on the second wafer. The orthographic projections on 200 overlap, and through this setting, the heat generated by the first chip and the second chip can be transferred to the heat dissipation pipeline 302 better and faster, so as to achieve the purpose of rapidly reducing the overall temperature of the semiconductor structure.

FIG. 5 is a schematic top view of a heat dissipation device in an embodiment. As shown in FIG. 5 , in one embodiment, a groove 308 is provided on the surface of the heat dissipation device 300 in contact with the second wafer 200 , the heat dissipation pipeline 302 is located in the groove 308 , and the heat dissipation pipeline 302 is connected to the second wafer 200 . The second surface of the circle 200 is in contact with each other. Through this arrangement, the heat conducted to the second surface of the second wafer 200 can be quickly dissipated through the heat dissipation pipe 302 to further reduce the overall temperature of the semiconductor structure.

In one embodiment, after the heat dissipation pipeline 302 passes through the heat dissipation device 300 , part of the pipeline is located in the groove 308 . In another embodiment, the cooling pipes 302 are all located in the groove 308 .

In one embodiment, the heat sink 300 includes a metal plate, and the orthographic projection of the second wafer 200 on the heat sink 300 is located in a central area of the heat sink 300 .

In one embodiment, the heat sink 300 includes a metal plate, and the orthographic projection of the second wafer 200 on the heat sink 300 coincides with the heat sink 300 .

In one of the embodiments, there is cooling liquid in the heat dissipation pipeline 302, one end of the heat dissipation pipeline 302 is the input end 304 of the cooling liquid, and the other end of the heat dissipation pipeline 302 is the output end 306 of the cooling liquid. The flow in line 302 dissipates heat.

In one of the embodiments, the number of the second TSVs 404 arranged at the input end 304 of the heat dissipation pipeline 302 is greater than the number of the second TSVs 404 arranged at the output end 306 of the heat dissipation pipeline 302, and the setting is more It is beneficial to the dissipation of heat and achieves the purpose of rapidly reducing the overall temperature of the sealed semiconductor structure.

In one of the embodiments, the heat dissipation pipeline 302 is made of thermally conductive material, through which the heat can be quickly transferred to the cooling liquid.

In one embodiment, the cooling liquid includes a silicate type cooling liquid, and the silicate type cooling liquid has good cooling performance and will not corrode the heat dissipation pipeline 302 .

In one embodiment, the semiconductor structure further includes a cooling pump, and the cooling pump is connected to the heat dissipation pipeline 302 for driving the flow of cooling liquid in the heat dissipation pipeline 302 . It can be understood that the semiconductor structure further includes a storage tank for storing cooling liquid, and the cooling pump is used to drive the cooling liquid in the storage tank to flow in the cooling pipeline 302 .

Continuing to refer to FIG. 5 , in one of the embodiments, the surface of the heat dissipation device 300 in contact with the second wafer 200 is provided with several vacuum adsorption holes 310 spaced apart from the heat dissipation pipeline 302, and the heat dissipation device 300 is connected to the heat dissipation device 300 through the vacuum adsorption holes 310. The second surface of the second wafer 200 is adsorbed and contacted, and the second surface of the second wafer 200 is adsorbed on the surface of the heat sink 300 by setting the vacuum suction hole 310, so as to eliminate the preparation error on the second surface of the second wafer 200 and the second surface of the second wafer 200. The contact effect of the heat sink 300 is more conducive to the conduction of heat.

In one embodiment, the second TSVs 404 are in contact with the vacuum adsorption holes 310 , at this time, heat can be dissipated through the vacuum adsorption holes 310 , so as to further increase the heat dissipation rate and quickly reduce the overall temperature of the packaging structure. It can be understood that when the second TSV 404 is a heat conduction structure filled in the through hole penetrating the first wafer 100 and the second wafer 200, there is no need to limit the size of the second TSV 404; When the second TSV 404 is a through hole structure penetrating the first wafer 100 and the second wafer 200 , the size of the second TSV 404 needs to be smaller than that of the vacuum suction hole 310 .

In one of the embodiments, the conductive bump 402 includes a main conductive bump for electrically connecting the first chip 102 and the second chip 202 and a secondary conductive bump for auxiliary support, that is, the two ends of the conductive bump 402 are respectively The main conductive bump that is in electrical contact with the first chip 102 and the second chip 202 and connects and transmits the signals in the first chip 102 and the second chip 202, that is, the main conductive bump is used to electrically connect the first chip 102 and the second chip 202. The second chip 202, the remaining conductive bumps 402 are secondary conductive bumps, and the vacuum suction holes 310 are in contact with the secondary conductive bumps. At this time, the secondary conductive bumps conduct heat from the first wafer 100 to the second wafer 200. The speed will increase to achieve the purpose of further improving the heat dissipation speed and rapidly reducing the overall temperature of the semiconductor structure.

In one embodiment, the size of the secondary conductive bump is larger than the size of the vacuum suction hole 310 .

Continuing to refer to FIG. 5 , in one embodiment, the heat dissipation pipeline 302 is disposed around the vacuum suction hole 310 .

In one of the embodiments, the first chip includes a logic chip and the second chip includes a memory chip.

In another embodiment, the first chip includes a memory chip and the second chip includes a logic chip.

In other embodiments, both the first chip and the second chip are memory chips or both are logic chips.

FIG. 6 is a schematic structural view of the semiconductor structure in the fifth embodiment. As shown in FIG. 6, in one embodiment, the functional surface of the first chip 102 is located on the second surface of the first wafer 100, and the The functional surface is located on the first surface of the second wafer 200 .

Continuing to refer to FIG. 6 , in one embodiment, the semiconductor structure further includes: a third through-silicon via 108; the third through-silicon via 108 is located in the first wafer 100, and one end of the third through-silicon via 108 is connected to the first chip 102 for electrical connection, the other end of the third through-silicon via 108 extends to the first surface of the first wafer 100, and the pad of the first chip 102 (the functional end of the first chip 102) is drawn out through the third through-silicon via 108 To the first surface of the first wafer 100, the second chip 202 is connected to at least one third TSV 108, that is, the functional end of the second chip 202 is electrically connected to the corresponding pad on the first chip 102, through which The electrical connection between the first chip 102 and the second chip 202 is realized by means of a method, wherein the connection between the second chip 202 and at least one third through-silicon via 108 can be through a conductive bump 402, or through a fusion bonding process or a hybrid bond bonded connection. It can be understood that the connection device 106 is electrically connected to at least one first chip 102 , and the number of the third TSVs 108 can be set according to actual needs.

Continuing to refer to FIG. 6 , in one implementation, the number of the first wafer 100 and the number of the second wafer 200 in the semiconductor structure is one.

In one of the embodiments, the number of the first wafer 100 and/or the second wafer 200 in the semiconductor structure is greater than 1, at this time, the stacking method of the first wafer 100 and the second wafer 200 can be set as required , as long as the bottom layer and the top layer are guaranteed to be the first wafer 100 and the second wafer 200 respectively, between adjacent first wafers 100, between adjacent second wafers 200 or between adjacent first wafers 100 and the second wafer 200 The connection method between the two wafers 200 can refer to the above-mentioned connection method between the first wafer 100 and the second wafer 200 , which will not be repeated here. FIG. 7 is a schematic structural diagram of the semiconductor structure in the sixth embodiment. As shown in FIG. 7 , for example, the number of the first wafer 100 in the semiconductor structure is 1, and the number of the second wafer 200 is 2.

The present disclosure also provides an electronic device, which includes the crystalline semiconductor structure described in any one of the above.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concepts of the embodiments of the present disclosure, and these all belong to the protection scope of the embodiments of the present disclosure. Therefore, the scope of protection of the disclosed embodiment patents should be determined by the appended claims.

Claims

A semiconductor structure comprising:

a first wafer, having a plurality of first chips inside the first wafer;

The second wafer has several second chips in the second wafer, the first surface of the second wafer is connected to the first surface of the first wafer, and the second chip is connected to the first surface of the first wafer. the first chip is electrically connected;

A heat dissipation device, the heat dissipation device is provided with a heat dissipation pipeline; the heat dissipation device is in contact with the second surface of the second wafer, and the second surface of the second wafer is in contact with the first surface of the second wafer set side by side.
The semiconductor structure according to claim 1, further comprising:

A first through-silicon via, the first through-silicon via is located in the first wafer, one end of the first through-silicon via is electrically connected to the first chip, and the other end of the first through-silicon via Extending to the second surface of the first wafer, the second surface of the first wafer is opposite to the first surface of the first wafer;

A connection device, the connection device is located on the second surface of the first wafer and is in contact with at least one of the first TSVs.
The semiconductor structure according to claim 2, further comprising:

a second through silicon via, the second through silicon via penetrates the first wafer and the second wafer along the direction in which the first wafer and the second wafer overlap, and is connected to the second wafer The surfaces of the heat sink are in contact.
The semiconductor structure according to claim 3, wherein the number of the connecting devices is not less than two, and the heat dissipated by the connecting devices is proportional to the number of adjacent second TSVs.
The semiconductor structure according to claim 1, further comprising:

The heat conduction device is in contact with the sidewalls of the first wafer and the second wafer respectively, and is used for conducting heat from the first wafer to the second wafer.
The semiconductor structure according to claim 1, wherein an orthographic projection of the heat dissipation pipe on the second wafer surrounds each of the second chips.
The semiconductor structure according to claim 1, wherein the surface of the heat dissipation device in contact with the second wafer is provided with a plurality of vacuum suction holes spaced apart from the heat dissipation pipeline, and the heat dissipation device passes through the The vacuum suction holes are in suction contact with the second surface of the second wafer.
The semiconductor structure according to claim 7, wherein the heat dissipation pipeline is arranged around the vacuum suction hole.
The semiconductor structure of claim 1, wherein the first chip includes a logic chip and the second chip includes a memory chip, or the first chip includes a memory chip and the second chip includes a logic chip.
The semiconductor structure according to claim 1, wherein the functional surface of the first chip is located on the first surface of the first wafer, and the functional surface of the second chip is located on the first surface of the second wafer. noodle.
The semiconductor structure according to claim 1, wherein the functional surface of the first chip is located on the second surface of the first wafer, and the functional surface of the second chip is located on the first surface of the second wafer. noodle.
The semiconductor structure according to claim 1, wherein the first surface of the first wafer and the first surface of the second wafer are bonded together by a conductive bump bonding process or a fusion bonding process.
The semiconductor structure according to any one of claims 1-12, wherein the surface of the heat dissipation device in contact with the second wafer is provided with a groove, the heat dissipation pipeline is located in the groove, and The heat dissipation pipe is in contact with the second surface of the second wafer.
The semiconductor structure according to claim 13, wherein there is cooling liquid in the heat dissipation pipeline, one end of the heat dissipation pipeline is the input end of the cooling liquid, and the other end of the heat dissipation pipeline is the cooling liquid. liquid output.
The semiconductor structure according to any one of claims 1-12, wherein the heat sink comprises a metal plate, and the orthographic projection of the second wafer on the heat sink is located in a central area of the heat sink.