CN115775778A - Semiconductor structure - Google Patents

Semiconductor structure Download PDF

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Publication number
CN115775778A
CN115775778A CN202111039932.3A CN202111039932A CN115775778A CN 115775778 A CN115775778 A CN 115775778A CN 202111039932 A CN202111039932 A CN 202111039932A CN 115775778 A CN115775778 A CN 115775778A
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CN
China
Prior art keywords
wafer
heat dissipation
semiconductor structure
chip
heat
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Pending
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CN202111039932.3A
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Chinese (zh)
Inventor
寗树梁
何军
刘杰
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202111039932.3A priority Critical patent/CN115775778A/en
Priority to PCT/CN2022/088429 priority patent/WO2023029518A1/en
Publication of CN115775778A publication Critical patent/CN115775778A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment of the application relates to a semiconductor structure. The method comprises the following steps: the chip packaging structure comprises a first wafer, a second wafer and a chip packaging structure, wherein a plurality of first chips are arranged in the first wafer; the first wafer is internally provided with a plurality of first chips, the first surface of the first wafer is connected with the first surface of the second wafer, and the first chips are electrically connected with the second chips; the heat dissipation device is internally provided with a heat dissipation pipeline; the heat dissipation device is in contact with the second surface of the second wafer, and the second surface of the second wafer is opposite to the first surface of the second wafer. The heat generated in the working process of the first chip and the second chip can be dissipated through the heat dissipation pipeline, the overall temperature of the semiconductor structure is reduced, and the service life of the semiconductor structure is prolonged.

Description

Semiconductor structure
Technical Field
The embodiment of the application relates to the technical field of semiconductors, in particular to a semiconductor structure.
Background
With the advent of the 5G communication and Artificial Intelligence (AI) era, the amount of data to be transmitted, stored and processed interactively at high speed by chips applied to semiconductor devices in such related fields is very large, a lot of heat is generated in the working process of the chips, so that the work and the service life of the semiconductor devices are influenced, and how to quickly dissipate the heat generated in the working process of the semiconductor devices becomes a problem which is urgently needed to be solved.
Disclosure of Invention
The embodiment of the application provides a semiconductor structure, can optimize semiconductor structure's heat dissipation, reaches the purpose that the express delivery reduced the semiconductor structure temperature.
A semiconductor structure, comprising:
the chip packaging structure comprises a first wafer, a second wafer and a chip packaging structure, wherein a plurality of first chips are arranged in the first wafer;
the first wafer is internally provided with a plurality of first chips, the first surface of the first wafer is connected with the first surface of the second wafer, and the first chips are electrically connected with the second chips;
the heat dissipation device is internally provided with a heat dissipation pipeline; the heat dissipation device is in contact with the second surface of the second wafer, and the second surface of the second wafer is opposite to the first surface of the second wafer.
In one embodiment, the semiconductor structure further comprises:
the first through silicon via is positioned in the first wafer, one end of the first through silicon via is electrically connected with the first chip, the other end of the first through silicon via extends to the second surface of the first wafer, and the second surface of the first wafer is arranged opposite to the first surface of the first wafer;
and the connecting device is positioned on the second surface of the first wafer and is in contact with the at least one first through silicon via.
In one embodiment, the semiconductor structure further comprises:
and the second silicon through hole penetrates through the first wafer and the second wafer along the direction of overlapping the first wafer and the second wafer and is in contact with the surface of the heat dissipation device.
In one embodiment, the number of the connecting devices is not less than 2, and the heat emitted by the connecting devices is proportional to the number of the adjacent second through silicon vias.
In one embodiment, the semiconductor structure further comprises:
and the heat conduction device is respectively contacted with the side walls of the first wafer and the second wafer and is used for conducting heat from the first wafer to the second wafer.
In one embodiment, the orthographic projection of the heat dissipation pipeline on the second wafer surrounds each second chip.
In one embodiment, the surface of the heat dissipation device contacting the second wafer is provided with a plurality of vacuum absorption holes spaced from the heat dissipation pipeline, and the heat dissipation device is in absorption contact with the second surface of the second wafer through the vacuum absorption holes.
In one embodiment, the heat dissipation pipe is arranged around the vacuum adsorption hole.
In one embodiment, the first chip comprises a logic chip and the second chip comprises a memory chip, or the first chip comprises a memory chip and the second chip comprises a logic chip.
In one embodiment, the functional surface of the first chip is located on the first surface of the first wafer, and the functional surface of the second chip is located on the first surface of the second wafer.
In one embodiment, the functional surface of the first chip is located on the second surface of the first wafer, and the functional surface of the second chip is located on the first surface of the second wafer.
In one embodiment, the first side of the first wafer and the first side of the second wafer are bonded together using a conductive bump bonding process or a fusion bonding process.
In one embodiment, a groove is formed on a surface of the heat dissipation device contacting the second wafer, the heat dissipation pipeline is located in the groove, and the heat dissipation pipeline contacts the second surface of the second wafer.
In one embodiment, the cooling liquid is provided in the heat dissipation pipeline, one end of the heat dissipation pipeline is an input end of the cooling liquid, and the other end of the heat dissipation pipeline is an output end of the cooling liquid.
In one embodiment, the heat dissipation device comprises a metal plate, and the orthographic projection of the second wafer on the heat dissipation device is located in the central area of the heat dissipation device.
In the semiconductor structure, the first surface of the second wafer is connected with the first surface of the first wafer, the first chip in the first wafer is electrically connected with the second chip in the second wafer, the second surface of the second wafer is in contact with the heat dissipation device, the heat dissipation device is internally provided with the heat dissipation pipeline, heat generated in the working process of the first chip and the second chip can be dissipated through the heat dissipation pipeline, the overall temperature of the semiconductor structure is reduced, and the service life of the semiconductor structure is prolonged.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic structural diagram of a semiconductor structure in embodiment 1;
FIG. 2 is a schematic diagram of a semiconductor structure in embodiment 2;
FIG. 3 is a schematic diagram illustrating the structure of the semiconductor structure in embodiment 3;
FIG. 4 is a schematic diagram illustrating the structure of the semiconductor structure in example 4;
FIG. 5 is a schematic top view of a heat dissipation device according to an embodiment;
FIG. 6 is a schematic diagram illustrating a semiconductor structure in accordance with example 5;
fig. 7 is a schematic structural diagram of a semiconductor structure in embodiment 6.
Description of reference numerals:
100. a first wafer; 102. a first chip; 104. a first through-silicon-via; 106. a connecting device; 108. a third through-silicon-via; 200. a second wafer; 202. a second chip; 300. a heat sink; 302. a heat dissipation pipeline; 304. an input end; 306. an output end; 308. a groove; 310. a vacuum adsorption hole; 402. a conductive bump; 404. a second through-silicon-via; 406. a heat conducting device.
Detailed Description
To facilitate an understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. The embodiments of the present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application belong. The terminology used herein in the description of the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the embodiments of the present application, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only used for convenience in describing the embodiments of the present application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have specific orientations, be constructed in specific orientations, and be operated, and thus, should not be construed as limiting the embodiments of the present application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first wafer may be referred to as a second wafer, and similarly, a second wafer may be referred to as a first wafer, without departing from the scope of the present application. The first wafer and the second wafer are both wafers, but they are not the same wafer.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. In the description of the present application, "a number" means at least one, such as one, two, etc., unless specifically limited otherwise.
Fig. 1 is a schematic structural diagram of a semiconductor structure in embodiment 1, and as shown in fig. 1, in this embodiment, a semiconductor structure is provided, which includes: a first wafer 100, a second wafer 200, and a heat sink 300; the first wafer 100 has a plurality of first chips 102 therein, that is, the first wafer 100 has a plurality of first chips 102 formed therein; a plurality of second chips 202 are formed in the second wafer 200, that is, a plurality of second chips 202 are formed in the second wafer 200; the first side of the second wafer 200 is connected to the first side of the first wafer 100, and the second chip 102 is electrically connected to the first chip 202; a heat dissipation pipe 302 is disposed in the heat dissipation device 300, the heat dissipation device 300 contacts with the second surface of the second wafer 200, heat generated during the operation of the first chip 102 and the second chip 202 can be conducted to the contact surface of the heat dissipation device 300 and the second wafer 200, and then dissipated through the heat dissipation pipe 302, the second surface of the second wafer 200 is disposed opposite to the first surface of the second wafer 200, that is, the second surface of the second wafer 200 is a surface of the second wafer 200 away from the first wafer 100.
In the semiconductor structure, the first surface of the second wafer 200 is connected to the first surface of the first wafer 100, the first chip 102 in the first wafer 100 is electrically connected to the second chip 202 in the second wafer 200, the second surface of the second wafer 200 is in contact with the heat dissipation device 300, and the heat dissipation device 300 is internally provided with the heat dissipation pipeline 302, so that heat generated in the working process of the first chip 102 and the second chip 202 can be dissipated through the heat dissipation pipeline 302, the overall temperature of the semiconductor structure is reduced, and the service life of the semiconductor structure is prolonged.
With continued reference to fig. 1, in one embodiment, the connection between the first side of the first wafer 100 and the first side of the second wafer 200 is achieved by Fusion bonding or hybrid bonding.
With continued reference to fig. 1, in one implementation, the functional side of the first chip 102 is located on the first side of the first wafer 100, and the functional side of the second chip 202 is located on the first side of the second wafer 200, and specifically, the first wafer 100 includes a substrate and a functional structure (the functional side of the first chip 102) located on the substrate, wherein the surface where the functional structure is located is the first side of the first wafer 100, and the substrate does not form the second side of the functional structure surface of the first wafer 100, and similarly, the second wafer 200 includes a substrate and a functional structure (the functional side of the second chip 202) located on the substrate, wherein the surface where the functional structure is located is the first side of the second wafer 200, and the substrate does not form the second side of the second wafer 200.
Fig. 2 is a schematic structural diagram of a wafer level package structure in embodiment 2, and as shown in fig. 2, in this embodiment, a first surface of a first wafer 100 and a first surface of a second wafer 200 are bonded together by using a conductive bump bonding process, that is, the first surface of the first wafer 100 and the first surface of the second wafer 200 are connected together by using a conductive bump bonding process, a conductive bump 402 is disposed between the first surface of the first wafer 100 and the first surface of the second wafer 200, and for example, the material of the conductive bump 402 includes nickel metal, tin metal, copper metal, gold metal, and the like.
In one embodiment, the conductive bumps 402 include a main conductive bump for electrically connecting the first chip 102 and the second chip 202 and a sub-conductive bump for assisting support, that is, two ends of the conductive bumps 402 are respectively electrically contacted with the first chip 102 and the second chip 202, and the main conductive bump is used for electrically connecting the first chip 102 and the second chip 202 and transmitting signals in the first chip 102 and the second chip 202, and the remaining conductive bumps 402 are sub-conductive bumps, and the sub-conductive bumps are used for transmitting heat from the first wafer 100 to the second wafer 200 while reducing deformation between the first wafer 100 and the second wafer 200 due to suspension, and further radiate the heat through the heat radiation pipe 302, thereby further reducing the overall temperature of the semiconductor structure. It is understood that the size of the primary conductive bump may be different from the size of the secondary conductive bump, or at least a portion of the primary conductive bump may be the same as the size of the secondary conductive bump.
With continued reference to fig. 2, in one embodiment, the semiconductor structure further comprises: a first through-silicon-via 104 and a connection device 106; the first through silicon via 104 is located in the first wafer 100, one end of the first through silicon via 104 is electrically connected to the first chip 102, the other end of the first through silicon via 104 extends to the second side of the first wafer 100, and the second side of the first wafer 100 is opposite to the first side of the first wafer 100; the first through-silicon-via 104 is a conductive structure filled in a through-hole in the first wafer 100, and exemplarily, the material of the first through-silicon-via 104 includes metal materials such as metal titanium, metal nickel, metal copper, metal tungsten, polysilicon, metal silver, and metal aluminum, and the pad of the first chip 102 (the functional end of the first chip 102) is led out to the second side of the first wafer 100 through the first through-silicon-via 104. The connection device 106 is located on the second side of the first wafer 100 and is in contact with the at least one first through-silicon-via 104, that is, the connection end of the connection device 106 is electrically connected to the corresponding pad on the first chip 102, so that the connection device 106, the first chip 102 and the second chip 202 are electrically connected, and then different signals are sent to the first chip 102 and the second chip 202 through the connection device 106.
Fig. 3 is a schematic structural diagram of the semiconductor structure in embodiment 3, and as shown in fig. 3, in one embodiment, the semiconductor structure further includes: the second through-silicon via 404, the second through-silicon via 404 penetrates the first wafer 100 and the second wafer 200 along the direction in which the first wafer 100 and the second wafer 200 are stacked, and contacts the surface of the heat dissipation device 300, heat can be directly conducted from the first wafer 100, the second wafer 200, and the connection device 106 (when having the connection device 106) to the surface of the heat dissipation device 300 through the second through-silicon via 404, and then dissipated through the heat dissipation pipeline 302, so as to achieve the effect of further reducing the overall temperature of the semiconductor structure, and the stacking direction of the first wafer 100 and the second wafer 200 is parallel to the direction in which the first surface of the first wafer 100 is connected with the second surface of the first wafer 100.
In one embodiment, the second through-silicon-via 404 is a heat-conducting structure filled in the through-holes penetrating through the first wafer 100 and the second wafer 200, and the material of the heat-conducting structure includes a solid heat-conducting material (e.g., a metal material) or a liquid heat-conducting material (e.g., water), through which heat can be conducted from the first wafer 100, the second wafer 200, the connecting device 106 (when having the connecting device 106) to the surface of the heat dissipation apparatus 300, and then dissipated through the heat dissipation pipe 302. In other embodiments, the second through-silicon-via 404 is a through-via structure penetrating the first wafer 100 and the second wafer 200, and the heat can be conducted from the first wafer 100, the second wafer 200, the connecting device 106 (when having the connecting device 106) to the surface of the heat sink 300 through the sidewall and the bottom of the through-via structure, and then dissipated through the heat dissipation pipeline 302.
In one embodiment, the number of connecting devices 106 is not less than 2, and the amount of heat dissipated by the connecting devices 106 is proportional to the number of adjacent second through-silicon vias 404. Specifically, the number of the second through silicon vias 404 near the connecting device 106 with high power (high heat dissipation) is greater than the number of the second through silicon vias 404 near the connecting device 106 with low power (low heat dissipation), and by this arrangement, the speed of heat (the heat dissipated by the connecting device 106 and the heat conducted to the connecting device 106) conducted from the connecting device 106 to the surface of the heat dissipation apparatus 300 can be increased, so as to achieve the purpose of rapidly reducing the overall temperature of the semiconductor structure.
Fig. 4 is a schematic structural diagram of the semiconductor structure in embodiment 4, and as shown in fig. 4, in one embodiment, the semiconductor structure further includes: the heat conduction device 406 is in contact with the sidewalls of the first wafer 100 and the second wafer 200, respectively, and is configured to conduct heat from the first wafer 100 to the second wafer 200, and the heat conduction device 406 is configured to increase the speed of conducting heat from the first wafer 100 to the second wafer 200, and further increase the speed of conducting heat to the surface of the heat dissipation device 300, so as to achieve the purpose of rapidly reducing the overall temperature of the semiconductor structure.
With continued reference to fig. 4, in one embodiment, the surface of the heat spreader 300 contacting the second wafer 200 is simultaneously in contact with the bottom of the heat conducting device 406, and the surface of the heat conducting device 406 adjacent to the heat spreader 300 is the bottom of the heat conducting device 406 along the direction of stacking the first wafer 100 and the second wafer 200. Through the arrangement, heat is directly conducted from the first wafer 100 and the second wafer 200 to the surface of the heat dissipation device 300, so that the speed of conducting the heat to the surface of the heat dissipation device 300 is further increased, and the purpose of further reducing the overall temperature of the package structure is achieved. The heat conducting means 406 is made of a heat conducting material, and illustratively, the material of the heat conducting means 406 includes metallic silver, metallic copper, metallic aluminum, aluminum oxide, aluminum alloy, heat conducting tape, graphite, diamond, silicon, and the like.
In one embodiment, the thermal conductor 406 contacts the sidewalls of the first and second wafers 100 and 200, respectively, while contacting the sidewalls of the heat spreader 300. Through the arrangement, heat is directly conducted from the first wafer 100 and the second wafer 200 to the side wall of the heat dissipation device 300, so that the speed of conducting the heat to the heat dissipation device 300 is further increased, and the purpose of further reducing the overall temperature of the semiconductor structure is achieved. The heat conducting means 406 is made of a heat conducting material, and exemplary materials of the heat conducting means 406 include metallic silver, metallic copper, metallic aluminum, aluminum oxide, aluminum alloy, heat conducting tape, graphite, diamond, silicon, and the like.
In one embodiment, the material of the heat conducting device 406 and the second through silicon via 404 are different. In other embodiments, the material of the heat conducting device 406 and the second through silicon via 404 are the same, and in this case, the production cost of the semiconductor structure can be reduced by forming the heat conducting device 406 and the second through silicon via 404 at the same time.
In one embodiment, the orthographic projection of the heat dissipation pipeline 302 on the second wafer 200 surrounds each second chip 202, that is, at least part of the scribe line on the second wafer 202 coincides with the orthographic projection of the heat dissipation pipeline 302 on the second wafer 200, by this arrangement, the heat generated by the first chip and the second chip can be better and faster conducted to the heat dissipation pipeline 302, and the purpose of rapidly reducing the overall temperature of the semiconductor structure is achieved.
Fig. 5 is a schematic top view of a heat dissipation device according to an embodiment. As shown in fig. 5, in one embodiment, a groove 308 is formed on a surface of the heat dissipation device 300 contacting the second wafer 200, the heat dissipation pipe 302 is located in the groove 308, and the heat dissipation pipe 302 contacts the second surface of the second wafer 200, so that heat conducted to the second surface of the second wafer 200 can be quickly dissipated through the heat dissipation pipe 302, thereby further reducing the overall temperature of the semiconductor structure.
In one embodiment, the heat sink conduit 302 is partially routed through the heat sink 300 and into the recess 308. In another embodiment, the heat sink conduit 302 is entirely located within the recess 308.
In one embodiment, the heat spreader 300 includes a metal plate, and the orthographic projection of the second wafer 200 on the heat spreader 300 is located in the central region of the heat spreader 300.
In one embodiment, the heat spreader 300 includes a metal plate, and the orthographic projection of the second wafer 200 on the heat spreader 300 coincides with the heat spreader 300.
In one embodiment, the heat dissipation pipe 302 has a cooling fluid therein, one end of the heat dissipation pipe 302 is an input end 304 of the cooling fluid, and the other end of the heat dissipation pipe 302 is an output end 306 of the cooling fluid, and heat is dissipated by the flow of the cooling fluid in the heat dissipation pipe 302.
In one embodiment, the number of the second through-silicon vias 404 disposed at the input end 304 of the heat dissipation pipeline 302 is greater than the number of the second through-silicon vias 404 disposed at the output end 306 of the heat dissipation pipeline 302, which is more favorable for heat dissipation and achieves the purpose of rapidly reducing the overall temperature of the semiconductor package.
In one embodiment, the heat dissipation conduit 302 is made of a thermally conductive material, and this arrangement allows heat to be quickly transferred to the cooling fluid.
In one embodiment, the cooling fluid comprises a silicate-type cooling fluid, which has good cooling performance and does not corrode the heat dissipation pipe 302.
In one embodiment, the semiconductor structure further comprises a cooling pump connected to the heat dissipation pipe 302 for driving the flow of the cooling fluid in the heat dissipation pipe 302. It is understood that the semiconductor structure further includes a storage tank for storing the cooling fluid, and the cooling pump is used to drive the flow of the cooling fluid in the storage tank in the heat dissipation pipe 302.
With reference to fig. 5, in one embodiment, the surface of the heat dissipation device 300 contacting the second wafer 200 is provided with a plurality of vacuum suction holes 310 spaced apart from the heat dissipation pipeline 302, the heat dissipation device 300 is in suction contact with the second surface of the second wafer 200 through the vacuum suction holes 310, and the second surface of the second wafer 200 is sucked on the surface of the heat dissipation device 300 through the vacuum suction holes 310, so as to eliminate the influence of the manufacturing error on the contact between the second surface of the second wafer 200 and the heat dissipation device 300, which is more beneficial to heat conduction.
In one embodiment, the second through-silicon-via 404 is in contact with the vacuum suction hole 310, and heat can be dissipated through the vacuum suction hole 310, so as to further increase the heat dissipation speed and rapidly lower the overall temperature of the package structure. It is understood that when the second through-silicon-via 404 is a heat-conducting structure filled in a through-hole penetrating the first wafer 100 and the second wafer 200, the size of the second through-silicon-via 404 is not necessarily limited; when the second through silicon via 404 is a through via structure penetrating the first wafer 100 and the second wafer 200, the second through silicon via 404 needs to be smaller than the vacuum chucking hole 310.
In one embodiment, the conductive bumps 402 include a main conductive bump for electrically connecting the first chip 102 and the second chip 202 and a sub-conductive bump for auxiliary support, that is, the main conductive bump is used for electrically connecting the first chip 102 and the second chip 202 at two ends of the conductive bump 402 and electrically connecting and transmitting signals in the first chip 102 and the second chip 202, the remaining conductive bumps 402 are sub-conductive bumps, and the vacuum suction hole 310 is in contact with the sub-conductive bump, at this time, the speed of the sub-conductive bump for transmitting heat from the first wafer 100 to the second wafer 200 is increased, so as to achieve the purposes of further increasing the heat dissipation speed and rapidly reducing the overall temperature of the semiconductor structure.
In one embodiment, the size of the sub-conductive bump is larger than the size of the vacuum chucking hole 310.
With continued reference to FIG. 5, in one embodiment, the heat sink tubing 302 is disposed around the vacuum chucking hole 310.
In one embodiment, the first chip comprises a logic chip and the second chip comprises a memory chip.
In another embodiment, the first chip comprises a memory chip and the second chip comprises a logic chip.
In other embodiments, the first chip and the second chip are both memory chips or both logic chips.
Fig. 6 is a schematic structural diagram of the semiconductor structure in the embodiment 5. As shown in fig. 6, in one embodiment, the functional surface of the first die 102 is located on the second side of the first wafer 100, and the functional surface of the second die 202 is located on the first side of the second wafer 200.
With continued reference to fig. 6, in one embodiment, the semiconductor structure further comprises: a third through-silicon-via 108; the third through silicon via 108 is located in the first wafer 100, one end of the third through silicon via 108 is electrically connected to the first chip 102, the other end of the third through silicon via 108 extends to the first side of the first wafer 100, a pad (a functional end of the first chip 102) of the first chip 102 is led out to the first side of the first wafer 100 through the third through silicon via 108, the second chip 202 is connected to at least one third through silicon via 108, that is, the functional end of the second chip 202 is electrically connected to a corresponding pad on the first chip 102, by this way, the first chip 102 and the second chip 202 are electrically connected, wherein the second chip 202 and the at least one third through silicon via 108 may be connected through a conductive bump 402, or may be bonded and connected through a fusion bonding process or a hybrid bonding process. It is understood that the connection device 106 is electrically connected to at least one first chip 102, and the number of the third through silicon vias 108 can be set according to actual needs.
With continued reference to fig. 6, in one implementation, the number of first wafers 100 and second wafers 200 in the semiconductor structure is 1.
In one embodiment, the number of the first wafers 100 and/or the second wafers 200 in the semiconductor structure is greater than 1, and at this time, a stacking manner of the first wafers 100 and the second wafers 200 may be set as needed as long as the bottom layer and the top layer are respectively the first wafers 100 and the second wafers 200, and the connection manner between the adjacent first wafers 100, the adjacent second wafers 200, or the adjacent first wafers 100 and the second wafers 200 may refer to the connection manner between the first wafers 100 and the second wafers 200, which is not described herein again. Fig. 7 is a schematic structural diagram of the semiconductor structure in the embodiment 6, as shown in fig. 7, in which the number of the first wafers 100 is 1 and the number of the second wafers 200 is 2.
The present application also provides an electronic device comprising the crystalline semiconductor structure of any one of the above.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above embodiments only express several implementation manners of the embodiments of the present application, and the descriptions are specific and detailed, but should not be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the appended claims.

Claims (15)

1. A semiconductor structure, comprising:
the chip packaging structure comprises a first wafer, a second wafer and a chip packaging structure, wherein a plurality of first chips are arranged in the first wafer;
the second wafer is internally provided with a plurality of second chips, the first surface of the second wafer is connected with the first surface of the first wafer, and the second chips are electrically connected with the first chips;
the heat dissipation device is internally provided with a heat dissipation pipeline; the heat dissipation device is in contact with the second surface of the second wafer, and the second surface of the second wafer is opposite to the first surface of the second wafer.
2. The semiconductor structure of claim 1, further comprising:
the first through silicon via is positioned in the first wafer, one end of the first through silicon via is electrically connected with the first chip, the other end of the first through silicon via extends to the second surface of the first wafer, and the second surface of the first wafer is arranged opposite to the first surface of the first wafer;
and the connecting device is positioned on the second surface of the first wafer and is in contact with at least one first through silicon via.
3. The semiconductor structure of claim 2, further comprising:
and the second silicon through hole penetrates through the first wafer and the second wafer along the direction of overlapping the first wafer and the second wafer, and is in contact with the surface of the heat dissipation device.
4. The semiconductor structure of claim 3, wherein the number of the connection devices is not less than 2, and the amount of heat dissipated by the connection devices is proportional to the number of adjacent second through silicon vias.
5. The semiconductor structure of claim 1, further comprising:
and the heat conduction device is respectively contacted with the side walls of the first wafer and the second wafer and is used for conducting heat from the first wafer to the second wafer.
6. The semiconductor structure of claim 1, wherein an orthographic projection of the heat dissipation pipeline on the second wafer surrounds each of the second chips.
7. The semiconductor structure of claim 1, wherein a surface of the heat sink contacting the second wafer is provided with a plurality of vacuum holes spaced apart from the heat sink channel, and the heat sink is in suction contact with the second surface of the second wafer through the vacuum holes.
8. The semiconductor structure of claim 7, wherein the heat dissipation pipe is disposed around the vacuum chucking hole.
9. The semiconductor structure of claim 1, wherein the first chip comprises a logic chip and the second chip comprises a memory chip, or wherein the first chip comprises a memory chip and the second chip comprises a logic chip.
10. The semiconductor structure of claim 1, wherein the functional surface of the first die is located on the first side of the first wafer and the functional surface of the second die is located on the first side of the second wafer.
11. The semiconductor structure of claim 1, wherein the functional surface of the first die is located on the second side of the first wafer, and the functional surface of the second die is located on the first side of the second wafer.
12. The semiconductor structure of claim 1, wherein the first side of the first wafer and the first side of the second wafer are bonded together using a conductive bump bonding process or a fusion bonding process.
13. The semiconductor structure of any one of claims 1-12, wherein a surface of the heat dissipation device contacting the second wafer is provided with a groove, the heat dissipation pipe is located in the groove, and the heat dissipation pipe contacts the second surface of the second wafer.
14. The semiconductor structure of claim 13, wherein the heat dissipation pipeline has a cooling fluid therein, one end of the heat dissipation pipeline is an input end of the cooling fluid, and the other end of the heat dissipation pipeline is an output end of the cooling fluid.
15. The semiconductor structure of any one of claims 1-12, wherein the heat spreader comprises a metal plate, and an orthographic projection of the second wafer on the heat spreader is located in a central region of the heat spreader.
CN202111039932.3A 2021-09-06 2021-09-06 Semiconductor structure Pending CN115775778A (en)

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PCT/CN2022/088429 WO2023029518A1 (en) 2021-09-06 2022-04-22 Semiconductor structure

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US8154116B2 (en) * 2008-11-03 2012-04-10 HeadwayTechnologies, Inc. Layered chip package with heat sink
CN101937907B (en) * 2009-06-29 2012-09-05 财团法人工业技术研究院 Chip stacking package structure and manufacture method thereof
TWI525787B (en) * 2013-06-10 2016-03-11 力成科技股份有限公司 Thermally-enhanced package of chip 3d-stack cube
CN107275238A (en) * 2017-06-28 2017-10-20 华进半导体封装先导技术研发中心有限公司 A kind of stacked wafer method for packing and structure

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