CN104167369A - Manufacturing method of chip packaging structure - Google Patents
Manufacturing method of chip packaging structure Download PDFInfo
- Publication number
- CN104167369A CN104167369A CN201310336975.7A CN201310336975A CN104167369A CN 104167369 A CN104167369 A CN 104167369A CN 201310336975 A CN201310336975 A CN 201310336975A CN 104167369 A CN104167369 A CN 104167369A
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- carrier
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- patterned metal
- metal layer
- dielectric layer
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 147
- 238000000034 method Methods 0.000 claims abstract description 96
- 239000000084 colloidal system Substances 0.000 claims abstract description 39
- 238000012856 packing Methods 0.000 claims description 36
- 239000004020 conductor Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 153
- 238000003466 welding Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 239000012792 core layer Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000012945 sealing adhesive Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A method for manufacturing a chip packaging structure comprises the following steps. First, a first carrier is provided. The first loader comprises a first surface and a patterned metal layer. The patterned metal layer is disposed on the first surface. Then, a dielectric layer is formed on the first surface to cover the patterned metal layer. Then, the patterned metal layer and the dielectric layer on the first carrier are transferred to the second carrier. Then, a plurality of chips are arranged on the patterned metal layer, so that the chips are electrically connected with the patterned metal layer. And finally, forming a packaging colloid on the second loader, wherein the packaging colloid covers the chip, the patterned metal layer and the dielectric layer. Then, the second carrier is removed. And then, cutting the packaging colloid and the dielectric layer between the chips to form a plurality of chip packaging structures.
Description
Technical field
The invention relates to a kind of manufacture method of encapsulating structure, and particularly relevant for a kind of manufacture method of chip-packaging structure.
Background technology
In semiconductor technology, chip packaging carrying plate is one of potted element often using at present.Chip packaging carrying plate is for example a multilayer circuit board, its be mainly by multilayer line layer and multilayer dielectric layer be superimposed form.
Generally speaking, above-mentioned multilayer circuit board was to make up and down multilayer line and multilayer dielectric layer at a core substrate in the past, and core substrate is for having certain thickness carrier.Multilayer line and multilayer dielectric layer are with fully-additive process (fully additive process), semi-additive process (semi-additive process), subtractive process (subtractive process) or other applicable methods are alternately stacked on core substrate.Along with electronic component slimming, if cannot effectively reduce the thickness of core substrate, certainly will be unfavorable for reducing the gross thickness of chip-packaging structure.The thickness of core substrate thereby need coordinate attenuation, to be configured in the confined space of electronic component.Yet when the reduced down in thickness of core substrate, the core substrate of slimming, because rigidity is not enough, therefore easily increases degree of difficulty and the fraction defective of substrate process and packaging technology.
Summary of the invention
The invention provides a kind of manufacture method of chip-packaging structure, its chip-packaging structure of producing does not have support plate core layer structure, thereby has thinner package thickness.
The present invention proposes a kind of manufacture method of chip-packaging structure, and it comprises the following steps.First, provide one first carrier.The first carrier comprises a first surface and a patterned metal layer.Patterned metal layer is arranged on first surface.Then, form a dielectric layer on first surface, with overlay pattern metal level.Then, the patterned metal layer on the first carrier and dielectric layer are transferred on one second carrier.Then, a plurality of chips are set on patterned metal layer, make chip be electrically connected patterned metal layer.Afterwards, form a packing colloid on the second carrier, and packing colloid covers chip, patterned metal layer and dielectric layer.Then, remove the second carrier.Afterwards, the packing colloid between diced chip and dielectric layer, to form a plurality of chip-packaging structures.
The present invention proposes a kind of manufacture method of chip-packaging structure, and it comprises the following steps.First, provide one first carrier.The first carrier comprises a metal level, is arranged on the first carrier.Then, form a dielectric layer on metal level.Metal level on the first carrier and dielectric layer are transferred on one second carrier, and its dielectric layer attaches the second carrier.Then, remove the first carrier to expose metal level, and metal level is carried out to a Patternized technique, to form a patterned metal layer, patterned metal layer comprises a plurality of conductive traces.Afterwards, a plurality of chips are set on patterned metal layer, make chip be electrically connected patterned metal layer.Then, form a packing colloid on the second carrier, and packing colloid covers chip, patterned metal layer and dielectric layer.Afterwards, remove the second carrier.Then, the packing colloid between diced chip and dielectric layer, to form a plurality of chip-packaging structures.
Based on above-mentioned, the present invention is prior to forming patterned metal layer and dielectric layer on the first carrier, again patterned metal layer and dielectric layer are transferred on the second carrier to carry out follow-up chip join, to cover the techniques such as packing colloid, afterwards, then remove the second carrier and the follow-up chip package process that continued.In addition, the present invention also can be prior to forming a metal level and dielectric layer on the first carrier, again metal level and dielectric layer are transferred on the second carrier, then just metal level is carried out to patterning, and carry out follow-up chip join, cover the techniques such as packing colloid, afterwards, then remove the second carrier, with the follow-up chip package process that continued.So, chip-packaging structure technique of the present invention can be produced the chip-packaging structure without support plate core layer structure, thereby the thickness of chip-packaging structure is minimized.In addition, the present invention first with dielectric layer in conjunction with patterned metal layer, form again afterwards the packing colloid that covers chip, patterned metal layer and dielectric layer, by this two stage sealing adhesives operation, make chip-packaging structure of the present invention there are two kinds of glue-lines, therefore can be by selecting the glue material of two kinds of different heat expansion coefficients (coefficients of thermal expansion, CTE) to adjust the situation of chip-packaging structure warpage.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to Fig. 1 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of one embodiment of the invention.
Fig. 2 A to Fig. 2 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of another embodiment of the present invention.
Fig. 3 A to Fig. 3 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of another embodiment of the present invention.
Fig. 4 A to Fig. 4 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of another embodiment of the present invention.
[symbol description]
100,200,300,400: chip-packaging structure
100a, 200a, 300a, 400a: sphere grid array encapsulation
100b, 200b, 300b, 400b: pad lattice array package
110,210,310,410: the first carriers
112,212,312: first surface
120,220,320,420: metal level
122,222,322,422: patterned metal layer
124a, 224a, 324a, 424a: connection pad
130,230,330,430: dielectric layer
132,432: opening
140,240,340,440: the second carriers
150,250,350,450: chip
160,260,360,460: packing colloid
170,270,370,470: soldered ball
180,280,380,480: pad type terminal
226,324: articulamentum
226a, 326a: conductive trace
228: patterning coating
Embodiment
Figure 1A to Fig. 1 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of one embodiment of the invention.Referring to Figure 1A and Figure 1B, in the present embodiment, first the manufacture method of chip-packaging structure comprises the following steps:, one first carrier 110 is provided.The first carrier 110 comprises a first surface 112 and a patterned metal layer 122.Patterned metal layer 122 is arranged on first surface 112.Specifically, in the present embodiment, the method that patterned metal layer 122 is arranged on first surface 112 can as shown in Figure 1A, first form a metal level 120 on the first surface 112 of the first carrier 110.Then, more as shown in Figure 1B, metal level 120 is carried out to a Patternized technique, to form above-mentioned patterned metal layer 122, patterned metal layer 122 comprises a plurality of conductive trace 122a, and wherein, Patternized technique is for example etch process.
Then, please refer to Fig. 1 C, form a dielectric layer 130 on first surface 112.In the present embodiment, dielectric layer 130 is overlay pattern metal levels 122 comprehensively.Particularly, dielectric layer 130 is for example packing colloid, and is covered on patterned metal layer 122 by for example mode of mold encapsulating, but the material that the present invention does not limit to dielectric layer 130 with and be formed at the mode on first surface 112.Then,, referring to Fig. 1 C and Fig. 1 D, the patterned metal layer 122 on the first carrier 110 in Fig. 1 C and dielectric layer 130 are transferred on the second carrier 140 of Fig. 1 D.Specifically, the mode that shifts patterned metal layer 122 and dielectric layer 130 is for example for the second carrier 140 being attached on the surface of dielectric layer 130 of Fig. 1 C, then removes the first carrier 110, to expose patterned metal layer 122.
Please then with reference to Fig. 1 E, a plurality of chips 150 are set on patterned metal layer 122, make chip 150 be electrically connected patterned metal layer 122, afterwards, form again a packing colloid 160 on the second carrier 140, and packing colloid 160 covers chip 150, patterned metal layer 122 and dielectric layer 130.In the present embodiment, chip 150 is that the mode with for example flip chip bonding is arranged on patterned metal layer 122, but the present invention does not limit to chip 150 is arranged at the mode on patterned metal layer 122, in the embodiment that other do not illustrate of the present invention, the mode that chip 150 also can for example engage with routing is arranged on patterned metal layer 122.
Then, referring to Fig. 1 E and Fig. 1 F, remove the second carrier 140 in Fig. 1 E, to expose dielectric layer 130, form afterwards that a plurality of openings 132 are in dielectric layer 130 as shown in Figure 1 F again, its split shed 132 exposes the patterned metal layer 122 of part.Then, filled conductive material is in opening 132, and to form a plurality of connection pad 124a, wherein connection pad 124a is electrically connected with the conductive trace 122a of patterned metal layer 122 respectively.Afterwards, as shown in Figure 1 G, carry out a singulation technique, this means, packing colloid 160 and the dielectric layer 130 of 150 of diced chips, make 150 of chips separated from one another, to form a plurality of chip-packaging structures 100.So,, complete the technique of the chip-packaging structure 100 of the present embodiment.
It should be noted that, in one embodiment of this invention, a plurality of soldered balls 170 also can be first set respectively on connection pad 124a, carry out again singulation technique, to form a plurality of sphere grid array (Ball Grid Array as shown in Fig. 1 H, BGA) encapsulation 100a, can be connected by soldered ball 170 chip-packaging structure with other electronic components.In the present invention in other embodiment that do not illustrate, also can form after a plurality of connection pad 124a, form a welding resisting layer on dielectric layer 130 and connection pad 124a, and corresponding connection pad 124a forms a plurality of openings to define Zhi Qiu district on welding resisting layer, then arrange again in soldered ball 170Yu Zhiqiu district, soldered ball 170 is connected with connection pad 124a.Certainly, in another embodiment of the present invention, can also be arranged on connection pad 124a by a plurality of pad type terminals 180 replacement soldered balls 170, carry out again singulation technique, to form a plurality of pad lattice array (Land Grid Array as shown in Figure 1 I, LGA) encapsulation 100b, can be connected by pad type terminal 180 chip-packaging structure with other electronic components.
So, the formed chip-packaging structure 100 of the present embodiment does not have support plate core layer structure and anti-welding green paint (Solder Mask), thereby can reduce its package thickness.In addition, the present embodiment is first usingd packing colloid as dielectric layer 130, form again afterwards the packing colloid 160 that covers chip 150, patterned metal layer 122 and dielectric layer 130, by two stage sealing adhesive operations, make the chip-packaging structure 100 of the present embodiment there is two-layer packing colloid, thereby can be by selecting the packing colloid of two kinds of different heat expansion coefficients (coefficients of thermal expansion, CTE) to adjust the situation of chip-packaging structure 100 warpages.
Fig. 2 A to Fig. 2 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of another embodiment of the present invention.At this, should be noted that, the manufacture method of the chip-packaging structure of the present embodiment is roughly similar to the manufacture method of the chip-packaging structure of Figure 1A to Fig. 1 I, the explanation of therefore having omitted constructed content.Explanation about clipped can be with reference to last embodiment, and it is no longer repeated for the present embodiment.
Referring to Fig. 2 A to Fig. 2 C, the manufacture method of the chip-packaging structure of the present embodiment is also that the first carrier 210 is first provided, wherein the first carrier 210 comprises first surface 212 and patterned metal layer 222, and patterned metal layer 222 is arranged on first surface 212.Only in the present embodiment, the method that patterned metal layer 222 is arranged on first surface 212 can first as shown in Figure 2 A, form a metal level 220 on the first carrier 210, and on metal level 220, carry out surface treatment to form a patterning coating 228.Then, as shown in Figure 2 B, the patterning coating 228 of take carries out a Patternized technique as covering curtain to metal level 220, to form patterned metal layer 222, wherein, patterned metal layer 222 comprises an articulamentum 226 and a plurality of connection pad 224a, and connection pad 224a is positioned on articulamentum 226.Specifically, Patternized technique is for example half etch process, and meaning only etches a plurality of connection pad 224a on the metal level 220 of Fig. 2 A, and connection pad 224a is still connected to each other with articulamentum 226.
Then, as shown in Figure 2 C, form dielectric layer 230 on first surface 212.In the present embodiment, dielectric layer 230 is surfaces that are at least filled between connection pad 224a and expose connection pad 224a, and in the embodiment that other do not illustrate of the present invention, dielectric layer 230 also can cover connection pad 224a completely.Particularly, dielectric layer 230 is for example a welding resisting layer (Solder Resist), and the mode being coated with by printing is filled between connection pad 224a, and certainly, the present invention is not as limit.Then,, referring to Fig. 2 C and Fig. 2 D, the patterned metal layer 222 on the first carrier 210 in Fig. 2 C and dielectric layer 230 are transferred on the second carrier 240 of Fig. 2 D.In the present embodiment, the mode that shifts patterned metal layer 222 and dielectric layer 230 is for example for being attached at the second carrier 240 on the surface that dielectric layer 230 in Fig. 2 C and connection pad 224a expose, remove again the first carrier 210, to expose the articulamentum 226 of patterned metal layer 222.Then, more simultaneously with reference to Fig. 2 D and Fig. 2 E, the articulamentum 226 in Fig. 2 D is carried out to a Patternized technique, to form the conductive trace 226a of the plurality of connection pad 224a of a plurality of correspondences in Fig. 2 E.
Then, as shown in Figure 2 F, a plurality of chips 250 are set on the conductive trace 226a of patterned metal layer 222, make chip 250 be electrically connected conductive trace 226a, afterwards, form again a packing colloid 260 on the second carrier 240, and packing colloid 260 covers chip 250, patterned metal layer 222 and dielectric layer 230.In the present embodiment, chip 250 is that the mode with for example flip chip bonding is arranged on patterned metal layer 222, but the present invention does not limit to chip 250, is not arranged at the mode on patterned metal layer 222.Then, referring to Fig. 2 F and Fig. 2 G, remove the second carrier 240 in Fig. 2 F, to expose the surface of connection pad 224a, in the embodiment that other do not illustrate of the present invention, when connection pad 224a is covered by dielectric layer 230, after removing the second carrier 240, corresponding connection pad 224a forms opening in dielectric layer 230, so that the surface of connection pad 224a exposes.Then carry out singulation technique, this means, packing colloid 260 and the dielectric layer 230 of 250 of diced chips, to form a plurality of chip-packaging structures 200 again.So,, complete the technique of the chip-packaging structure 200 of the present embodiment.
It should be noted that, in one embodiment of this invention, also can be as described in last embodiment, a plurality of soldered balls 270 are first set respectively on the surface of connection pad 224a exposure, carry out again singulation technique, to form a plurality of sphere grid array encapsulation 200a as shown in Fig. 2 H, chip-packaging structure can be connected by soldered ball 270 with other electronic components.In the present invention in other embodiment that do not illustrate, also can be after removing the second carrier 240 and connection pad 224a exposed, form a welding resisting layer on dielectric layer 230 and connection pad 224a, and corresponding connection pad 224a forms a plurality of openings on welding resisting layer, to define Zhi Qiu district, then arrange again in soldered ball 270Yu Zhiqiu district, soldered ball 270 is connected with connection pad 224a.And in another embodiment of the present invention, can also be arranged on the surface of connection pad 224a exposure by a plurality of pad type terminals 280 replacement soldered balls 270, carry out again singulation technique, to form a plurality of pad lattice array package 200b as shown in Fig. 2 I, chip-packaging structure can be connected by pad type terminal 280 with other electronic components.
Fig. 3 A to Fig. 3 I is the section signal according to the manufacture method of a kind of chip-packaging structure of another embodiment of the present invention.At this, should be noted that, the manufacture method of the chip-packaging structure of the present embodiment is roughly similar to the manufacture method of the chip-packaging structure of Figure 1A to Fig. 1 I, the explanation of therefore having omitted constructed content.Explanation about clipped can be with reference to above-described embodiment, and it is no longer repeated for the present embodiment.
Referring to Fig. 3 A to Fig. 3 C, the manufacture method of the chip-packaging structure of the present embodiment is also to provide the first carrier 310, wherein the first carrier 310 comprises first surface 312 and patterned metal layer 322, and patterned metal layer 322 is arranged on first surface 312.Only in the present embodiment, the method that patterned metal layer 322 is arranged on first surface 312 can be first as shown in Figure 3A, one metal level 320 is provided, wherein metal level 320 comprises an articulamentum 324 and a plurality of conductive trace 326a, conductive trace 326a is positioned on articulamentum 324, that is to say, conductive trace 326a is connected to each other with articulamentum 324.Then, please refer to Fig. 3 B, metal level 320 is arranged on the first carrier 310, make conductive trace 326a attach the first carrier 310, afterwards, referring to Fig. 3 B and Fig. 3 C, the articulamentum 324 of the metal level 320 in Fig. 3 B is carried out to Patternized technique, to form the connection pad 324a of a plurality of corresponding conductive trace 326a.Above-mentioned patterned metal layer 322 is comprised of the connection pad 324a of conductive trace 326a and corresponding conductive trace 326a.
Then, please refer to Fig. 3 D, form dielectric layer 330 on first surface 312.In the present embodiment, dielectric layer 330 is surfaces that are at least filled between connection pad 324a and conductive trace 326a and expose connection pad 324a, and in the embodiment that other do not illustrate of the present invention, dielectric layer 330 also can cover connection pad 324a completely.Particularly, dielectric layer 330 is for example welding resisting layer, and the mode being coated with by printing is filled between connection pad 324a and conductive trace 326a, or dielectric layer 330 is for example packing colloid, and be filled between connection pad 324a and conductive trace 326a and cover connection pad 324a by for example mode of mold encapsulating, certainly, the present invention is not as limit.Afterwards, referring to Fig. 3 D and Fig. 3 E, the patterned metal layer 322 on the first carrier 310 in Fig. 3 D and dielectric layer 330 are transferred on one second carrier 340.In the present embodiment, the mode that shifts patterned metal layer 322 and dielectric layer 330 is for example that the second carrier 340 is attached on the dielectric layer 330 of Fig. 3 D and the surface of connection pad 324a exposure, then removes the first carrier 310, to expose conductive trace 326a.
Hold above-mentionedly, shown in Fig. 3 F, a plurality of chips 350 are set upper in the conductive trace 326a of patterned metal layer 322, make chip 350 be electrically connected conductive trace 326a.Afterwards, then form a packing colloid 360 on the second carrier 340, and packing colloid 360 covers chip 350, patterned metal layer 322 and dielectric layer 330.Then, referring to Fig. 3 F and Fig. 3 G, remove the second carrier 340 in Fig. 3 F to expose connection pad 324a, in the embodiment that other do not illustrate of the present invention, if connection pad 324a is covered by dielectric layer 330,, after removing the second carrier 340, corresponding connection pad 324a forms opening in dielectric layer 330, so that the surface of connection pad 324a exposes.Then carry out again singulation technique, to form a plurality of chip-packaging structures 300.So,, complete the technique of the chip-packaging structure 300 of the present embodiment.It should be noted that, in one embodiment of this invention, a plurality of soldered balls 370 can be first set respectively on the surface of connection pad 324a exposure, carry out again singulation technique, to form a plurality of sphere grid array encapsulation 300a as shown in Fig. 3 H, chip-packaging structure can be connected by soldered ball 370 with other electronic components.In the present invention in other embodiment that do not illustrate, can be after removing the second carrier 340 and connection pad 324a exposed, form a welding resisting layer on dielectric layer 330 and connection pad 324a, and corresponding connection pad 324a forms a plurality of openings on welding resisting layer, to define Zhi Qiu district, then arrange again in soldered ball 370Yu Zhiqiu district, soldered ball 370 is connected with connection pad 324a.In another embodiment of the present invention, can also be arranged at connection pad 324a above by a plurality of pad type terminals 380 replacement soldered balls 370, then carry out singulation technique, to form a plurality of pad lattice array package 300b as shown in Fig. 3 I.Chip-packaging structure can be connected with other electronic components by pad type terminal 380.
Fig. 4 A to Fig. 4 I is the generalized section according to the manufacture method of a kind of chip-packaging structure of another embodiment of the present invention.At this, should be noted that, the manufacture method of the chip-packaging structure of the present embodiment is roughly similar to the manufacture method of the chip-packaging structure of Figure 1A to Fig. 1 I, the explanation of therefore having omitted constructed content.Explanation about clipped can be with reference to above-described embodiment, and it is no longer repeated for the present embodiment.
Please refer to Fig. 4 A, first the manufacture method of the chip-packaging structure of the present embodiment comprises the following steps:, one first carrier 410 is provided.The first carrier 410 comprises a metal level 420, is arranged on the first carrier 410.Then, as shown in Figure 4 B, form a dielectric layer 430 on metal level 420.Afterwards, referring to Fig. 4 B and Fig. 4 C, the metal level 420 on the first carrier 410 in Fig. 4 B and dielectric layer 430 are transferred on the second carrier 440 in Fig. 4 C.In the present embodiment, the mode that shifts metal level 420 and dielectric layer 430 is for example for the second carrier 440 being attached on the surface of dielectric layer 430 of Fig. 4 B, then removes the first carrier 410, to expose metal level 420.Then, referring to Fig. 4 C and Fig. 4 D, the metal level 420 in Fig. 4 C is carried out to a Patternized technique, to form the patterned metal layer 422 of Fig. 4 D, wherein patterned metal layer 422 comprises a plurality of conductive trace 422a.In other words, the manufacture method of the chip-packaging structure of the present embodiment is first to form a metal level 420 on the first carrier 410, dielectric layer 430 is set again on metal level 420, then shift metal level 420 and dielectric layer 430 to second carriers 440, just carry out afterwards Patternized technique to form patterned metal layer 422.Previous embodiment, for forming at the beginning a patterned metal layer on the first carrier, just continues afterwards dielectric layer is set, shifts the steps such as patterned metal layer and dielectric layer to the second carrier.
Hold above-mentioned, referring again to Fig. 4 E, a plurality of chips 450 are set on patterned metal layer 422, make chip 450 be electrically connected patterned metal layer 422, afterwards, form again a packing colloid 460 on the second carrier 440, and packing colloid 460 covers chip 450, patterned metal layer 422 and dielectric layer 430.In the present embodiment, chip 450 is that mode with for example flip chip bonding is arranged on patterned metal layer 422.Then, referring to Fig. 4 E and Fig. 4 F, remove the second carrier 440 in Fig. 4 E with exposed dielectric layer 430, afterwards, then form a plurality of openings 432 in the dielectric layer 430 exposing.Opening 432 exposes the patterned metal layer 422 of part.Then recharge conduction material in opening 432, to form a plurality of connection pad 424a.Afterwards, as shown in Figure 4 G, carry out a singulation technique, this means, packing colloid 460 and the dielectric layer 430 of 450 of diced chips, to form a plurality of chip-packaging structures 400.So,, complete the technique of the chip-packaging structure 400 of the present embodiment.It should be noted that, in one embodiment of this invention, a plurality of soldered balls 470 can be first set respectively upper in connection pad 424a, then carry out singulation technique, to form a plurality of sphere grid array encapsulation 400a as shown in Fig. 4 H, chip-packaging structure can be connected by soldered ball 470 with other electronic components.In another embodiment of the present invention, can also be arranged on connection pad 424a by a plurality of pad type terminals 480 replacement soldered balls 470, carry out again singulation technique, to form a plurality of pad lattice array package 400b as shown in Fig. 4 I, chip-packaging structure can be connected by pad type terminal 480 with other electronic components.
In sum, the present invention is prior to forming patterned metal layer and dielectric layer on the first carrier, again patterned metal layer and dielectric layer are transferred on the second carrier to carry out follow-up chip join, to cover the techniques such as packing colloid, afterwards, then remove the second carrier and the follow-up chip package process that continued.In addition, the present invention also can be prior to forming a metal level and dielectric layer on the first carrier, again metal level and dielectric layer are transferred on the second carrier, then just metal level is carried out to patterning, and carry out follow-up chip join, cover the techniques such as packing colloid, afterwards, then remove the second carrier, with the follow-up chip package process that continued.So, chip-packaging structure technique of the present invention can be produced the chip-packaging structure without support plate core layer structure, thereby the thickness of chip-packaging structure is minimized.In addition, the present invention first with dielectric layer in conjunction with patterned metal layer, form again afterwards the packing colloid that covers chip, patterned metal layer and dielectric layer, by this two stage sealing adhesives operation, make chip-packaging structure of the present invention there are two kinds of glue-lines, therefore can be by selecting the glue material of two kinds of different heat expansion coefficients (coefficients of thermal expansion, CTE) to adjust the situation of chip-packaging structure warpage.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (17)
1. a manufacture method for chip-packaging structure, is characterized in that, comprising:
The first carrier is provided, and this first carrier comprises first surface and patterned metal layer, and this patterned metal layer is arranged on this first surface;
Form dielectric layer on this first surface, to cover this patterned metal layer;
This patterned metal layer on this first carrier and this dielectric layer are transferred on the second carrier;
A plurality of chips are set on this patterned metal layer, make the plurality of chip be electrically connected this patterned metal layer;
Form packing colloid on this second carrier, and this packing colloid covers the plurality of chip, this patterned metal layer and this dielectric layer;
Remove this second carrier; And
Cut this packing colloid and this dielectric layer of the plurality of chip chamber, to form a plurality of chip-packaging structures.
2. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, this first carrier is provided, and this first carrier comprises that the step of this first surface and this patterned metal layer more comprises:
Form metal level on this first carrier; And
This metal level is carried out to Patternized technique, and to form this patterned metal layer, this patterned metal layer comprises a plurality of conductive traces.
3. the manufacture method of chip-packaging structure as claimed in claim 2, is characterized in that, when this patterned metal layer on this first carrier and this dielectric layer are transferred on this second carrier, this dielectric layer attaches this second carrier.
4. the manufacture method of chip-packaging structure as claimed in claim 3, is characterized in that, more comprises:
After removing this second carrier, form in a plurality of these dielectric layers that are opened on exposure, the plurality of opening exposes this patterned metal layer of part; And
Filled conductive material is in the plurality of opening, and to form a plurality of connection pads, the plurality of connection pad is electrically connected with the plurality of conductive trace respectively.
5. the manufacture method of chip-packaging structure as claimed in claim 4, is characterized in that, more comprises:
A plurality of soldered balls are set respectively on the plurality of connection pad.
6. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, this first carrier is provided, and this first carrier comprises that the step of this first surface and this patterned metal layer more comprises:
Form metal level on this first carrier; And
This metal level is carried out to Patternized technique, and to form this patterned metal layer, this patterned metal layer comprises articulamentum and a plurality of connection pad, and the plurality of connection pad is positioned on this articulamentum.
7. the manufacture method of chip-packaging structure as claimed in claim 6, is characterized in that, this dielectric layer is at least filled between the plurality of connection pad.
8. the manufacture method of chip-packaging structure as claimed in claim 7, is characterized in that, when this patterned metal layer on this first carrier and this dielectric layer are transferred on this second carrier, this dielectric layer attaches this second carrier.
9. the manufacture method of chip-packaging structure as claimed in claim 8, is characterized in that, more comprises:
After this patterned metal layer on this first carrier and this dielectric layer are transferred on this second carrier, this articulamentum is carried out to Patternized technique, to form the conductive trace of the plurality of connection pad of a plurality of correspondences, so that the plurality of chip is arranged on the plurality of conductive trace, make the plurality of chip be electrically connected the plurality of conductive trace.
10. the manufacture method of chip-packaging structure as claimed in claim 9, is characterized in that, more comprises:
Remove after this second carrier, a plurality of soldered balls are set respectively on the plurality of connection pad.
The manufacture method of 11. chip-packaging structures as claimed in claim 1, is characterized in that, this first carrier is provided, and this first carrier comprises that the step of this first surface and this patterned metal layer more comprises:
Metal level is provided, and this metal level comprises articulamentum and a plurality of conductive trace, and the plurality of conductive trace is positioned on this articulamentum;
This metal level is arranged on this first carrier, makes the plurality of conductive trace attach this first carrier; And
This articulamentum to this metal level carries out Patternized technique, and to form the connection pad of the plurality of conductive trace of a plurality of correspondences, wherein this patterned metal layer comprises the plurality of conductive trace and the plurality of connection pad.
The manufacture method of 12. chip-packaging structures as claimed in claim 11, is characterized in that, this dielectric layer is at least filled between the plurality of conductive trace and the plurality of connection pad.
The manufacture method of 13. chip-packaging structures as claimed in claim 12, is characterized in that, when this patterned metal layer on this first carrier and this dielectric layer are transferred on this second carrier, this dielectric layer attaches this second carrier.
The manufacture method of 14. chip-packaging structures as claimed in claim 13, is characterized in that, more comprises:
Remove after this second carrier, a plurality of soldered balls are set respectively on the plurality of connection pad.
The manufacture method of 15. 1 kinds of chip-packaging structures, is characterized in that, comprising:
The first carrier is provided, and this first carrier comprises metal level, is arranged on this first carrier;
Form dielectric layer on this metal level;
This metal level on this first carrier and this dielectric layer are transferred on the second carrier, and wherein this dielectric layer attaches this second carrier;
Remove this first carrier to expose this metal level;
This metal level is carried out to Patternized technique, and to form patterned metal layer, this patterned metal layer comprises a plurality of conductive traces;
A plurality of chips are set on this patterned metal layer, make the plurality of chip be electrically connected this patterned metal layer;
Form packing colloid on this second carrier, and this packing colloid covers the plurality of chip, this patterned metal layer and this dielectric layer;
Remove this second carrier; And
Cut this packing colloid and this dielectric layer of the plurality of chip chamber, to form a plurality of chip-packaging structures.
The manufacture method of 16. chip-packaging structures as claimed in claim 15, is characterized in that, more comprises:
After removing this second carrier, form in a plurality of these dielectric layers that are opened on exposure, the plurality of opening exposes this patterned metal layer of part; And
Filled conductive material is in the plurality of opening, and to form a plurality of connection pads, the plurality of connection pad is electrically connected with the plurality of conductive trace respectively.
The manufacture method of 17. chip-packaging structures as claimed in claim 16, is characterized in that, more comprises:
A plurality of soldered balls are set respectively on the plurality of connection pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102117579 | 2013-05-17 | ||
| TW102117579A TWI550732B (en) | 2013-05-17 | 2013-05-17 | Manufacturing method of chip package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104167369A true CN104167369A (en) | 2014-11-26 |
| CN104167369B CN104167369B (en) | 2017-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310336975.7A Active CN104167369B (en) | 2013-05-17 | 2013-08-05 | Manufacturing method of chip packaging structure |
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| Country | Link |
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| CN (1) | CN104167369B (en) |
| TW (1) | TWI550732B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224002A (en) * | 2019-06-18 | 2019-09-10 | 京东方科技集团股份有限公司 | A kind of microLED panel preparation method and Preparation equipment |
| CN111883502A (en) * | 2020-08-03 | 2020-11-03 | 中国电子科技集团公司第三十八研究所 | Solder micro-bump array preparation method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3345541B2 (en) * | 1996-01-16 | 2002-11-18 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| TW512500B (en) * | 2000-12-05 | 2002-12-01 | Jr-Gung Huang | Transfer bump encapsulation |
| TWI308383B (en) * | 2006-06-02 | 2009-04-01 | Chipmos Technologies Inc | Chip package with array pads and method for manufacturing the same |
| US8258012B2 (en) * | 2010-05-14 | 2012-09-04 | Stats Chippac, Ltd. | Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die |
-
2013
- 2013-05-17 TW TW102117579A patent/TWI550732B/en active
- 2013-08-05 CN CN201310336975.7A patent/CN104167369B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110224002A (en) * | 2019-06-18 | 2019-09-10 | 京东方科技集团股份有限公司 | A kind of microLED panel preparation method and Preparation equipment |
| CN111883502A (en) * | 2020-08-03 | 2020-11-03 | 中国电子科技集团公司第三十八研究所 | Solder micro-bump array preparation method |
| CN111883502B (en) * | 2020-08-03 | 2022-07-01 | 中国电子科技集团公司第三十八研究所 | Solder micro-bump array preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI550732B (en) | 2016-09-21 |
| CN104167369B (en) | 2017-03-01 |
| TW201445649A (en) | 2014-12-01 |
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