CN107316819A - Chip package and chip packaging process - Google Patents
Chip package and chip packaging process Download PDFInfo
- Publication number
- CN107316819A CN107316819A CN201610471869.3A CN201610471869A CN107316819A CN 107316819 A CN107316819 A CN 107316819A CN 201610471869 A CN201610471869 A CN 201610471869A CN 107316819 A CN107316819 A CN 107316819A
- Authority
- CN
- China
- Prior art keywords
- chip
- carrier plate
- line carrier
- packing colloid
- conductive pole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012858 packaging process Methods 0.000 title abstract 3
- 239000000084 colloidal system Substances 0.000 claims abstract description 82
- 238000012856 packing Methods 0.000 claims description 74
- 239000004020 conductor Substances 0.000 claims description 47
- 238000004519 manufacturing process Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 21
- 238000007747 plating Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 abstract description 8
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 59
- 238000003466 welding Methods 0.000 description 26
- 239000012792 core layer Substances 0.000 description 12
- 238000005538 encapsulation Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging body and a chip packaging process, which comprises the following steps: the circuit board comprises a circuit carrier plate with a conductive column, a chip, a packaging colloid, a conductive layer and a plurality of external terminals. The packaging colloid is arranged on the circuit carrier plate and covers the chip and the conductive columns. The top surfaces of the conductive posts are exposed outside the packaging adhesive and are arranged on the circuit carrier plate. The chip is disposed on the circuit carrier, and the circuit carrier is electrically connected to the chip through at least one bonding wire. The external terminal is located on the circuit carrier plate, is located on the different side of the circuit carrier plate with the chip, and is electrically connected with the chip through the circuit carrier plate. The packaging colloid is provided with a conductive layer, and the conductive layer is connected with the top surface of the conductive column, so that the conductive layer is electrically connected with the circuit carrier plate and the chip through the conductive column. In summary, the technical solution of the present invention can improve the packaging yield of the chip packaging process.
Description
Technical field
The invention relates to a kind of chip packing-body and chip encapsulating manufacturing procedure, and in particular to one kind
Chip packing-body and chip encapsulating manufacturing procedure with conductive pole.
Background technology
In semiconductor industry, the production of IC (Integrated Circuits, IC) is broadly divided into three
Stage：Manufacture, the making of IC and encapsulation of chip (Package) of wafer (wafer) etc..Its
In, chip system is via wafer manufacturing, circuit design, light shield manufacture, circuit production and cutting crystal wafer etc.
Step and complete, and each is cut formed chip by wafer, the contact on via chip with it is outer
After portion's signal is electrically connected with, chip can be coated with packing colloid material again, its purpose encapsulated is to prevent
Only chip is influenceed by moisture, heat, noise, and provides electric connection between chip and external circuit
Medium, so i.e. complete IC production.
In the manufacturing process of communication element, after communication chip is coated with packing colloid, one must be entered
Step makes exterior antenna, and the making of this exterior antenna includes being formed exterior antenna in itself and is connected to outside
Contact conductor between antenna and communication chip.In general, foregoing contact conductor is typically in encapsulation
Colloid is made after completing with laser drill inserting for conductive material of collocation.
However, because packing colloid is blocked up and energy of laser is difficult to control, in laser drill mode
Contact openings are formed in packing colloid and are encountered by the problem of processing procedure nargin (process window) is not enough.Cause
This, being electrically connected between exterior antenna and communication chip is it is possible that open a way or electrical characteristic is not good
The problems such as, and then cause the encapsulation yield of communication element can not be effectively elevated.Therefore, how further
The encapsulation yield of communication element is lifted, it is real into the problem for desiring most ardently solution at present.
The content of the invention
The present invention provides various chips packaging body and various chips encapsulation procedure.
The present invention provides a kind of chip encapsulating manufacturing procedure, and it comprises the following steps.Line carrier plate, this line are provided
There is conductive pole on road-load plate.Chip is placed on line carrier plate, its chips by an at least bonding wire with
Line carrier plate is electrically connected with.Packing colloid is formed on line carrier plate, with coating chip and conductive pole.Move
Except the packing colloid of part, to expose the top surface of conductive pole.Formed on packing colloid and conductive capital
The conductive layer of face connection, this conductive layer is electrically connected with by line carrier plate and chip.The shape on line carrier plate
Into multiple outside terminals, this outside terminal and chip are in the not homonymy of line carrier plate, and outside terminal is logical
Line carrier plate is crossed to be electrically connected with chip.
The present invention provides a kind of chip packing-body, and it includes line carrier plate, chip, packing colloid, conduction
Layer and multiple outside terminals.Line carrier plate has conductive pole.Chip is configured on line carrier plate, and
It is electrically connected with by an at least bonding wire and line carrier plate.Packing colloid is configured on line carrier plate, wherein sealing
Colloid coating chip and conductive pole are filled, and the top surface of conductive pole is exposed to outside packing colloid.Conductive layer is configured
It is connected on packing colloid with the top surface with conductive pole, wherein conductive layer is electrical with chip by line carrier plate
Connection.Outside terminal and chip are located at the not homonymy of line carrier plate, and outside terminal by line carrier plate with
Chip is electrically connected with.
In one embodiment of this invention, removing the method for the packing colloid of part includes grinding.
In one embodiment of this invention, forming the method for conductive layer includes plating.
In one embodiment of this invention, conductive pole is located at the homonymy of line carrier plate, and conductive pole with chip
Height be more than chip thickness.
The present invention provides another chip encapsulating manufacturing procedure, and it comprises the following steps.Line carrier plate is provided, this
There is conductive pole on line carrier plate.Chip is placed in line carrier plate, its chips by an at least bonding wire with
Line carrier plate is electrically connected with.Packing colloid is formed on line carrier plate, with coating chip and conductive pole.Move
Except the packing colloid of part, it is open with being formed in packing colloid, and this opening exposes the top of conductive pole
Face.Contact conductor is inserted in the opening.The conduction with contacting the connection of conductor top surface is formed on packing colloid
Layer, this conductive layer is electrically connected with by contacting conductor and line carrier plate with chip.
The present invention provides another chip packing-body, and it includes line carrier plate, contact conductor, chip, envelope
Fill colloid, conductive layer and multiple outside terminals.Line carrier plate has conductive pole.Conductor configuration is contacted to exist
On conductive pole.Chip is configured on line carrier plate, and is electrically connected with line carrier plate.Packing colloid is matched somebody with somebody
Put on line carrier plate, wherein packing colloid coating chip, conductive pole and contact conductor, and contact conductor
Top surface outside the packing colloid.Conductive layer configuration is on packing colloid with the top surface company with contacting conductor
Connect, wherein conductive layer is electrically connected with by contacting conductor and line carrier plate with chip.Outside terminal and chip
Positioned at the not homonymy of line carrier plate, and outside terminal passes through line carrier plate and chip electric connection.
In another embodiment of the invention, the packing colloid for removing part is opened with being formed in packing colloid
The method of mouth includes laser drill.
In another embodiment of the invention, forming the method for conductive layer includes plating.
In another embodiment of the invention, also it is included on line carrier plate and forms multiple outside terminals, its
Middle outside terminal is located at the not homonymy of line carrier plate with chip, and outside terminal passes through line carrier plate and chip
It is electrically connected with.
In another embodiment of the invention, conductive pole, contact conductor and chip are located at the same of line carrier plate
Side.
Based on above-mentioned, the above embodiment of the present invention first formation on line carrier plate before packing colloid is formed
Conductive pole, this process sequence can lift the encapsulation yield of chip encapsulating manufacturing procedure.Further, since conductive pole
Formation of the making earlier than packing colloid, therefore the thickness of packing colloid does not interfere with the making of conductive pole
Yield.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate
Accompanying drawing is described in detail below.
Brief description of the drawings
Figure 1A to Fig. 1 D is that a kind of manufacturing process of chip packing-body according to first embodiment of the invention shows
It is intended to；
Fig. 1 D are the diagrammatic cross-sections of the chip packing-body according to first embodiment of the invention；
Fig. 2A to Fig. 2 D is that a kind of manufacturing process of chip packing-body according to second embodiment of the invention shows
It is intended to；
Fig. 2 D are the diagrammatic cross-sections of the chip packing-body according to second embodiment of the invention.
Description of reference numerals：
200、200’：Chip packing-body；
210：Line carrier plate；
210a：First surface；
210b：Second surface；
S1、S2：Surface；
212a：First connection pad；
212b：Second connection pad；
214a：First welding resisting layer；
214b：Second welding resisting layer；
C：Conductor；
216：Outside terminal；
220、220’：Conductive pole；
H、H’：Highly；
220a：Top surface；
230：Chip；
240：Bonding wire；
250、250’、251：Packing colloid；
252：Contact openings；
T1、T2、T3：Thickness；
260：Contact conductor；
260a：Top surface；
270：Conductive layer.
Embodiment
Figure 1A to Fig. 1 D is that a kind of manufacturing process of chip packing-body according to first embodiment of the invention shows
It is intended to.First, Figure 1A is refer to there is provided the line carrier plate 210 for having been formed with conductive pole 220, wherein
Line carrier plate 210 has first surface 210a and second surface 210b, and conductive pole 220 is located at circuit
On the first surface 210a of support plate 210.Specifically, line carrier plate 210 includes core layer 212, led
Body C, the first connection pad 212a, the second connection pad 212b, the first welding resisting layer 214a and the second welding resisting layer 214b,
Wherein core layer 212 is hard or the dielectric material of pliability, the first connection pad 212a and the second connection pad 212b
Respectively on two apparent surface S1, S2 of core layer 212, and the first connection pad 212a is respectively with passing through
The conductor C being embedded in core layer 212 is electrically connected with corresponding second connection pad 212b.First welding resisting layer
214a and the second welding resisting layer 214b are respectively overlay on two apparent surface S1, S2 of core layer 212, and
Expose the first connection pad 212a and the second connection pad 212b.In one embodiment, conductive pole 220 is located at circuit
On the surface S1 of the core layer 212 of support plate 210, and conductive pole 220 is, for example, to be embedded in the first welding resisting layer
In 214a.However, the present invention does not limit conductive pole 220 and must be embedded in the first welding resisting layer 214a.Change speech
It, in other embodiments, conductive pole 220 can be disposed on line carrier plate 210, and (i.e. first is anti-welding
Layer 214a) first surface 210a on.Or, conductive pole 220 is except that can be embedded in the first welding resisting layer 214a
In, also further it can be embedded in or extend in core layer 212.
In the present embodiment, line carrier plate 210 is, for example, to have the printed circuit board (PCB) of individual layer circuit or have
The printed circuit board (PCB) of multilayer line.Foregoing line carrier plate 210 can be hard line carrier plate or pliability line
Road-load plate.First connection pad 212a and the second connection pad 212b material be, for example, copper, nickel, gold, tin or on
The combination stated, the first welding resisting layer 214a and the second welding resisting layer 214b material be, for example, epoxy resin or
Other anti-welding materials, and the material of conductive pole 220 is, for example, copper or copper alloy.
Then, Figure 1B is refer to, chip 230 is placed on the first surface 210a of line carrier plate 210,
So that chip 230 is located at the same side of line carrier plate 210 with conductive pole 220, then, pass through at least one
Bonding wire 240 makes chip 230 be electrically connected with the first connection pad 212a on line carrier plate 210.
As shown in Figure 1B, foregoing conductive pole 220, chip 230 and bonding wire 240 are all located at line carrier plate
210 the same side.In one embodiment, chip 230 is configured on welding resisting layer 214a surface.Complete
Into after the engagement of chip 230 and line carrier plate 210, chip 230 can by line carrier plate 210 it
Conductor C is electrically connected with conductive pole 220.
After engagement of the chip 230 with line carrier plate 210 is completed, then, on line carrier plate 210
Packing colloid 250 is formed, with coated with conductive post 220 and chip 230.Specifically, foregoing packaging plastic
Body 250 in addition to coated with conductive post 220 and chip 230, can further coat bonding wire 240 and by
The first connection pad 212a that welding resisting layer 214a is exposed.In the present embodiment, such as communication chip of chip 230,
Such as gold thread of bonding wire 240, and packing colloid 250 is, for example, in the way of ejection formation (mold injection)
Make, and the thickness and the camber of bonding wire 240 of chip 230 determine the packing colloid 250 to be formed
Thickness T1.Herein, the thickness T1 of packing colloid 250 is enough to cover the top surface 220a of conductive pole 220.
After the making of packing colloid 250 is completed, the present embodiment can be in the second table of line carrier plate 210
Outside terminal 216 is formed on the 210b of face, wherein outside terminal 216 by welding resisting layer 214b with being exposed
The second connection pad 212b be electrically connected with.For example, outside terminal 216 can for soldered ball, projection etc., and
Chip 230 can pass through bonding wire 240, the first connection pad 212a, conductor C, the second connection pad 212b and outside
Terminal 216 is electrically connected with outer member.
Then, Fig. 1 C are refer to, the packing colloid 250 of part are removed, until the top surface of conductive pole 220
220a is exposed.In the present embodiment, packing colloid 250 can by grind processing procedure, etch process or its
He carries out thinning by processing procedure, to form packing colloid 250 '.It is worth noting that, when the envelope that thickness is T1
When dress colloid 250 is thinned and turns into packing colloid 250 ', the thickness of packing colloid 250 ' is T2..
Fig. 1 D are refer to, after packing colloid 250 ' is formed, then in shape on packing colloid 250 '
Into a conductive layer 270, this conductive layer 270 is connected with the top surface 220a of conductive pole 220, makes conductive layer 270
It is electrically connected with by conductive pole 220, line carrier plate 210 and chip 230.In addition, in the present embodiment,
The method for forming conductive layer 270 is, for example, plating, sputter or other appropriate film forming processing procedures, conductive layer 270
Material be, for example, metal.In the present embodiment, conductive layer 270 can be used as antenna stack.
In the present embodiment, as shown in figs 1C and 1D, due to conductive pole 220 can it is pre- it is leading making simultaneously
It is arranged on line carrier plate 210, therefore the present embodiment can be accurately controlled the top surface 220a of conductive pole 220
Flatness so that the top surface of the packing colloid 250 ' after top surface 220a and thinning is trimmed (substantially altogether
Plane), and then enable top surface 220a of the conductive layer 270 being subsequently formed successfully with conductive pole 220
It is electrically connected with.It is conductive in the case where the top surface 220a of conductive pole 220 flatness obtains good control
The top surface 220a of layer 270 and conductive pole 220 can form good Ohmic contact so that overall encapsulation letter
Property is relied to be lifted.
The making of the chip packing-body 200 of the present embodiment can be substantially completed after above-mentioned processing procedure.On
The chip packing-body 200 stated include line carrier plate 210, conductive pole 220, chip 230, bonding wire 240,
Packing colloid 250 ', conductive layer 270 and outside terminal 216.Line carrier plate 210 has first surface
210a and second surface 210b, and conductive pole 220, chip 230, bonding wire 240, packing colloid 250 '
And conductive layer 270 is located on the first surface 210a of line carrier plate 210, outside terminal 216 is located at circuit
On the second surface 210b of support plate 210.In one embodiment, line carrier plate 210 include core layer 212,
Conductor C, the first connection pad 212a, the second connection pad 212b, the first welding resisting layer 214a and the second welding resisting layer
214b, the first connection pad 212a and the second connection pad 212b respectively positioned at core layer 212 two apparent surface S1,
On S2, and the first connection pad 212a respectively with the conductor C by being embedded in core layer 212 and corresponding
Two connection pad 212b are electrically connected with.Chip 230 is sudden and violent with by welding resisting layer 214a institutes by an at least bonding wire 240
The the first connection pad 212a exposed is electrically connected with.Outside terminal 216 and exposed by welding resisting layer 214b
Second connection pad 212b is electrically connected with.Therefore, chip 230 by an at least bonding wire 240, the first connection pad 212a,
Conductor C, the second connection pad 212b and outside terminal 216 are electrically connected with outer member.Packing colloid 250 '
It is configured on line carrier plate, except coating chip 230 and conductive pole 220, can further coats bonding wire 240
And the first connection pad 212a exposed by welding resisting layer 214a, and conductive pole 220 is exposed conductive pole
220 top surface 220a.Conductive layer 270 is configured on packing colloid 250 ', leads the contact of conductive layer 270
The top surface 220a of electric post 220, and electrically connected by conductive pole 220, line carrier plate 210 and chip 230
Connect.
The manufacturing process of chip packing-body will be illustrated with different embodiments below.In this mandatory declaration
It is that following embodiments adopt the element numbers and partial content of previous embodiment, wherein using identical mark
Number represent identical or approximate element, and eliminate the explanation of constructed content.On omission portion
The explanation divided may be referred to previous embodiment, and following embodiments are no longer repeated.
Fig. 2A to Fig. 2 D is that a kind of manufacturing process of chip packing-body according to second embodiment of the invention shows
It is intended to.First, refer to has conduction in Figure 1A, Figure 1B, Fig. 2A and Fig. 2 B, the present embodiment
The line carrier plate 210 of post 220 ' and the circuit with conductive pole 220 shown in Figure 1A and Figure 1B
Support plate 210 is similar, and difference is therebetween：Formed in the present embodiment (Fig. 2A and Fig. 2 B)
In the conductive pole 220 ' on line carrier plate 210 compared with conductive pole 220 (Figure 1A and Figure 1B) to be short.
Then, Fig. 2 C are refer to, after the making of packing colloid 251 is completed, in packing colloid 251
Middle formation contact openings 252, this contact openings 252 expose the top surface 220a of conductive pole 220 '.Then,
Contact conductor 260 is inserted in contact openings 252, herein, contact conductor 260 and the electricity of conductive pole 220 '
Property connection.The present embodiment can be by etching, grinding drilling, laser drill or other processing procedures in packing colloid
Contact openings 252 are formed in 251.In addition, contact conductor 260 material be, for example, tin cream, silver paste or
Other melting points are less than the conductive materials of the material of conductive pole 220 '.
In the present embodiment, as shown in figs. 2 b and 2 c, due to conductive pole 220 ' can pre-production simultaneously
It is arranged on line carrier plate 210, therefore contact openings 252 of the present embodiment in packing colloid 251 is formed
When, the depth-to-width ratio (aspect ratio) of contact perforate 252 in packing colloid 251 will be effectively reduced so that
Processing time shortens, and then increases production capacity.
Fig. 2 D are refer to, it is then conductive in formation on packing colloid 251 after contact conductor 260 is inserted
Layer 270, so that conductive layer 270 is by contacting conductor 260, conductive pole 220 and line carrier plate 210
It is electrically connected with chip 230.
In the present embodiment, as shown in Fig. 2 C and Fig. 2 D, foregoing contact conductor 260 is in inserting opening
Afterwards, contact conductor 260 has top surface 260a, and wherein top surface 260a will not be packaged colloid 251 and be coated,
And then enable the conductive layer 270 being subsequently formed successfully with to contact the top surface 260a of conductor 260 electrical
Connection.
The making of the chip packing-body 200 ' of the present embodiment can be substantially completed after above-mentioned processing procedure.
Above-mentioned chip packing-body 200 ' include line carrier plate 210, conductive pole 220, chip 230, bonding wire 240,
Packing colloid 251, contact conductor 260, conductive layer 270 and outside terminal 216.Line carrier plate 210 has
Have a first surface 210a and second surface 210b, and conductive pole 220, chip 230, bonding wire 240,
Packing colloid 251, contact conductor 260 and conductive layer 270 are located at the first surface 210a of line carrier plate 210
On, outside terminal 216 is located on the second surface 210b of line carrier plate 210.In one embodiment, line
Road-load plate 210 includes core layer 212, conductor C, the first connection pad 212a, the second connection pad 212b, first
Welding resisting layer 214a and the second welding resisting layer 214b, the first connection pad 212a are located at respectively with the second connection pad 212b
On two apparent surface S1, S2 of core layer 212, and the first connection pad 212a respectively with by being embedded in core
Conductor C in layer 212 is electrically connected with corresponding second connection pad 212b.Chip 230 passes through at least one weldering
Line 240 and the first connection pad 212a exposed by welding resisting layer 214a are electrically connected with.Outside terminal 216
With the second connection pad 212b electric connections exposed by welding resisting layer 214b.Therefore, chip 230 passes through
An at least bonding wire 240, the first connection pad 212a, conductor C, the second connection pad 212b and outside terminal 216
It is electrically connected with outer member.Packing colloid 251 is configured on line carrier plate 210, except coating chip
230th, contact conductor 260 and conductive pole 220, can further coat bonding wire 240 and by welding resisting layer 214a
The the first connection pad 212a exposed, and contact conductor 260 is exposed the top surface 260a for contacting conductor 260.
Conductive layer 270 is configured on packing colloid 251, makes the contact contact conductor 260 of conductive layer 270, and logical
Conductive pole 220, line carrier plate 210 is crossed to be electrically connected with chip 230.
In summary, the above embodiment of the present invention formed packing colloid before prior on line carrier plate formed
Conductive pole, this process sequence can lift the encapsulation yield of chip encapsulating manufacturing procedure.Further, since conductive pole
Formation of the making earlier than packing colloid, therefore the thickness of packing colloid does not interfere with the making of conductive pole
Yield.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still modify to the technical scheme described in foregoing embodiments,
Or equivalent substitution is carried out to which part or all technical characteristic；And these modifications or replacement, and
The essence of appropriate technical solution is not set to depart from the scope of various embodiments of the present invention technical scheme.
Claims (11)
1. a kind of chip encapsulating manufacturing procedure, including：
There is provided has conductive pole on line carrier plate, the line carrier plate；
Chip is placed in line carrier plate, and the chip is passed through an at least bonding wire and line carrier plate electricity
Property connection；
Packing colloid is formed on the line carrier plate to coat the chip and the conductive pole；
The packing colloid of part is removed to expose the top surface of the conductive pole；And
The conductive layer being connected with the top surface of the conductive pole, wherein institute are formed on the packing colloid
Conductive layer is stated to be electrically connected with by the line carrier plate and the chip；
Multiple outside terminals are formed on the line carrier plate, wherein the multiple outside terminal and the core
Piece is located at the not homonymy of the line carrier plate, and the multiple outside terminal passes through the line carrier plate and institute
State chip electric connection.
2. chip encapsulating manufacturing procedure according to claim 1, wherein removing the packing colloid of part
Method include grinding.
3. chip encapsulating manufacturing procedure according to claim 1, wherein forming the method bag of the conductive layer
Include plating.
4. a kind of chip packing-body, including：
Line carrier plate, the line carrier plate has conductive pole；
Chip, is configured on the line carrier plate, and passes through an at least bonding wire and line carrier plate electricity
Property connection；
Packing colloid, is configured on the line carrier plate, wherein the packing colloid coat the chip and
The conductive pole, and the conductive pole top surface outside the packing colloid；
Conductive layer, configuration is connected on the packing colloid with the top surface with the conductive pole, wherein
The conductive layer is electrically connected with by the line carrier plate and the chip；And
Multiple outside terminals, wherein the multiple outside terminal is located at the line carrier plate with the chip
Not homonymy, and the multiple outside terminal passes through the line carrier plate and chip electric connection.
5. chip packing-body according to claim 4, wherein the conductive pole is located at the chip
The homonymy of the line carrier plate, and thickness of the height more than the chip of the conductive pole.
6. a kind of chip encapsulating manufacturing procedure, including：
There is provided has conductive pole on line carrier plate, the line carrier plate；
Chip is placed in line carrier plate, and the chip is passed through an at least bonding wire and line carrier plate electricity
Property connection；
Packing colloid is formed on the line carrier plate to coat the chip and the conductive pole；
The packing colloid of part is removed with forming opening in the packing colloid, wherein the opening
Expose the top surface of the conductive pole；
Contact conductor is inserted in said opening；And
The conductive layer with the top surface connection for contacting conductor is formed on the packing colloid, wherein described
Conductive layer is electrically connected with by the contact conductor and the line carrier plate with the chip.
7. chip encapsulating manufacturing procedure according to claim 6, wherein removing the packing colloid of part
Include laser drill in the method that the opening is formed in the packing colloid.
8. chip encapsulating manufacturing procedure according to claim 6, wherein forming the method bag of the conductive layer
Include plating.
9. chip encapsulating manufacturing procedure according to claim 6, is additionally included on the line carrier plate and is formed
Multiple outside terminals, wherein the multiple outside terminal is located at the difference of the line carrier plate with the chip
Side, and the multiple outside terminal passes through the line carrier plate and chip electric connection.
10. a kind of chip packing-body, including：
Line carrier plate, the line carrier plate has conductive pole；
Conductor is contacted, is configured on the conductive pole；
Chip, is configured on the line carrier plate, and is electrically connected with the line carrier plate；
Packing colloid, is configured on the line carrier plate, wherein the packing colloid cladding chip,
The conductive pole and the contact conductor, and the top surface for contacting conductor is outside packing colloid；
Conductive layer, is configured to be connected with the top surface for contacting conductor on the packing colloid, its
Described in conductive layer pass through the contact conductor and the line carrier plate and the chip are electrically connected with；And
Multiple outside terminals, wherein the multiple outside terminal is located at the line carrier plate with the chip
Not homonymy, and the multiple outside terminal passes through the line carrier plate and chip electric connection.
11. chip packing-body according to claim 10, wherein the conductive pole, the contact are led
Body is located at the homonymy of the line carrier plate with the chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105113070A TWI590349B (en) | 2016-04-27 | 2016-04-27 | Chip package and chip packaging process |
| TW105113070 | 2016-04-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107316819A true CN107316819A (en) | 2017-11-03 |
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ID=60048447
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610471869.3A Pending CN107316819A (en) | 2016-04-27 | 2016-06-24 | Chip package and chip packaging process |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107316819A (en) |
| TW (1) | TWI590349B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI763056B (en) * | 2020-06-10 | 2022-05-01 | 大陸商訊芯電子科技(中山)有限公司 | Semiconductor devices and methods for manufacturing the semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103632988A (en) * | 2012-08-28 | 2014-03-12 | 宏启胜精密电子(秦皇岛)有限公司 | Stacked encapsulation structure and manufacturing method thereof |
| CN104011858A (en) * | 2011-10-17 | 2014-08-27 | 英闻萨斯有限公司 | Package-on-package assembly with wire bond vias |
| CN104037166A (en) * | 2013-03-07 | 2014-09-10 | 日月光半导体制造股份有限公司 | Semiconductor package including antenna layer and manufacturing method thereof |
-
2016
- 2016-04-27 TW TW105113070A patent/TWI590349B/en active
- 2016-06-24 CN CN201610471869.3A patent/CN107316819A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104011858A (en) * | 2011-10-17 | 2014-08-27 | 英闻萨斯有限公司 | Package-on-package assembly with wire bond vias |
| CN103632988A (en) * | 2012-08-28 | 2014-03-12 | 宏启胜精密电子(秦皇岛)有限公司 | Stacked encapsulation structure and manufacturing method thereof |
| CN104037166A (en) * | 2013-03-07 | 2014-09-10 | 日月光半导体制造股份有限公司 | Semiconductor package including antenna layer and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI763056B (en) * | 2020-06-10 | 2022-05-01 | 大陸商訊芯電子科技(中山)有限公司 | Semiconductor devices and methods for manufacturing the semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201738976A (en) | 2017-11-01 |
| TWI590349B (en) | 2017-07-01 |
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