TWI763056B - Semiconductor devices and methods for manufacturing the semiconductor devices - Google Patents

Semiconductor devices and methods for manufacturing the semiconductor devices Download PDF

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TWI763056B
TWI763056B TW109133439A TW109133439A TWI763056B TW I763056 B TWI763056 B TW I763056B TW 109133439 A TW109133439 A TW 109133439A TW 109133439 A TW109133439 A TW 109133439A TW I763056 B TWI763056 B TW I763056B
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layer
chip
substrate
conductive element
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TW202147533A (en
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黃柏仁
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大陸商訊芯電子科技(中山)有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device includes a substrate, a chip, a conductive element, an encapsulation layer, and an antenna element. The chip is disposed on the substrate. The conductive element is disposed on the substrate. The molding layer covers the chip and the conductive element, and the top of the chip and the conductive element are exposed. The antenna element is disposed on the encapsulation layer and is electrically connected to the conductive element.

Description

半導體封裝裝置和半導體封裝裝置製造方法 Semiconductor packaging device and semiconductor packaging device manufacturing method

本發明有關於一種半導體封裝裝置和其製造方法，尤指一種在封膠層上直接印刷天線結構的半導體封裝裝置和其製造方法。 The present invention relates to a semiconductor packaging device and a manufacturing method thereof, in particular to a semiconductor packaging device and a manufacturing method thereof in which an antenna structure is directly printed on a sealing layer.

天線封裝(Antennas in package，AiP)技術是基於封裝材料與工藝，將天線與晶片集成在封裝內，實現系統級無線功能的技術。然而，傳統天線封裝需要在晶片上疊加具有天線模組的電路板，造成整體封裝產品厚度的增加，並且需要額外的製程，導致成本的增加。 Antennas in package (AiP) technology is a technology that integrates antennas and chips in a package based on packaging materials and processes to realize system-level wireless functions. However, the conventional antenna package requires a circuit board with an antenna module to be stacked on the wafer, which increases the thickness of the overall packaged product and requires additional manufacturing processes, resulting in an increase in cost.

有鑑於此，在本發明一實施例中，提供一種降低封裝產品厚度並具有天線模組的半導體封裝裝置和半導體封裝裝置製造方法。 In view of this, in an embodiment of the present invention, a semiconductor packaging device and a method for manufacturing the semiconductor packaging device with reduced thickness of packaging products and having an antenna module are provided.

本發明一實施例揭露一種半導體封裝裝置，包括基板；晶片，設置於所述基板；導電元件，設置於所述基板；封膠層，包覆所述晶片與所述導電元件，並露出所述晶片與所述導電元件的頂部；及天線元件，設置於所述封膠層，並與所述導電元件電性連接。 An embodiment of the present invention discloses a semiconductor packaging device, including a substrate; a chip, disposed on the substrate; a conductive element, disposed on the substrate; a sealing layer, covering the chip and the conductive element, and exposing the The chip and the top of the conductive element; and the antenna element are arranged on the encapsulation layer and electrically connected with the conductive element.

本發明另一實施例揭露一種半導體封裝裝置製造方法，包括提供基板；設置晶片於所述基板；設置導電元件於所述基板；形成封膠層，所述包覆所述晶片與所述導電元件；研磨封膠層，使得所述晶片的頂部與所述導電元件露出；及設置天線元件於所述封膠層，並與所述導電元件電性連接。 Another embodiment of the present invention discloses a method for manufacturing a semiconductor packaging device, which includes providing a substrate; disposing a chip on the substrate; disposing a conductive element on the substrate; forming an encapsulant layer, which covers the chip and the conductive element ; grinding the sealant layer to expose the top of the chip and the conductive element; and disposing an antenna element on the sealant layer and electrically connected to the conductive element.

根據本發明一實施例，所述基板具有線路層，以及與所述線路層電性連接的複數接合墊，所述晶片與所述導電元件透過所述接合墊與所述線路層電性連接。 According to an embodiment of the present invention, the substrate has a circuit layer and a plurality of bonding pads electrically connected to the circuit layer, and the chip and the conductive element are electrically connected to the circuit layer through the bonding pads.

根據本發明一實施例，更包括設置於所述基板的電子元件，所述電子元件包括濾波電路或被動元件。 According to an embodiment of the present invention, it further includes an electronic component disposed on the substrate, and the electronic component includes a filter circuit or a passive component.

根據本發明一實施例，所述天線元件透過網版印刷方式直接貼附於所述封膠層。 According to an embodiment of the present invention, the antenna element is directly attached to the sealing layer by screen printing.

根據本發明一實施例，更包括散熱層，設置於所述晶片上，所述散熱層透過網版印刷方式直接貼附於所述晶片露出所述封膠層的表面。 According to an embodiment of the present invention, it further includes a heat dissipation layer disposed on the chip, and the heat dissipation layer is directly attached to the surface of the chip exposing the sealing layer by screen printing.

根據本發明一實施例，所述天線元件與所述散熱層的底面與所述封膠層的表面共平面。 According to an embodiment of the present invention, the bottom surface of the antenna element and the heat dissipation layer and the surface of the sealing layer are coplanar.

根據本發明一實施例，所述導電元件是由複數銅球疊合而成。 According to an embodiment of the present invention, the conductive element is formed by stacking a plurality of copper balls.

根據本發明實施例，利用封膠層包覆晶片，並在封膠層上直接印刷天線結構，省去了天線基板的厚度，有效縮小封裝產品結合天線的厚度空間，滿足未來更小產品尺寸需求。另外，透過封膠層的設計，方便實踐直接印刷天線的目的，大幅降低產品成本。再者，透過散熱層的設計，進一步提高散熱的效率，有效改善產品的可靠度。 According to the embodiment of the present invention, the encapsulation layer is used to cover the chip, and the antenna structure is directly printed on the encapsulation layer, which saves the thickness of the antenna substrate, effectively reduces the thickness space of the encapsulated product combined with the antenna, and meets the size requirements of smaller products in the future. . In addition, through the design of the sealing layer, it is convenient to practice the purpose of directly printing the antenna, and the product cost is greatly reduced. Furthermore, through the design of the heat dissipation layer, the heat dissipation efficiency is further improved, and the reliability of the product is effectively improved.

100A、100B:半導體封裝裝置 100A, 100B: Semiconductor packaging device

10:基板 10: Substrate

11:接合墊 11: Bond pads

12:晶片 12: Wafer

14:電子元件 14: Electronic Components

16A、16B:導電元件 16A, 16B: Conductive elements

17:封膠層 17: Sealing layer

18:散熱層 18: heat dissipation layer

19:天線元件 19: Antenna Elements

30、40:饋入點 30, 40: Feed point

32、42:輻射體 32, 42: Radiator

圖1A顯示根據本發明一實施例所述的半導體封裝裝置的剖面圖。 FIG. 1A shows a cross-sectional view of a semiconductor package device according to an embodiment of the present invention.

圖1B顯示根據本發明另一實施例所述的半導體封裝裝置的剖面圖。 FIG. 1B shows a cross-sectional view of a semiconductor package device according to another embodiment of the present invention.

圖2A-圖2D顯示根據本發明一實施例所述的半導體封裝裝置的製造方法的剖面圖。 2A-2D are cross-sectional views illustrating a method of manufacturing a semiconductor package device according to an embodiment of the present invention.

圖3A顯示根據本發明一實施例所述的陣列天線的俯視示意圖。 FIG. 3A shows a schematic top view of an array antenna according to an embodiment of the present invention.

圖3B顯示根據本發明一實施例所述的陣列天線的返回損失對頻率的模擬結果曲線圖。 FIG. 3B is a graph showing a simulation result of return loss versus frequency of an array antenna according to an embodiment of the present invention.

圖4A顯示根據本發明一實施例所述的貼片天線的俯視示意圖。 FIG. 4A shows a schematic top view of a patch antenna according to an embodiment of the present invention.

圖4B顯示根據本發明一實施例所述的貼片天線的返回損失對頻率的模擬結果曲線圖。 FIG. 4B is a graph showing a simulation result of return loss versus frequency of a patch antenna according to an embodiment of the present invention.

為了便於本領域普通技術人員理解和實施本發明，下面結合附圖與實施例對本發明進一步的詳細描述，應當理解，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。熟悉此技藝之人士可利用這些實施例或其他實施例所描述之細節及其他可以利用的結構，邏輯和電性變化，在沒有離開本發明之精神與範圍之下以實施發明。 In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the present invention provides many applicable inventive concepts, which can be implemented in various specific forms. Those skilled in the art can utilize the details described in these and other embodiments and other structural, logical and electrical changes that may be utilized to practice the invention without departing from the spirit and scope of the invention.

本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。且實施例中圖式標號之部分重複，係為了簡化說明，並非意指不同實施例之間的關聯性。其中，圖示和說明書中使用之相同的元件編號係表示相同或類似之元件。本說明書之圖示為簡化之形式且並未以精確比例繪製。為清楚和方便說明起見，方向性用語(例如頂、底、上、下以及對角)係針對伴隨之圖示說明。而以下說明所使用之方向性用語在沒有明確使用在以下所附之申請專利範圍時，並非用來限制本發明之範圍。 The present specification provides different embodiments to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, and not for limiting the present invention. In addition, some of the reference numerals in the drawings in the embodiments are repeated for the purpose of simplifying the description, and do not mean the relationship between different embodiments. Wherein, the same element numbers used in the drawings and the description represent the same or similar elements. The illustrations in this specification are in simplified form and are not drawn to precise scale. For clarity and convenience of description, directional terms (eg, top, bottom, upper, lower, and diagonal) are directed to the accompanying illustrations. The directional terms used in the following description are not intended to limit the scope of the present invention when they are not explicitly used in the scope of the patent application attached below.

再者，在說明本發明一些實施例中，說明書以特定步驟順序說明本發明之方法以及(或)程序。然而，由於方法以及程序並未必然根據所述之特定步驟順序實施，因此並未受限於所述之特定步驟順序。熟習此項技藝者可知其他順序也為可能之實施方式。因此，於說明書所述之特定步驟順序並未用來限定申請專利範圍。再者，本發明針對方法以及(或)程序之申請專利範圍 並未受限於其撰寫之執行步驟順序，且熟習此項技藝者可瞭解調整執行步驟順序並未跳脫本發明之精神以及範圍。 Furthermore, in describing some embodiments of the present invention, the description describes the method and/or procedure of the present invention in a particular sequence of steps. However, since the methods and procedures are not necessarily implemented according to the specific order of steps described, they are not limited to the specific order of steps described. Those skilled in the art will appreciate that other sequences are possible implementations. Therefore, the specific sequence of steps described in the specification is not intended to limit the scope of the patent application. Furthermore, the present invention is directed to the scope of the patent application of the method and/or program It is not limited by the order of execution steps written, and those skilled in the art can understand that adjusting the sequence of execution steps does not deviate from the spirit and scope of the present invention.

圖1A顯示根據本發明一實施例所述的半導體封裝裝置的剖面圖。根據本發明一實施例所述的半導體封裝裝置100A，包括基板10、晶片12、電子元件14、導電元件16A、封膠層17以及天線元件19。基板10內部具有線路層(圖未顯示)，以及與線路層電性連接，分別位於基板10相對的上表面與下表面的複數接合墊11，基板10可以是通過壓合法(laminated)及增層法(Build-up)等方式形成的雙層或多層電路層的基板。此屬於現有技術，因此不再詳述具體的實施細節以精簡說明。根據本申請一實施例，基板10可用不同的材料製作，如矽、高分子和陶瓷材料製作。 FIG. 1A shows a cross-sectional view of a semiconductor package device according to an embodiment of the present invention. The semiconductor packaging device 100A according to an embodiment of the present invention includes a substrate 10 , a chip 12 , an electronic element 14 , a conductive element 16A, an encapsulant layer 17 and an antenna element 19 . The substrate 10 has a circuit layer (not shown) inside, and a plurality of bonding pads 11 which are electrically connected to the circuit layer and are respectively located on the upper surface and the lower surface of the substrate 10 opposite to the substrate 10. The substrate 10 can be laminated and build-up A double-layer or multi-layer circuit layer substrate formed by methods such as Build-up. This belongs to the prior art, so the specific implementation details will not be described in detail to simplify the description. According to an embodiment of the present application, the substrate 10 can be made of different materials, such as silicon, polymer and ceramic materials.

晶片12設置於基板10的上表面的接合墊11上，透過接合墊11與線路層電性連接。根據本發明一實施例，晶片12可以是各種包含有源元件或無源元件(active/passive elements)、數字電路或模擬電路(digital/analog circuits)等集成電路的電子元件(electronic components)，例如是有關於光電裝置(optoelectronic devices)、微機電系統(Micro-electromechanical Systems，MEMS)、功率放大晶片、電源管理晶片、生物辨識裝置、微流體系統(microfluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理傳感器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測裝置、發光二極管(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力傳感器(process sensors)或噴墨頭(ink printer heads)等半導體晶片。 The chip 12 is disposed on the bonding pads 11 on the upper surface of the substrate 10 , and is electrically connected to the circuit layer through the bonding pads 11 . According to an embodiment of the present invention, the wafer 12 may be various electronic components including integrated circuits such as active/passive elements, digital circuits or digital/analog circuits, such as It is about optoelectronic devices, micro-electromechanical systems (MEMS), power amplifier chips, power management chips, biometric devices, microfluidic systems, or the use of heat, light and pressure, etc. A physical sensor that measures changes in physical quantities. In particular, the wafer scale package (WSP) process can be optionally used for image sensing devices, light-emitting diodes (LEDs), solar cells (solar cells), radio frequency components (RF circuits), accelerometers Semiconductor wafers such as accelerators, gyroscopes, fingerprint readers, micro actuators, surface acoustic wave devices, process sensors or ink printer heads.

電子元件14設置於基板10的上表面的接合墊11上，透過接合墊11與線路層電性連接。根據本發明一實施例，電子元件14可包括濾波電路或被動元件，例如電阻、電容、電感等，以搭配晶片12實施濾波、穩壓、信號放大等 功能。根據本發明一實施例，晶片12與電子元件14可利用表面黏著技術(Surface Mount Technology，SMT)安裝在基板10上。 The electronic components 14 are disposed on the bonding pads 11 on the upper surface of the substrate 10 , and are electrically connected to the circuit layer through the bonding pads 11 . According to an embodiment of the present invention, the electronic components 14 may include filter circuits or passive components, such as resistors, capacitors, inductors, etc., so as to cooperate with the chip 12 to implement filtering, voltage regulation, signal amplification, etc. Function. According to an embodiment of the present invention, the chip 12 and the electronic components 14 can be mounted on the substrate 10 by using surface mount technology (SMT).

導電元件16A設置於基板10的上表面的接合墊11上，透過接合墊11與線路層電性連接。根據本發明一實施例，導電元件16A可以是金屬插塞(plug)或是導電柱，材質可以是例如金、銀、銅、鋁、鎢、錫、合金或其他合適的導電材料。 The conductive element 16A is disposed on the bonding pad 11 on the upper surface of the substrate 10 , and is electrically connected to the circuit layer through the bonding pad 11 . According to an embodiment of the present invention, the conductive element 16A may be a metal plug or a conductive column, and the material may be, for example, gold, silver, copper, aluminum, tungsten, tin, alloy or other suitable conductive materials.

封膠層17，順應性地形成於基板10上，用以包覆晶片12、電子元件14以及導電元件16A，並露出晶片12與導電元件16A的頂部。封膠層17可提供機械穩定性及抵抗氧化、濕度及其它環境條件的保護。根據本發明一實施例，封膠層17可由一封裝材料(molding material)形成。該封裝材料可包括酸醛基樹脂(novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其它適當的包覆劑。該封裝材料亦可包括適當的填充劑(filler)，例如是粉狀的二氧化矽。該封裝材料可以是預浸漬材料(pre-impregnated material)，例如是預浸漬介電材料。 The encapsulant layer 17 is conformably formed on the substrate 10 to cover the chip 12 , the electronic element 14 and the conductive element 16A, and expose the tops of the chip 12 and the conductive element 16A. The encapsulant layer 17 may provide mechanical stability and protection against oxidation, humidity and other environmental conditions. According to an embodiment of the present invention, the encapsulant layer 17 may be formed of a molding material. The encapsulation material may include novolac-based resin, epoxy-based resin, silicon-based resin or other suitable capping agents. The encapsulation material may also include a suitable filler, such as powdered silicon dioxide. The encapsulation material may be a pre-impregnated material, such as a pre-impregnated dielectric material.

散熱層18，設置於晶片12上，用以幫助晶片12散熱。根據本發明一實施例，散熱層18的材質可為鋁膠或銀膠，透過網版印刷(Screen printing)的方式直接貼附在晶片12露出封膠層17的表面。根據本發明其他實施例，散熱層18的材料還可包含陶瓷、石墨烯(graphene)、石墨(graphite)、奈米碳管(carbon nanotube，CNT)、奈米碳球(carbon nanoball)、或其組合。 The heat dissipation layer 18 is disposed on the chip 12 for helping the chip 12 to dissipate heat. According to an embodiment of the present invention, the material of the heat dissipation layer 18 may be aluminum glue or silver glue, which is directly attached to the surface of the chip 12 exposed to the sealing layer 17 by means of screen printing. According to other embodiments of the present invention, the material of the heat dissipation layer 18 may further include ceramic, graphene, graphite, carbon nanotube (CNT), carbon nanoball, or its combination.

天線元件19，設置於封膠層17，並與導電元件16A電性連接。根據本發明一實施例，天線元件19可包括輻射體，具有饋入端，輻射體設置於封膠層17上，而天線元件19的接地層可共用電子元件14的接地層。天線元件19部分設置於導電元件16A上，且天線元件19可透過網版印刷(Screen printing)的方式直接貼附在封膠層17上，材質可為鋁膠或銀膠。在此實施例，天線元件19與散熱層18的底面與封膠層17的表面共平面。另外，天線元件19可以是陣列天線(array antenna)或貼片天線(patch antenna)。由於陣列天線所需的佈局面積相 對貼片天線較大，本領域技術人員可根據功能需要以及產品尺寸而選擇使用陣列天線或貼片天線。 The antenna element 19 is disposed on the sealing layer 17 and is electrically connected to the conductive element 16A. According to an embodiment of the present invention, the antenna element 19 may include a radiator with a feeding end, the radiator is disposed on the sealing layer 17 , and the ground layer of the antenna element 19 may share the ground layer of the electronic element 14 . The antenna element 19 is partially disposed on the conductive element 16A, and the antenna element 19 can be directly attached to the sealing layer 17 by means of screen printing, and the material can be aluminum glue or silver glue. In this embodiment, the bottom surfaces of the antenna element 19 and the heat dissipation layer 18 are coplanar with the surface of the sealing layer 17 . In addition, the antenna element 19 may be an array antenna or a patch antenna. Since the layout area required by the array antenna is different The patch antenna is larger, and those skilled in the art can choose to use an array antenna or a patch antenna according to functional requirements and product size.

圖1B顯示根據本發明另一實施例所述的半導體封裝裝置的剖面圖。圖1B與圖1A的差異在於圖1A的導電元件16A改以導電元件16B代替。根據本發明一實施例，導電元件16B可由複數銅球疊合而成。透過複數銅球疊合的方式形成導電元件16B，可以簡化製程，降低成本。在其他實施例中，導電元件16B亦可由複數錫球疊合而成。 FIG. 1B shows a cross-sectional view of a semiconductor package device according to another embodiment of the present invention. The difference between FIG. 1B and FIG. 1A is that the conductive element 16A of FIG. 1A is replaced by a conductive element 16B. According to an embodiment of the present invention, the conductive element 16B can be formed by stacking a plurality of copper balls. The conductive element 16B is formed by stacking a plurality of copper balls, which can simplify the manufacturing process and reduce the cost. In other embodiments, the conductive element 16B can also be formed by stacking a plurality of solder balls.

圖2A-圖2D顯示根據本發明一實施例所述的半導體封裝裝置的製造方法的剖面圖。參閱圖2A，首先提供基板10。基板10具有線路層，以及與線路層電性連接，分別位於基板10相對的上表面與下表面的複數接合墊11，基板10可以是通過壓合法(laminated)及增層法(Build-up)等方式形成的雙層或多層電路層的基板。此屬現有技術，因此不再詳述具體的實施細節以精簡說明。根據本申請一實施例，基板10可用不同的材料製作，如矽、高分子和陶瓷材料製作。 2A-2D are cross-sectional views illustrating a method of manufacturing a semiconductor package device according to an embodiment of the present invention. Referring to FIG. 2A, the substrate 10 is first provided. The substrate 10 has a circuit layer, and a plurality of bonding pads 11 which are electrically connected to the circuit layer, respectively located on the upper surface and the lower surface of the substrate 10 opposite to the substrate 10 . The substrate 10 may be laminated or Build-up A substrate with a double-layer or multi-layer circuit layer formed by other methods. This belongs to the prior art, so the specific implementation details will not be described in detail to simplify the description. According to an embodiment of the present application, the substrate 10 can be made of different materials, such as silicon, polymer and ceramic materials.

接下來，設置晶片12以及電子元件14於基板10的上表面的接合墊11上，根據本發明一實施例，晶片12與電子元件14可利用表面黏著技術(Surface Mount Technology，SMT)安裝在基板10上。晶片12可以是各種包含有源元件或無源元件(active/passive elements)、數字電路或模擬電路(digital/analog circuits)等集成電路的電子元件(electronic components)，例如是有關於光電裝置(optoelectronic devices)、微機電系統(Micro-electromechanical Systems，MEMS)、功率放大晶片、電源管理晶片、生物辨識裝置、微流體系統(microfluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理傳感器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測裝置、發光二極管(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力傳感器(process sensors)或噴墨頭(ink printer heads)等半導體晶片。電子元件14透過接合墊11與線 路層電性連接。根據本發明一實施例，電子元件14可包括濾波電路或被動元件，例如電阻、電容、電感等，以搭配晶片12實施濾波、穩壓、信號放大等功能。 Next, the chip 12 and the electronic components 14 are placed on the bonding pads 11 on the upper surface of the substrate 10. According to an embodiment of the present invention, the chip 12 and the electronic components 14 can be mounted on the substrate by using surface mount technology (SMT). 10 on. The wafer 12 may be a variety of electronic components including integrated circuits such as active/passive elements, digital circuits or analog circuits (digital/analog circuits), such as those related to optoelectronic devices. devices), Micro-electromechanical Systems (MEMS), power amplifier chips, power management chips, biometric devices, microfluidic systems, or physical sensors that measure changes in physical quantities such as heat, light, and pressure (Physical Sensor). In particular, the wafer scale package (WSP) process can be optionally used for image sensing devices, light-emitting diodes (LEDs), solar cells (solar cells), radio frequency components (RF circuits), accelerometers Semiconductor wafers such as accelerators, gyroscopes, fingerprint readers, micro actuators, surface acoustic wave devices, process sensors or ink printer heads. Electronic components 14 through bonding pads 11 and wires circuit layer electrical connection. According to an embodiment of the present invention, the electronic components 14 may include filter circuits or passive components, such as resistors, capacitors, inductors, etc., so as to cooperate with the chip 12 to implement functions such as filtering, voltage regulation, and signal amplification.

接下來，形成導電元件16A於基板10的上表面的接合墊11上，並透過接合墊11與線路層電性連接。根據本發明一實施例，導電元件16A可以是金屬插塞(plug)或是導電柱，材質可以是例如金、銀、銅、鋁、鎢、錫、合金或其他合適的導電材料，根據本發明另一實施例，導電元件16A也可置換為圖1B所示的導電元件16B，由複數銅球疊合而成。 Next, the conductive elements 16A are formed on the bonding pads 11 on the upper surface of the substrate 10 , and are electrically connected to the circuit layer through the bonding pads 11 . According to an embodiment of the present invention, the conductive element 16A may be a metal plug or a conductive post, and the material may be, for example, gold, silver, copper, aluminum, tungsten, tin, alloy or other suitable conductive materials, according to the present invention In another embodiment, the conductive element 16A can also be replaced with the conductive element 16B shown in FIG. 1B , which is formed by stacking a plurality of copper balls.

接下來，參閱圖2B，順應性地形成封膠層17於基板10上，以包覆晶片12、電子元件14以及導電元件16A。封膠層17可提供機械穩定性及抵抗氧化、濕度及其它環境條件的保護。根據本發明一實施例，封膠層17可由一封裝材料(molding material)形成。該封裝材料可包括酸醛基樹脂(novolac-based resin)、環氧基樹脂(epoxy-based resin)、矽基樹脂(silicone-based resin)或其它適當的包覆劑。該封裝材料亦可包括適當的填充劑(filler)，例如是粉狀的二氧化矽。該封裝材料可以是預浸漬材料(pre-impregnated material)，例如是預浸漬介電材料。 Next, referring to FIG. 2B , the encapsulant layer 17 is conformally formed on the substrate 10 to cover the chip 12 , the electronic components 14 and the conductive components 16A. The encapsulant layer 17 may provide mechanical stability and protection against oxidation, humidity and other environmental conditions. According to an embodiment of the present invention, the encapsulant layer 17 may be formed of a molding material. The encapsulation material may include novolac-based resin, epoxy-based resin, silicon-based resin or other suitable capping agents. The encapsulation material may also include a suitable filler, such as powdered silicon dioxide. The encapsulation material may be a pre-impregnated material, such as a pre-impregnated dielectric material.

接下來，參閱圖2C，研磨封膠層17，使得晶片12的頂部露出，並磨去部份的導電元件16A頂部，使得留下的導電元件16A的頂部與晶片12的頂部以及研磨後的封膠層17上表面切齊。根據本發明一實施例，可透過機械式研磨的方式使用砂輪來研磨封膠層17。 Next, referring to FIG. 2C, the encapsulant layer 17 is ground to expose the top of the wafer 12, and part of the top of the conductive element 16A is ground away, so that the remaining top of the conductive element 16A and the top of the wafer 12 and the ground seal The upper surface of the adhesive layer 17 is cut evenly. According to an embodiment of the present invention, the sealing layer 17 may be ground by a grinding wheel by means of mechanical grinding.

接下來，參閱圖2D，形成散熱層18於晶片12上，並形成天線元件19於封膠層17，同時與導電元件16電性連接，完成了根據本發明一實施例所述的半導體封裝裝置。根據本發明一實施例，散熱層18的材料還可包含陶瓷、石墨烯(graphene)、石墨(graphite)、奈米碳管(carbon nanotube，CNT)、奈米碳球(carbon nanoball)、或其組合。天線元件19可包括輻射體，具有饋入端，輻射體設置於封膠層17上，而天線元件19的接地層可共用電子元件14的接地層。天線元件19可部分設置於導電元件16上，天線類型可以是陣列天線(array antenna)或貼片天線(patch antenna)。根據本發明另一實施例，散熱層18與天線元件19的 材質可為鋁膠或銀膠，並透過網版印刷(Screen printing)的方式同時分別貼附在晶片12與封膠層17的表面。 Next, referring to FIG. 2D , a heat dissipation layer 18 is formed on the chip 12 , and an antenna element 19 is formed on the sealing layer 17 , and is electrically connected to the conductive element 16 , thereby completing the semiconductor packaging device according to an embodiment of the present invention. . According to an embodiment of the present invention, the material of the heat dissipation layer 18 may further include ceramic, graphene, graphite, carbon nanotube (CNT), carbon nanoball, or its combination. The antenna element 19 may include a radiator with a feeding end, the radiator is disposed on the sealing layer 17 , and the ground layer of the antenna element 19 may share the ground layer of the electronic element 14 . The antenna element 19 may be partially disposed on the conductive element 16, and the antenna type may be an array antenna or a patch antenna. According to another embodiment of the present invention, the difference between the heat dissipation layer 18 and the antenna element 19 is The material can be aluminum glue or silver glue, and is attached to the surfaces of the wafer 12 and the sealing layer 17 by means of screen printing.

圖3A是根據本發明一實施例所述的陣列天線的俯視示意圖。如圖所示，饋入點30位於中央，輻射體32呈矩形。在圖示中，僅顯示四個輻射體32，然而在實際應用上，本領域技術人員可根據功能需要以及產品尺寸而選擇適當個數的輻射體32。根據圖3A所示的實施例，陣列天線的尺寸可小於12*12毫米。圖3B是根據本發明一實施例所述的陣列天線的返回損失(Return Loss)對頻率的模擬結果曲線圖。如圖3B所示，陣列天線可使用的頻寬介於27.54GHz-28.58GHz之間。 3A is a schematic top view of an array antenna according to an embodiment of the present invention. As shown, the feed point 30 is in the center and the radiator 32 is rectangular. In the figure, only four radiators 32 are shown, but in practical applications, those skilled in the art can select an appropriate number of radiators 32 according to functional requirements and product size. According to the embodiment shown in FIG. 3A , the size of the array antenna may be smaller than 12*12 mm. FIG. 3B is a graph showing a simulation result of return loss versus frequency of the array antenna according to an embodiment of the present invention. As shown in Fig. 3B, the usable bandwidth of the array antenna is between 27.54GHz-28.58GHz.

圖4A是根據本發明一實施例所述的貼片天線的俯視示意圖。如圖所示，饋入點40位於左下角，輻射體42呈矩形。根據圖4A所示的實施例，貼片天線的尺寸可小於6.5*6.5毫米，比陣列天線的尺寸更小。圖4B是根據本發明一實施例所述的貼片天線的返回損失(Return Loss)對頻率的模擬結果曲線圖。如圖4B所示，貼片天線可使用的頻寬介於27.6GHz-28.58GHz之間。 4A is a schematic top view of a patch antenna according to an embodiment of the present invention. As shown, the feed point 40 is located in the lower left corner, and the radiator 42 is rectangular. According to the embodiment shown in FIG. 4A , the size of the patch antenna can be smaller than 6.5*6.5 mm, which is smaller than that of the array antenna. FIG. 4B is a graph showing a simulation result of return loss versus frequency of the patch antenna according to an embodiment of the present invention. As shown in Fig. 4B, the usable bandwidth of the patch antenna is between 27.6GHz-28.58GHz.

根據本發明實施例，利用封膠層包覆晶片，並在封膠層上直接印刷天線結構，省去了天線基板的厚度，有效縮小封裝產品結合天線的厚度空間，滿足未來更小產品尺寸需求。另外，透過封膠層的設計，方便實踐直接印刷天線的目的，大幅降低產品成本。再者，透過散熱層的設計，進一步提高散熱的效率，有效改善產品的可靠度。 According to the embodiment of the present invention, the encapsulation layer is used to cover the chip, and the antenna structure is directly printed on the encapsulation layer, which saves the thickness of the antenna substrate, effectively reduces the thickness space of the encapsulated product combined with the antenna, and meets the size requirements of smaller products in the future. . In addition, through the design of the sealing layer, it is convenient to practice the purpose of directly printing the antenna, and the product cost is greatly reduced. Furthermore, through the design of the heat dissipation layer, the heat dissipation efficiency is further improved, and the reliability of the product is effectively improved.

綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上該者僅為本發明之較佳實施方式，本發明之範圍並不以上述實施方式為限，舉凡熟悉本案技藝之人士爰依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 To sum up, the present invention complies with the requirements of an invention patent, and a patent application can be filed in accordance with the law. However, the above are only the preferred embodiments of the present invention, and the scope of the present invention is not limited to the above-mentioned embodiments. Those who are familiar with the techniques of this case may make equivalent modifications or changes according to the spirit of the present invention. Covered in the following patent applications.

100B:半導體封裝裝置 100B: Semiconductor packaging device

10:基板 10: Substrate

11:接合墊 11: Bond pads

12:晶片 12: Wafer

14:電子元件 14: Electronic Components

16B:導電元件 16B: Conductive elements

17:封膠層 17: Sealing layer

18:散熱層 18: heat dissipation layer

19:天線元件 19: Antenna Elements

Claims (6)

一種半導體封裝裝置，包括：基板；晶片，設置於所述基板；導電元件，設置於所述基板；封膠層，包覆所述晶片與所述導電元件，並露出所述晶片與所述導電元件的頂部；天線元件，設置於所述封膠層，並與所述導電元件電性連接；及散熱層，設置於所述晶片上，其中所述散熱層透過網版印刷方式直接貼附於所述晶片露出所述封膠層的表面，同時所述天線元件透過網版印刷方式直接貼附於所述封膠層，所述天線元件與所述散熱層的底面與所述封膠層的表面共平面。。 A semiconductor packaging device, comprising: a substrate; a chip, disposed on the substrate; a conductive element, disposed on the substrate; a sealing layer, covering the chip and the conductive element, and exposing the chip and the conductive element The top of the element; the antenna element, which is arranged on the encapsulation layer and is electrically connected with the conductive element; and the heat dissipation layer, which is arranged on the chip, wherein the heat dissipation layer is directly attached to the chip through screen printing. The chip is exposed on the surface of the sealing layer, and the antenna element is directly attached to the sealing layer by screen printing. The bottom surface of the antenna element and the heat dissipation layer and the sealing layer are The surfaces are coplanar. . 如請求項1所述的半導體封裝裝置，其中所述基板具有線路層，以及與所述線路層電性連接的複數接合墊，所述晶片與所述導電元件透過所述接合墊與所述線路層電性連接。 The semiconductor packaging device of claim 1, wherein the substrate has a circuit layer and a plurality of bonding pads electrically connected to the circuit layer, the chip and the conductive element pass through the bonding pads and the circuit Layer electrical connection. 如請求項1所述的半導體封裝裝置，更包括設置於所述基板的電子元件，所述電子元件包括濾波電路或被動元件。 The semiconductor packaging device according to claim 1, further comprising an electronic component disposed on the substrate, the electronic component including a filter circuit or a passive component. 一種半導體封裝裝置製造方法，包括：提供基板；設置晶片於所述基板；設置導電元件於所述基板；形成封膠層，所述包覆所述晶片與所述導電元件；研磨封膠層，使得所述晶片的頂部與所述導電元件露出；及 設置天線元件於所述封膠層以及設置散熱層於所述晶片上，其中所述天線元件與所述導電元件電性連接，所述散熱層透過網版印刷方式直接貼附於所述晶片露出所述封膠層的表面，同時所述天線元件透過網版印刷方式直接貼附於所述封膠層，所述天線元件與所述散熱層的底面與所述封膠層的表面共平面。 A method for manufacturing a semiconductor packaging device, comprising: providing a substrate; arranging a chip on the substrate; arranging a conductive element on the substrate; forming an encapsulant layer, which covers the chip and the conductive element; and grinding the encapsulant layer, exposing the top of the wafer and the conductive elements; and Disposing an antenna element on the encapsulant layer and disposing a heat dissipation layer on the chip, wherein the antenna element is electrically connected to the conductive element, and the heat dissipation layer is directly attached to the chip through screen printing to expose The surface of the sealing layer, and the antenna element is directly attached to the sealing layer by screen printing, and the antenna element and the bottom surface of the heat dissipation layer are coplanar with the surface of the sealing layer. 如請求項4所述的半導體封裝裝置製造方法，其中所述基板具有線路層，以及與所述線路層電性連接的複數接合墊，所述晶片與所述導電元件透過所述接合墊與所述線路層電性連接。 The method for manufacturing a semiconductor package device according to claim 4, wherein the substrate has a circuit layer and a plurality of bonding pads electrically connected to the circuit layer, and the chip and the conductive element are connected to the circuit through the bonding pads. The circuit layer is electrically connected. 如請求項4所述的半導體封裝裝置製造方法，其中所述導電元件是由複數銅球疊合而成。 The method for manufacturing a semiconductor package device according to claim 4, wherein the conductive element is formed by stacking a plurality of copper balls.
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