CN103151274A - Semiconductor component and manufacturing method thereof - Google Patents
Semiconductor component and manufacturing method thereof Download PDFInfo
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- CN103151274A CN103151274A CN2013100399178A CN201310039917A CN103151274A CN 103151274 A CN103151274 A CN 103151274A CN 2013100399178 A CN2013100399178 A CN 2013100399178A CN 201310039917 A CN201310039917 A CN 201310039917A CN 103151274 A CN103151274 A CN 103151274A
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- metal
- layer
- semiconductor element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention discloses a semiconductor component comprising a substrate, a crystalline grain, a plurality of metal columns, a sealing compound material and a patterned metal layer. The substrate is provided with a plurality of first contacts and a plurality of second contacts, the crystalline grain is electrically connected to the plurality of first contacts, the plurality of metal columns are electrically connected to the plurality of second contacts, the crystalline grain and the plurality of metal columns are packaged by the sealing compound material, and the patterned metal layer is located on the sealing compound material and is electrically connected to the plurality of metal columns. Accordingly, the plurality of metal columns are used as inner connectors so as to achieve the micro distance, and the plurality of metal columns are formed by means of a process independent from the substrate and the crystalline grain in an implementation example of the manufacturing method of the semiconductor component.
Description
Technical field
The present invention is about a kind of semiconductor element with metal column.
Background technology
Packaging body laminated (Package on Package, POP) uses at mobile device, such as: mobile phone, Smartphone, panel computer etc.In the inner, processor must reach the purpose of small size with memory combination to reduce encapsulating structure whole height and space surface (Footprint).In better business model, upper encapsulating structure (memory) and lower encapsulating structure (processor) are transported to respectively assembles manufacturer to stack simultaneously and to assemble.Due to the chip size of two encapsulating structures, substrate section, and other structural parameters neither with, these encapsulating structures can synchronously not produce warpage when reflow.Therefore, when these encapsulating structures stacked, normally, relative soldered ball or connection pad (Lands) and soldered ball can not fuse together thereby cause opening circuit (Open Interconnects).
Therefore, lower encapsulating structure experience several iteration (Iterations) stacks yield to reduce warpage and improvement.A kind of design is based on valve gated mold design (Top Gate Mold Design) on, and it allows on every side the ball pad appears and can be approaching by the soldered ball of encapsulating structure this on.This design needs sizable soldered ball, and this soldered ball has enough height with stand highly (Stand-off) of the sealing die cap (Mold Cap) that overcomes this time encapsulating structure.The problem of this design is for controlling the merging (Coalescence) of height to guarantee relative soldered ball of this soldered ball.For the necessity that reaches between these encapsulating structures connects height (Necessary Interconnect Height), these soldered balls must have certain external diameter, and therefore, little spacing (Smaller Pitches) is impossibility.Therefore, be necessary to provide the improvement of structure ﹠processes, with distance between linking in more reducing, reduce stacking the height of encapsulating structure, and improve the technique yield.
Summary of the invention
The one side of this exposure is about a kind of manufacture method of semiconductor element.In one embodiment, the manufacture method of this semiconductor element comprises the following steps: adhere to crystal grain to one base plate for packaging, this base plate for packaging comprises several contacts, is positioned at a upper surface; Form several metal columns in a carrier; Adhere to these metal columns to these contacts: and this crystal grain of encapsulation and these metal columns, wherein a upper surface of each these metal column is revealed in outside this packaging body.
This exposure on the other hand about a kind of manufacture method of semiconductor element.In one embodiment, the manufacture method of this semiconductor element comprises the following steps: have on the carrier of a metal level in one, form several metal columns on this metal level; Have on the substrate of several first contacts and several the second contacts in one, be electrically connected a crystal grain to these the first contacts; Be electrically connected these metal columns to these the second contacts; Remove this carrier; And this metal level of patterning is to form a patterned metal layer.
This exposure on the other hand about a kind of semiconductor element.In one embodiment, this semiconductor element comprises a substrate, a crystal grain, several metal columns, an adhesive material and a patterned metal layer.This substrate has a upper surface and several contacts, and these contacts are positioned at this upper surface.This crystal grain is electrically connected to this substrate.These metal columns are positioned at the upper surface of this substrate and around this crystal grain, and are electrically connected to these contacts.This adhesive material is positioned at the upper surface of this substrate, and this adhesive material encapsulates this crystal grain and part encapsulates these metal columns, wherein the upper end of each these metal column be revealed in this adhesive material outside.This patterned metal layer is positioned at a upper surface of this adhesive material, and is electrically connected to these metal columns.
Description of drawings
Fig. 1 shows the cross-sectional schematic of an embodiment of semiconductor element of the present invention;
Fig. 2 is the vertical view of the semiconductor element of Fig. 1;
Fig. 3 is the details drawing in the zone that in Fig. 1, circle 3-3 indicates;
The step schematic diagram of one embodiment of the manufacture method of Fig. 4 to 14 demonstration semiconductor element of the present invention;
Figure 15 shows the cross-sectional schematic of another embodiment of semiconductor element of the present invention;
Figure 16 is the schematic top plan view of the semiconductor element of Figure 15;
Figure 17 shows the cross-sectional schematic of another embodiment of semiconductor element of the present invention;
Figure 18 shows the cross-sectional schematic of another embodiment of semiconductor element of the present invention;
The step schematic diagram of another embodiment of the manufacture method of Figure 19 to 20 demonstration semiconductor element of the present invention; And
Figure 21 shows the cross-sectional schematic of another embodiment of semiconductor element of the present invention.
Embodiment
With reference to figure 1, show the cross-sectional schematic of an embodiment of semiconductor element of the present invention.This semiconductor element 1 comprises a substrate 11, a crystal grain 12, several metal columns 13, an adhesive material 14, a patterned metal layer 15 and a welding resisting layer 16.
This substrate 11 can be, for example: an organic intermediate plate (Organic Interposer), in order to connect this crystal grain 12 and outer member, printed circuit board (PCB) (PCB) (not shown) for example.This substrate 11 has a upper surface 111, a lower surface 112, several first contacts (Contacts) 113, several second contacts 114 and several the 3rd contacts 115.These first contacts 113 and these the second contacts 114 are positioned at this upper surface 111, and these grade in an imperial examination three contacts 115 are positioned at this lower surface 112.With reference to figure 2, be the vertical view of Fig. 1, these second contacts 114 are around these the first contacts 113.In the present embodiment, these first contacts 113, these second contacts 114 and this grade in an imperial examination three contacts 115 are weld pad (Pads).Yet in other embodiments, these contacts 113,114,115 are whole or arbitrary can be the contact of copper metal column, conductive trace (Trace) or other any patterns.
This crystal grain 12 can be one to have the integrated circuit of logic and/or memory function.This crystal grain 12 is electrically connected to these the first contacts 113.In the present embodiment, this crystal grain 12 has several crystal grain contacts 121, and utilizes the chip bonding mode and be electrically connected to these the first contacts 113.That is these crystal grain contacts 121 directly or utilize scolder 122 and be engaged to these the first contacts 113.Perhaps, this crystal grain 12 also can utilize the routing mode and be electrically connected to these the first contacts 113.In the present embodiment, these crystal grain contacts 121 are weld pad.Yet in other embodiments, these crystal grain contacts 121 can be the contacts of copper metal column, conductive trace or other any patterns.
Please continue with reference to figure 1, these metal columns 13 are electrically connected to these the second contacts 114.In the present embodiment, the end of each these metal column 13 has a scolder 131, and these metal columns 13 are electrically connected to these the second contacts 114 via these scolders 131.These metal columns 13 can be, for example, and copper or other electric conducting materials.In the present embodiment, these metal columns 13 are positioned at the upper surface 111 of this substrate 11 and around this crystal grain 12.
This adhesive material 14 is positioned at the upper surface 111 of this substrate 11, and encapsulates this crystal grain 12 and these metal columns 13.In the present embodiment, these adhesive material 14 parts encapsulate these metal columns 13, and wherein the upper end of each these metal column 13 is revealed in outside this adhesive material 14.This patterned metal layer 15 is positioned on this adhesive material 14, and is electrically connected to these metal columns 13, with as a line layer.This patterned metal layer 15 has one first or upper surface 151 and one second or lower surface 152.These second surface 152 these adhesive materials 14 of contact.This patterned metal layer 15 can be a Copper Foil (Copper Foil), for example, directly is attached to this adhesive material 14 and is patterned afterwards.Perhaps, this patterned metal layer 15 can be a rerouting layer (Redistribution Layer), wherein one for example the dielectric layer of polymer at first be applied on this adhesive material 14, then a Copper Foil is applied on this dielectric layer and is patterned.
This welding resisting layer 16 is positioned on this patterned metal layer 15, and has several openings to appear several contact pads 161 on these patterned metal layer 15 upper surfaces 151 as shown in Fig. 1 and 2.These contact pads 161 can be bonded to a upper end of each metal column 13, or from this element 1 periphery towards the contact of this rerouting layer of the inner fan-in of this element 1 (Fan in), make these contact pads 161 of part cover (Overlie) these crystal grain 12.The advantage of this mode can replace an extra intermediate plate (Interposer) for the combination of these metal columns 13 and this patterned metal layer 15, thereby provides better elasticity when signal route (Signal Routing).With reference to figure 2, show several center contact pads 161.In another embodiment, these center contact pads 161 can be replaced by a continuum of this Copper Foil, with the fin as this element 1.
Fig. 3 is the details drawing in the zone that in Fig. 1, circle 3-3 indicates.In the present embodiment, this second surface 152 is a rough surface, to increase the cohesive force of 14 of this patterned metal layer 15 and this adhesive materials.Preferably, the outer surface of these metal columns 13 is also rough surface, to increase the cohesive force of 14 of these metal columns 13 and this adhesive materials.In addition, a side 153 of this patterned metal layer 15 is curved surface, and it is because etch process causes.
With reference to figure 4 to 14, the schematic diagram of an embodiment of the manufacture method of demonstration semiconductor element of the present invention.Fig. 4 shows a carrier 30 as one kind, and it has a metal level 31.This metal level 31 has a first surface 311 and a second surface 312.These first surface 311 these carrier 30 as one kind of contact.In the present embodiment, this metal level 31 can be Copper Foil, and this carrier 30 as one kind can be aluminium or the thicker Copper Foil with chromium/zinc layer.
With reference to figure 5, apply a photoresist layer 33 in the second surface 312 of this metal level 31.This photoresist layer 33 has several openings 331 to appear this metal level 31 of part.With reference to figure 6, form several metal columns 13 on the second surface 312 of this metal level 31 and be arranged in these openings 331 of this photoresist layer 33.Then, more form several scolders 131 in the end of these metal columns 13.These scolders 131 can utilize, such as electroplate, printing or ball fall techniques such as (Ball Dropping) and make.In the present embodiment, these metal columns 13 can be (for example: metal column copper) to have identical material with this metal level 31.Yet, in other embodiments, the material of these metal columns 13 can with these metal level 31 differences.
With reference to figure 7, remove this photoresist layer 33.For example, remove this photoresist layer 33 with etching or other technique.Moreover the second surface of this metal level 31 312 is simultaneously etched forming a rough surface, and preferably, the outer surface of these metal columns 13 is also etched to form rough surface, as shown in Figure 8.
Fig. 9 shows this substrate 11, these grade in an imperial examination three contacts 115 that it has this upper surface 111, this lower surface 112, is positioned at these first contacts 113 of this upper surface 111, is positioned at these second contacts 114 of this upper surface 111 and is positioned at this lower surface 112.This substrate 11 can be for example strip (Strip), array pattern (Matrix) or single (Row) pattern.This crystal grain 12 is electrically connected to these the first contacts 113 in the chip bonding mode via these crystal grain contacts 121.
With reference to Figure 10, this carrier 30 as one kind with this metal level 31 and these metal columns 13 of Fig. 7 is attached to this substrate 11 of Fig. 9, and wherein these metal columns 13 are electrically connected to these the second contacts 114.Adhering to this carrier 30 as one kind to this substrate 11 can be, for example reflow (Reflow).In the present embodiment, these metal columns 13 are electrically connected to these the second contacts 114 via these scolders 131.Yet in other embodiments, these metal columns 13 can directly be engaged to these second contacts 114.
With reference to Figure 11, remove this carrier 30 as one kind.This removes step and can comprise, for example etching.With reference to Figure 12, import an adhesive material 14 to a space of 111 of the upper surfaces of the second surface 312 of this metal level 31 and this substrate 11, to encapsulate this crystal grain 12 and these metal columns 13.With reference to Figure 13, apply a photoresist layer 32 in the first surface 311 of this metal level 31.This photoresist layer 32 has several openings 321 to appear this metal level 31 of part.
With reference to Figure 14, remove the metal level 31 in the zone of these openings 321 of being positioned at this photoresist layer 32, make this metal level 31 be patterned and form this patterned metal layer 15.For example, can utilize etching or other technique to remove this metal level 31.This patterned metal layer 15 is electrically connected to these metal columns 13, and has this first surface 151, this second surface 152 and this curved side 153, wherein these second surface 152 these adhesive materials 14 of contact.This patterned metal layer 15 can be as above-mentioned rerouting layer, line layer, or has the fin of large-area metal.This adhesive material 14 also can be etched, with formation one roughened upper surface in the zone of these openings 321 of this photoresist layer 32.
Then, remove this photoresist layer 32.Preferably, more form a surface-treated layer (Surface Finish Layer) (not shown) on this patterned metal layer 15.The material of this surface-treated layer can be, for example: nickel/gold or organic solderability preservative (Organic Solderability Preservative, OSP).Then, form this welding resisting layer 16 (Fig. 1) in the first surface 151 of this patterned metal layer 15 to make this semiconductor element 1, wherein this welding resisting layer 16 has several openings to appear this patterned metal layer 15 of part.
In the embodiment in figure 1, these metal columns 13 are as the interior connection (Interconnects) of 114 of this patterned metal layer 15 and these the second contacts.This mode can reach little spacing (Fine Pitch), because the copper metal column can be very thin.Moreover the warpage of this semiconductor element 1 can reduce via the dielectric layer that uses suitable adhesive material 14 and this substrate 11.In addition, these metal columns 13 utilize the technique that is independent of this substrate 11 and this crystal grain 12 to form.Therefore, if found the metal column defective before these metal columns 13 are bonded to this substrate 11, corresponding crystal grain 12 can be as virtual crystal grain (Dummy Die) to guarantee best yield.Perhaps, can abolish relatively cheap metal level 31 and metal column 13 and not need to abolish relatively costly crystal grain 12.
With reference to Figure 15, show the cross-sectional schematic of another embodiment of semiconductor element 1a of the present invention.This semiconductor element 1a and semiconductor element 1 shown in Figure 1 are roughly the same.Yet, in the embodiment of Fig. 1, be omitted in order to the rerouting layer of fan-in (Fans In) signal.On the contrary, one fin 17 is formed on the some of a upper surface of this semiconductor element 1a, make between this fin 17 and this element 1a outer rim spacing is arranged, and be positioned at its center, and connect and to be positioned at inner metal column 13, to form the hot path (Thermal Path) of 17 of this substrate 11, these metal columns 13 and this fin.Yet, in the present embodiment, be not that all metal columns 13 all are connected to this fin 17.Be positioned at outside metal column 13 and do not connect this fin 17 and appear its end, can be in order to connect one second element (being described below) to this element 1a
Figure 16 is the schematic top plan view of this semiconductor element 1a.In the present embodiment, this fin 17 is positioned at and is connected to the metal column 13 of an inner ring, does not extend to this element 1a outer rim simultaneously, therefore, several outer ring metal columns 13 are not covered by this fin 17, can be connected to this element 1a's for one second element and keep.As shown in Figure 15 and 16, this upper surface does not have welding resisting layer.Yet welding resisting layer can be applied to this upper surface to define several openings, the end of corresponding these metal columns 13 of these openings and/or the peripheral limit (Peripheral Limit) of this fin 17.
With reference to Figure 17, show the cross-sectional schematic of another embodiment of semiconductor element of the present invention.This semiconductor element 3 of the present embodiment is roughly the same with semiconductor element 1 shown in Figure 1.Yet this semiconductor element 3 of Figure 17 more comprises encapsulating structure 2 on, is positioned at this patterned metal layer 15 and this welding resisting layer 16 tops.Should have several soldered balls 21 by upper encapsulating structure 2.These soldered balls 21 are arranged in the opening of this welding resisting layer 16 to contact this patterned metal layer 15, make that on this, encapsulating structure 2 is electrically connected to this patterned metal layer 15.
With reference to Figure 18, show the cross-sectional schematic of another embodiment of semiconductor element of the present invention.This semiconductor element 4 of the present embodiment is roughly the same with semiconductor element 1 shown in Figure 1.Yet, in this semiconductor element 4 of the present embodiment, the upper surface 123 of this crystal grain 12 and the upper surface 141 of this adhesive material 14 and upper surface 132 coplines of this metal column 13.Moreover this semiconductor element 4 is patterned metal layer 15 (Fig. 1) not.
Referring to figures 19 through 20, the schematic diagram of another embodiment of the manufacture method of demonstration semiconductor element of the present invention.The initial step of the present embodiment is identical with the step of Fig. 4-11.With reference to Figure 19, remove this metal level 31.With reference to Figure 20, form an adhesive material 14 in the upper surface 111 of this substrate 11, to encapsulate this crystal grain 12 and these metal columns 13.Then, remove this adhesive material 14 of part and these metal columns 13 of part, with this adhesive material 14 of thinning and these metal columns 13, and appear these metal column 13 these crystal grain 12.Therefore, this semiconductor element 4 shown in Figure 180 is namely completed.
With reference to Figure 21, show the cross-sectional schematic of another embodiment of semiconductor element of the present invention.This semiconductor element 5 of the present embodiment is roughly the same with semiconductor element 4 shown in Figure 180.Yet this semiconductor element 5 of the present embodiment more comprises encapsulating structure 2 on, is positioned at this adhesive material 14 tops.Should have several soldered balls 21 by upper encapsulating structure 2.These soldered balls 21 are positioned at the upper surface 132 of these metal columns 13, make that on this, encapsulating structure 2 is electrically connected to these metal columns 13.
Only above-described embodiment only is explanation principle of the present invention and effect thereof, but not in order to limit the present invention.Therefore, practise above-described embodiment being modified and changing in the personage of this technology and still do not take off spirit of the present invention.Interest field of the present invention should be as listed in claims.
Claims (18)
1. the manufacture method of a semiconductor element comprises the following steps:
Adhere to crystal grain to one substrate, this substrate comprises several contacts, is positioned at a upper surface;
Form several metal columns in a carrier;
Adhere to extremely described contact of described metal column: and
Encapsulate this crystal grain and described metal column, wherein a upper surface of each described metal column is revealed in outside this packaging body.
2. method as claimed in claim 1, wherein in adhering to described metal column to the described contact, the method more comprises and forms a metal level on this carrier.
3. method as claimed in claim 2, wherein in adhering to described metal column to the described contact, the method more comprises and removes this carrier.
4. method as claimed in claim 3, comprise that more this metal level of patterning is to form a patterned metal layer.
5. method as claimed in claim 3, wherein this metal level is electrically connected to one first group of metal column, and is not electrically connected to one second group of metal column.
6. method as claimed in claim 1, more comprise forming a scolder in the end of each described metal column, and wherein said metal column is electrically connected to described contact via described scolder.
7. method as claimed in claim 1, comprise that more in electric connection one, encapsulating structure is to this semiconductor element.
8. the manufacture method of a semiconductor element comprises the following steps:
Have on the carrier of a metal level in one, form several metal columns on this metal level;
Have on the substrate of several first contacts and several the second contacts in one, be electrically connected a crystal grain to described the first contact;
Be electrically connected described metal column to described the second contact;
Remove this carrier; And
This metal level of patterning is to form a patterned metal layer.
9. method as claimed in claim 8, more comprise importing an adhesive material to the space between this metal level and this substrate.
10. method as claimed in claim 8, more comprise forming a scolder in the end of each described metal column, and wherein said metal column is electrically connected to described the second contact via described scolder.
11. method as claimed in claim 8, wherein this patterned metal layer is a rerouting layer, a line layer, or a fin.
12. method as claimed in claim 8 comprises more forming a welding resisting layer on this patterned metal layer that wherein this welding resisting layer appears this patterned metal layer of part.
13. method as claimed in claim 8 comprises that more in electric connection one, encapsulating structure is to this patterned metal layer.
14. a semiconductor element comprises:
One substrate has a upper surface and several contacts, and described contact is positioned at this upper surface;
One crystal grain is electrically connected to this substrate;
Several metal columns are positioned at the upper surface of this substrate and around this crystal grain, and are electrically connected to described contact;
One adhesive material is positioned at the upper surface of this substrate, and this adhesive material encapsulates this crystal grain and part encapsulates described metal column, and wherein the upper end of each described metal column is revealed in outside this adhesive material: and
One patterned metal layer is positioned at a upper surface of this adhesive material, and is electrically connected to described metal column.
15. as the semiconductor element of claim 14, wherein the end of each described metal column has a scolder, and described metal column is electrically connected to described contact via described scolder.
16. as the semiconductor element of claim 14, wherein this patterned metal layer is a rerouting layer, a line layer, or a fin.
17. as the semiconductor element of claim 14, wherein this patterned metal layer has a surface, it contacts this adhesive material, and this surface is a rough surface.
18. as the semiconductor element of claim 14, more comprise a welding resisting layer, be positioned on this patterned metal layer, and this welding resisting layer appears this patterned metal layer of part.
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| CN2013100399178A CN103151274A (en) | 2013-01-31 | 2013-01-31 | Semiconductor component and manufacturing method thereof |
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| CN2013100399178A CN103151274A (en) | 2013-01-31 | 2013-01-31 | Semiconductor component and manufacturing method thereof |
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Cited By (5)
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| CN104681499A (en) * | 2013-11-29 | 2015-06-03 | 矽品精密工业股份有限公司 | Package stack structure and method for fabricating the same |
| CN105140135A (en) * | 2014-05-30 | 2015-12-09 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
| CN106601626A (en) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | Process of producing three-dimensional system-level circuit board through packaging, etching, copper column electroplating and conduction |
| CN106941101A (en) * | 2016-01-05 | 2017-07-11 | 恒劲科技股份有限公司 | Package substrate and preparation method thereof |
| CN106981430A (en) * | 2016-12-21 | 2017-07-25 | 江苏长电科技股份有限公司 | A kind of affixed metal turns on the process of three-dimensional systematic wiring board |
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| CN202394881U (en) * | 2012-01-04 | 2012-08-22 | 日月光半导体制造股份有限公司 | Semiconductor package structure for stacking |
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| US20110147901A1 (en) * | 2009-12-17 | 2011-06-23 | Rui Huang | Integrated circuit packaging system with package stacking and method of manufacture thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104681499A (en) * | 2013-11-29 | 2015-06-03 | 矽品精密工业股份有限公司 | Package stack structure and method for fabricating the same |
| CN105140135A (en) * | 2014-05-30 | 2015-12-09 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
| CN106941101A (en) * | 2016-01-05 | 2017-07-11 | 恒劲科技股份有限公司 | Package substrate and preparation method thereof |
| CN106601626A (en) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | Process of producing three-dimensional system-level circuit board through packaging, etching, copper column electroplating and conduction |
| CN106981430A (en) * | 2016-12-21 | 2017-07-25 | 江苏长电科技股份有限公司 | A kind of affixed metal turns on the process of three-dimensional systematic wiring board |
| CN106981430B (en) * | 2016-12-21 | 2019-01-29 | 江苏长电科技股份有限公司 | A kind of process of affixed metal conducting three-dimensional systematic wiring board |
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Application publication date: 20130612 |