CN106941101A - Package substrate and preparation method thereof - Google Patents
Package substrate and preparation method thereof Download PDFInfo
- Publication number
- CN106941101A CN106941101A CN201610004607.6A CN201610004607A CN106941101A CN 106941101 A CN106941101 A CN 106941101A CN 201610004607 A CN201610004607 A CN 201610004607A CN 106941101 A CN106941101 A CN 106941101A
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- China
- Prior art keywords
- circuit chip
- connecting elements
- conductor layer
- package substrate
- conductive connecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Abstract
The invention discloses a kind of package substrate and preparation method thereof.The package substrate includes：One conductor layer, includes an at least metal routing；One conductive connecting elements, on the conductor layer；One circuit chip, with least one external foot pad, and is arranged on the conductive connecting elements；And a conductive film, coat the conductor layer, the conductive connecting elements and the circuit chip；Wherein, one of them one of them with an at least metal routing of the conductive connecting elements to connect at least one external foot pad.
Description
Technical field
The present invention on a kind of package substrate with and preparation method thereof, belong to technical field of semiconductors.
Background technology
Electronic product of new generation not only pursues compact high density, more there is the trend developed towards high power；
Therefore, IC (Integrated Circuit, abbreviation IC) technology and the wafer package technology of its rear end also with
Progress, to meet the efficiency specification of this electronic product of new generation.Buried in circuit chip embedment package substrate
Element Technology, because having the advantages that reduction package substrate product is disturbed by noise and product size reduces,
Turn into the Research Emphasis of this area manufacturer in recent years.Prior art is typically first by circuit chip or crystal grain
It is embedded in the casting die compound as package substrate main body, then to make leading as package substrate circuit layout
Line layer.
However, conductor layer is mostly the fine rule road of narrower width, processing procedure difficulty is high so that when conductor layer occurs
During defect in making, the circuit chip or crystal grain related must also be scrapped.Once in addition, circuit chip or
Crystal grain is embedded in package substrate, and the electric connection circuit of the circuit chip or crystal grain and external circuit will become
It must be difficult to handle, for example, procedure for processing and the labyrinth such as extra laser perforate, dielectric materials layer pressing
Electric connection circuit, these can all improve manufacturing cost and reduction product yield.Therefore, it is necessary to develop
New package substrate technology, the problem of with to controlling and improving above-mentioned.
The content of the invention
To reach this purpose, the present invention provides a kind of package substrate, and it is included：One conductor layer, comprising at least
One metal routing；One conductive connecting elements, on the conductor layer；One circuit chip, outside at least one
Pin pad, and be arranged on the conductive connecting elements；And a conductive film, coat the conductor layer,
The conductive connecting elements and the circuit chip；Wherein, the conductive connecting elements are at least one external to connect this
One of them of one of them of foot pad and an at least metal routing.
In one embodiment, the conductive connecting elements are a columnar metal thing.
In one embodiment, the conductive connecting elements are a solder bump thing.
In one embodiment, the package substrate further includes a fin, and it is arranged on the circuit chip, and
Connect the circuit chip.
In one embodiment, the package substrate further includes a metal loading plate, and it is arranged under the conductor layer.
On the other hand, the present invention provides a kind of preparation method of package substrate, and its step is included：One is provided to hold
Support plate；A conductor layer No.1 is formed on the loading plate so that the conductor layer No.1 includes at least one first gold medal
Belong to cabling；A conductive connecting elements are formed on the conductor layer No.1；Setting one has at least one external foot pad
Circuit chip on the conductive connecting elements so that the conductive connecting elements connect at least one external foot pad
One of them one of them with least one first metal routing；And one conductive film of formation exists
On the circuit chip, and make it that the conductive film fills the space between the circuit chip and the loading plate.
In one embodiment, the conductive connecting elements are one first columnar metal thing.
In one embodiment, the conductive connecting elements are a solder bump thing.
In one embodiment, this method is further included：The conductive film of part is removed, to expose the electricity
The upper surface of road chip；And remove the loading plate.
In one embodiment, this method is further included：One fin is set on the circuit chip so that this dissipates
Backing connects the upper surface of the circuit chip.
In one embodiment, this method is further included：One second conductor layer is formed on the conductive film,
So that second conductor layer includes at least one second metal routing；A conductive posts are formed in second conductor layer
On, the conductive posts include at least one second columnar metal thing；And a dielectric materials layer is formed in the mold
On compound layer, and make it that the dielectric materials layer coats all this at least one second on the conductive film
Metal routing and at least one second columnar metal thing.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section according to first embodiment of the invention package substrate.
Fig. 2~6 are the profile of each fabrication steps of first embodiment of the invention package substrate.
Fig. 7 A and 7B are the diagrammatic cross-section of the package substrate according to second embodiment of the invention.
Fig. 8~10 are the profile of each fabrication steps according to third embodiment of the invention package substrate.
Description of reference numerals：100th, 200,300-package substrate；110-loading plate；120-the first leads
Line layer；121~125-the first metal routing；130th, 131~134-conductive connecting elements；140-circuit is brilliant
Piece；141~144-external foot pad；150-conductive film；160-fin；170-the second wire
Layer；171~174-the second metal routing；180-conductive posts；181~184-columnar metal thing；190—
Dielectric materials layer.
Embodiment
It is further cognitive with understanding to make to have feature, purpose and the function of the present invention, hereby coordinate schema
Embodiments of the invention are described in detail as after.In all specifications and diagram, identical element will be used
Numbering is with specified same or similar element.
In the explanation of each embodiment, when an element be described be another element " top/on " or " under
Side/under ", refer to the situation either directly or indirectly on or below another element, it may include setting
Other elements therebetween；So-called " directly " refers to therebetween and is not provided with other intermediary elements." top/
On " or the description of " lower section/under " etc. illustrated on the basis of schema, but also include other possible directions
Transformation.So-called " first ", " second " and " the 3rd " to describe different elements, these yuan
Element is not restricted because of such meaning diction.For the facility on illustrating and clearly, each element in schema
Thickness or size, by exaggerate or omit or outline in the way of represent, and each element size be entirely its
Actual size.
Fig. 1 is the diagrammatic cross-section of the package substrate 100 according to first embodiment of the invention.The package substrate
100 include：One conductor layer No.1 120, a conductive connecting elements 130, a circuit chip 140 and a casting
Mold compound layer 150.The conductor layer No.1 120 represents the configuration of the package substrate 100, and it is comprising extremely
Few one first metal routing；The conductive connecting elements 130 are formed on the conductor layer No.1 120, its quantity
Can be more than one；The circuit chip 140 is arranged on the conductive connecting elements 130, and the circuit is brilliant
Piece 140 has at least one external foot pad；For convenience of description, example as shown in Figure 1, this
One conductor layer 120 have five the first metal routings (numbering is 121~125 from left to right), this be conductively connected list
The quantity of member 130 is external with four for four (numbering is 131~134 from left to right), the circuit chips 140
Foot pad (from left to right numbering be 141~144), but its quantity is not limited thereto, and end regards the package substrate 100
Depending on the need for configuration.Each conductive connecting elements 131~134 is to connect the external foot pad such as this
One of them of one of them of 141~144 and first metal routing of grade 121~125；For example, the conduction is even
Order member 131 connects the external foot pad 141 and first metal routing 121, and the conductive connecting elements 132 connect
The external foot pad 142 and first metal routing 122 are connect, the conductive connecting elements 133 connect the external foot pad
143 with first metal routing 123, the conductive connecting elements 134 connect the external foot pad 144 with this first
Metal routing 124.In addition, the conductive film 150 then coats the conductor layer No.1 120, the conduction even
Order member 130 and the circuit chip 140, it can be used as the envelope beyond the part of the upper surface of circuit chip 140
Fill the outermost protective layer of substrate 100.
The composition material of the conductor layer No.1 120 can be copper (Cu), nickel (Ni), tin (Sn) and ni au (Ni/Au)
Combination or alloy, its can plating (Electrolytic plating), sputter (Sputtering coating) or evaporation
(Evaporation) formed metal film after, by the patterning process of lithography (Photolithography) come
Make, be used as wherein one layer of the circuit layout line layer of the package substrate 100.In the present embodiment, should
Conductor layer No.1 120 has five the first metal routings 121~125, as shown in Figure 1.
The circuit chip 140 is an active member.In the present embodiment, the making of the circuit chip 140 can
To be to put on semiconductor crystal wafer (wafer) with IC (IC) processing procedure, and crystal grain (die) is cut into, and
Connect external foot pad (for example, conductive connecting pin (pin), conductive spacer (pad) or conductive projection (bump)) in advance,
And will be embedded to using embedded element technology in the package substrate 100.Thereby, package substrate can effectively be lowered
Noise suffered by product disturbs and reduced its finished size, and can be applied to the application processing of portable apparatus
Device (Application processor) and power management chip.As shown in figure 1, the circuit chip 140 has four
Individual external foot pad 141~144, can self contraposition when it is arranged on the conductive connecting elements 130
(Self-alignment) the external foot pad 141~144 such as this is connected into the grade conductive connecting elements respectively
131~134, and be not necessary to use fine alignment technique.
First led to allow the circuit chip 140 to be connected to this in the case of without using fine alignment technique
Line layer 120, the present embodiment makes the conduction for having column structure or projection cube structure on 120 layers of the conductor layer No.1
Connection unit 131~134, for example, copper post (Cu pillar) or solder bump (solder bump) so that the circuit
The external foot pad 141~144 of chip 140 simply self can be aligned to the grade conductive connecting elements 131~134,
Then it can will effectively reduce the cost of manufacture of package substrate.In the present embodiment, single conductive connecting elements 130
(or, the grade conductive connecting elements 131~134) to connect the external foot pad 141~144 such as this one of them with
One of them of first metal routing of grade 121~125.As shown in figure 1, the conductive connecting elements 131 connect
The external foot pad 141 and first metal routing 121 are connect, the conductive connecting elements 132 connect the external foot pad
142 with first metal routing 122, the conductive connecting elements 133 connect the external foot pad 143 with this first
Metal routing 123, the conductive connecting elements 134 connect the external foot pad 144 and first metal routing 124,
So that the circuit chip 140 can be connected to the conductor layer No.1 according to the circuit design of the package substrate 100
120。
The conductive film 150 can be made by the molded technology of packing colloid, for example, compression mold
Method (Compression Molding), and the composition material of packing colloid can be phenolic group resin
(Novolac-Based Resin), epoxy (Epoxy-Based Resin) or silicone
Insulating materials such as (Silicone-Based Resin), but be not limited.The conductive film 150 can be coated
The circuit chip 140, and fill the space between the circuit chip 140 and the conductor layer No.1 120 so that
The electronic component or product of the package substrate 100 formation tool robust structure.In addition, the conductive film 150
The part beyond the upper surface of circuit chip 140 can act also as the outside protective layer of the package substrate 100,
To protect the package substrate 100 to be protected from the possibility from external environment condition or successive process (for example, welding)
Injury.
In the present embodiment, the package substrate 100 can be used as the crystal covering type applied to mold interconnection substrates technology
The substrate of chip-size package (FCCSP).In addition, the single conductor of the configuration of the present embodiment package substrate is also
Can be the stacking structure of multi-layer conductor leads layer, for example, the conductor layer of two layers, three layers or more layers.
Illustrate the processing procedure of the package substrate 100 of the embodiment of the present invention below.It refer to Fig. 2~6 and Fig. 1, its point
Not Dui Ying above-described embodiment package substrate 100 each fabrication steps package substrate profile.
First, as shown in Figure 2 there is provided a loading plate 110, it can be the substrate of a conductive material, for example,
Metal substrate or surface are coated with the dielectric material substrate of one layer of conductive layer, to carry or support the encapsulation base
The successive process of plate 100, for example, making the conducting wire of the package substrate 100.Above-mentioned metal substrate
Comprising iron (Fe), copper (Cu), nickel (Ni), tin (Sn), aluminium (Al), ni au (Ni/Au) and combinations thereof or alloy,
But the present invention is not limited.
Then, as shown in Fig. 2 forming a conductor layer No.1 120 on the loading plate 110 so that this
One conductor layer 120 includes at least one first metal routing.For example, the photoresist of photosensitive type can be used in we,
A photoresistance film is first formed on the loading plate 110, then is patterned by micro image etching procedure, is formed
The resistance coating of metal plating, re-plating metal film thereon, and forms the pattern of metal routing in the loading plate
On 110.Either, the dielectric material of non-photo-sensing type can be used in we, first forms one on the loading plate 110
Dielectric film, then the dielectric film is patterned by laser transfer technique, then be deposited with or jet-plating metallization
Film thereon, finally removes the dielectric film with stripping method (Lift-off), while the pattern of metal routing is stayed in
On the loading plate 110.In the present embodiment, the conductor layer 120 has five the first metal routings 121~125,
And it constitutes combination or the alloy that material can be copper, nickel, tin and ni au.
Then, an at least conductive connecting elements 130 are formed on the conductor layer No.1 120.Such as Fig. 4 A institutes
Show, an at least conductive connecting elements 130 include the conductive connecting elements 131~134 of four projection cube structures, example
Such as, solder bump (Solder bump), in successive process by the circuit chip 140 be connected to this first
Conductor layer 120.But the quantity of an at least conductive connecting elements 130 is not limited thereto, end regards the encapsulation base
The need for the configuration of plate 100 or depending on the external foot pad quantity of the circuit chip 140.In another embodiment
In, grade conductive connecting elements 131 '~134 ' also can be column structure, as shown in Figure 4 B, for example, copper post,
Aluminium post, nickel post, tin post or alloy column, preferably be copper post.For avoid it is excessive repeat, after this specification
Half portion illustrates the implementation of correlation with the grade conductive connecting elements 131~134 for projection cube structure (as shown in Figure 4 A)
Example, but reader can appreciate that, those embodiments are also equally applicable to grade conductive connecting elements 131 '~134 ' and are
The case of column structure (as shown in Figure 4 B).
Then, a circuit chip 140 with least one external foot pad is set at least one to be conductively connected list in this
(in the present embodiment, the circuit chip 140 has four external foots pad 141~144, such as Fig. 5 in member 130
It is shown, but the present invention is not limited thereto system) so that each external connection of foot pad 141~144 this outside at least one
One of them of one of them of pin pad 141~144 and at least one first metal routing 121~125.Should
Circuit chip 140 is to cut into crystal grain (die) form with the active member made by IC (IC) processing procedure
Chip, and connected external foot pad (for example, conductive connecting pin, conductive spacer or conductive projection) in advance, can answer
It is embedded to embedded element technology in the package substrate 100.When the circuit chip 140 is installed on the conduction even
When in order member 130, the external foot pad 141~144 such as this can be placed on this etc. easily and be conductively connected list
Member 131~134, for example, self contraposition (self-alignment), and be not necessary to use fine alignment technique.At this
In embodiment, the conductive connecting elements 131 connect the external foot pad 141 and first metal routing 121, should
Conductive connecting elements 132 connect the external foot pad 142 and first metal routing 122, the conductive connecting elements
133 connect the external foot pad 143 and first metal routing 123, and it is outer that the conductive connecting elements 134 connect this
Pin pad 144 and first metal routing 124 so that the circuit chip 140 can be according to the package substrate 100
Circuit design and be connected to the conductor layer No.1 120.
Then, as shown in fig. 6, forming a conductive film 150 on the circuit chip 140, and make
Obtain the space between the conductive film 150 filling circuit chip 140 and the loading plate 110.The casting
Mold compound layer 150 can be made by the molded technology of packing colloid, for example, compression mold method, and seal
The composition material of dress colloid can be that phenolic aldehyde (Novolac) base resin, epoxy or silicone etc. are exhausted
Edge material, but be not limited.The conductive film 150 can coat the circuit chip 140, and filling should
Space between circuit chip 140 and the conductor layer No.1 120 so that the package substrate 100 formation tool is steady
The electronic component or product of fixing structure.In addition, the conductive film 150 exceed the circuit chip 140
The part of upper surface can act also as the outside protective layer of the package substrate 100, to protect the package substrate 100
It is protected from the possibility injury from external environment condition or successive process (for example, welding).So far, the package substrate
100 basic circuit has been completed, and first can be removed the loading plate 110, as shown in Figure 1.
Circuit chip be embedded to package substrate embedded element technology because with reduction package substrate product by
The advantage that noise is disturbed and product size reduces, turns into the Research Emphasis of this area manufacturer in recent years.With
Exemplified by Fig. 1 package substrate, prior art is typically that circuit chip 140 first is embedded into package substrate 100
In main body (conductive film 150), then to make the conductor layer No.1 120 as package substrate circuit layout,
And the conductor layer No.1 120 is mostly the fine rule road of narrower width, processing procedure difficulty is high so that when this first is led
The defect made occurs for line layer 120, then the circuit chip 140 related must also be scrapped.In addition, once
The circuit chip 140 is embedded in the package substrate 100, the electric connection of the circuit chip 140 and external circuit
Circuit will become to be difficult to handle, for example, the procedure for processing such as extra laser perforate, dielectric materials layer pressing
And the electric connection circuit of labyrinth, these can all improve manufacturing cost and reduction product yield.
The technology of the present invention is reviewed, is performed as described above described in the fabrication steps of example, is embedded to by circuit chip 140
Before the package substrate 100, the conductor layer No.1 120 as package substrate circuit layout is just first completed, then will
The circuit chip 140 is bonded to the conductor layer No.1 120, finally again by conductive film 150 with mold side
Formula is injected, and completes package substrate 100 as shown in Figure 1.Therefore, narrower width, processing procedure difficulty are higher
Fine rule road (conductor layer No.1 120) can be first produced, and the conductor layer No.1 120 can also include circuit chip
140 with the electric connection circuit of external circuit and complete or be not necessary to additional processing simultaneously；Therefore, it is possible to decrease
Manufacturing cost and raising product yield.
According to above-described embodiment, Fig. 6 package substrate can be further developed into the production with higher order function
Product.For example, Fig. 7 A are the diagrammatic cross-section of the package substrate 200 according to second embodiment of the invention.Upper
State after the step of first embodiment processing procedure proceeds to Fig. 6, the conductive film 150 can be removed from top to bottom
To the upper surface for exposing the circuit chip 140；For example, removing the conductive film using lapping mode
150 first half, and using the upper surface of the circuit chip 140 as grinding halt.Therefore, because the circuit
The upper surface of chip 140 is exposed state, and this is beneficial to the radiating effect of the circuit chip 140.
In another embodiment, a fin (Heat sink) 160 can be further disposed upon on the circuit chip 140, made
Obtain the fin 160 and connect the circuit chip 140, to strengthen the radiating effect to the circuit chip 140, such as
Shown in Fig. 7 B.For example, using bonding method, the fin 160 is directly adhered into the circuit chip 140
Upper surface.
Further, since the loading plate 110 that above-described embodiment is used is conductive substrate, no matter its
It is the metal substrate of monoblock or the dielectric substrate of conductive layer is only coated with surface, the loading plate 110 can be also made
It is used for the radiating that provides the circuit chip 140, and the processing procedure that it is remained in after Fig. 6.For example, figure
8~10 be to be illustrated according to the section of the package substrate 300 of third embodiment of the invention correspondence successive process steps
Figure.When above-mentioned first embodiment proceeds to Fig. 6 step, if being intended to regard the loading plate 110 as radiating
Piece, then the conductor layer No.1 120 can be used as heat produced by the circuit chip 140 to the loading plate 110
The heat dissipation path of transmission.In the present embodiment, we can separately make envelope on the conductive film 150
Fill the circuit layout line layer of substrate；Therefore, as shown in figure 8, one second conductor layer 170 can be formed at this
On conductive film 150 so that second conductor layer 170 includes at least one second metal routing；For example,
Second conductor layer 170 has four the second metal routings 171~174, and its production method and composition material can join
According to the conductor layer No.1 120 of such as Fig. 2 steps, but it is not limited.
Then, as shown in figure 9, a conductive posts 180 can be formed on second conductor layer 170, this is led
Electric post layer 180 includes an at least columnar metal thing；For example, the conductive posts 180 have four columnar metals
Thing 181~184, it is respectively to that should wait the second metal routing 171~174.
Then, as shown in Figure 10, a dielectric materials layer 190 is formed on the conductive film 150, and
So that the dielectric materials layer 190 coats second metal routing of grade 171~174 on the conductive film 150
With the grade columnar metal thing 181~184.The production method and composition material of the dielectric materials layer 190 can refer to as
The conductive film 150 of Fig. 6 steps, but be not limited
In addition, we can be made based on Fig. 1 package substrate 100 in response to different demand or purposes
Further application.For example, it is outer to connect that tin ball (Solder ball) is made in the lower section of the package substrate 100
Portion's circuit；The package substrate 100 top superposition surface adhering technical (Surface-Mount Technology,
Abbreviation SMT) element or other circuit chip or crystal grain；Above or below the package substrate 100
Superposition others package substrate, forms the package substrate of sandwich construction.
The above embodiment is only exemplary, does not constitute any limitation to the scope of the present invention.Ability
Field technique personnel should be understood that without departing from the spirit and scope of the invention can be to the technology of the present invention
The details and form of scheme are modified or replaced, but these modifications and replacement each fall within the protection model of the present invention
In enclosing.
Claims (11)
1. a kind of package substrate, it is characterised in that include：
One conductor layer, includes an at least metal routing；
One conductive connecting elements, on the conductor layer；
One circuit chip, with least one external foot pad, and is arranged on the conductive connecting elements；With
And
One conductive film, coats the conductor layer, the conductive connecting elements and the circuit chip；
Wherein, the conductive connecting elements to connect at least one external foot pad one of them with this extremely
One of them of a few metal routing.
2. package substrate as claimed in claim 1, it is characterised in that the conductive connecting elements are a gold medal
Belong to column.
3. package substrate as claimed in claim 1, it is characterised in that the conductive connecting elements are a weldering
Tin projection thing.
4. package substrate as claimed in claim 1, it is characterised in that further include a fin, it sets
It is placed on the circuit chip, and connects the circuit chip.
5. package substrate as claimed in claim 1, it is characterised in that further include a metal loading plate,
It is arranged under the conductor layer.
6. a kind of preparation method of package substrate, it is characterised in that step is included：
(A) loading plate is provided；
(B) conductor layer No.1 is formed on the loading plate so that the conductor layer No.1 includes at least one
First metal routing；
(C) conductive connecting elements are formed on the conductor layer No.1；
(D) set a circuit chip with least one external foot pad on the conductive connecting elements, make
Obtain the conductive connecting elements connect at least one external foot pad one of them with this at least one
One of them of first metal routing；And
(E) conductive film is formed on the circuit chip, and make it that the conductive film fills
The space filled out between the circuit chip and the loading plate.
7. preparation method as claimed in claim 6, it is characterised in that the conductive connecting elements are one the
One columnar metal thing.
8. preparation method as claimed in claim 6, it is characterised in that the conductive connecting elements are a weldering
Tin projection thing.
9. preparation method as claimed in claim 6, it is characterised in that further include：
(F1) conductive film of part is removed, to expose the upper surface of the circuit chip；And
(F2) loading plate is removed.
10. preparation method as claimed in claim 9, it is characterised in that further include：
One fin is set on the circuit chip so that the fin connects the upper table of the circuit chip
Face.
11. preparation method as claimed in claim 6, it is characterised in that further include：
(H1) one second conductor layer is formed on the conductive film so that second conductor layer is included
At least one second metal routing；
(H2) conductive posts are formed on second conductor layer, the conductive posts include at least one second
Columnar metal thing；And
(H3) dielectric materials layer is formed on the conductive film, and causes the dielectric materials layer bag
Cover at least one second metal routings all on the conductive film with this at least 1 the
Two columnar metal things.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610004607.6A CN106941101A (en) | 2016-01-05 | 2016-01-05 | Package substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610004607.6A CN106941101A (en) | 2016-01-05 | 2016-01-05 | Package substrate and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106941101A true CN106941101A (en) | 2017-07-11 |
Family
ID=59469360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610004607.6A Pending CN106941101A (en) | 2016-01-05 | 2016-01-05 | Package substrate and preparation method thereof |
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| CN109427714A (en) * | 2017-08-24 | 2019-03-05 | 日月光半导体制造股份有限公司 | Semiconductor packages and its manufacturing method |
| CN110035625A (en) * | 2019-03-07 | 2019-07-19 | 武汉迈斯卡德微电子科技有限公司 | A kind of production method that signal measures medium soft board |
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| CN109427714B (en) * | 2017-08-24 | 2023-09-08 | 日月光半导体制造股份有限公司 | Semiconductor package and method of manufacturing the same |
| CN110035625A (en) * | 2019-03-07 | 2019-07-19 | 武汉迈斯卡德微电子科技有限公司 | A kind of production method that signal measures medium soft board |
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