CN105140135A - Method for manufacturing semiconductor package - Google Patents
Method for manufacturing semiconductor package Download PDFInfo
- Publication number
- CN105140135A CN105140135A CN201410260874.0A CN201410260874A CN105140135A CN 105140135 A CN105140135 A CN 105140135A CN 201410260874 A CN201410260874 A CN 201410260874A CN 105140135 A CN105140135 A CN 105140135A
- Authority
- CN
- China
- Prior art keywords
- bearing part
- making
- semiconductor package
- adhesive layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title description 4
- 239000010410 layer Substances 0.000 claims abstract description 44
- 239000012790 adhesive layer Substances 0.000 claims description 40
- 238000010276 construction Methods 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 13
- 238000012545 processing Methods 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 238000003825 pressing Methods 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000004891 communication Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000003292 glue Substances 0.000 abstract 2
- 239000000565 sealant Substances 0.000 abstract 2
- 238000007789 sealing Methods 0.000 abstract 2
- 239000012945 sealing adhesive Substances 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A method for preparing semiconductor package, it provides a first bearing member equipped with semiconductor component first, and the first bearing member has interval layer jointed with the semiconductor component, and then form a sealant layer with relative first surface and second surface on the interval layer, make the sealant layer wrap the semiconductor component, and make the first surface jointed with the interval layer; then, forming a plurality of openings on the second surface of the sealing adhesive layer so as to enable the openings to be communicated with the first surface and the second surface; then, forming a second bearing piece on the second surface of the sealing glue layer; finally, the first bearing piece and the spacing layer are removed to expose the semiconductor element, the first surface of the sealing glue layer and the opening, so that the spacing layer is only damaged and the structure of the second bearing piece is not damaged when the opening is manufactured.
Description
Technical field
The present invention relates to a kind of encapsulation procedure, particularly about a kind of method for making of semiconductor package part, laser damage conductive layer and residue problem can be improved.
Background technology
Along with the evolution of semiconductor packaging, different encapsulation kenels developed by semiconductor device (Semiconductordevice), and be promote electrical functionality and save encapsulated space, then different three-dimensional encapsulation technology is developed, such as, the encapsulation of fan-out formula stacks (FanOutPackageonpackage, be called for short FOPoP) etc., with coordinate various wafer significantly increases input/go out of the port quantity, and then the integrated circuit of difference in functionality is integrated in single encapsulating structure, this kind of packaged type can play system in package (SiP) heterogeneous integration characteristic, can by the electronic component of different function, such as: memory body, central processing unit, painting processor, image application processor etc., by stacking the integration designing the system that reaches, be applicable to being applied to the various electronic product of light and thin type.
Figure 1A to Fig. 1 F is the generalized section that existing encapsulation stacks the method for making of the wherein semiconductor packaging part 1 of device.
As shown in Figure 1A, arrange semiconductor element 10 just like wafer in one first bearing part 11 from shape layer 110, then formed an adhesive layer 13 in this on shape layer 110 to cover this semiconductor element 10.
As shown in Figure 1B, second bearing part 12 with Copper Foil 120 is located on this adhesive layer 13.
As shown in Figure 1 C, remove this first bearing part 11 and from shape layer 110, to expose this semiconductor element 10 and adhesive layer 13.
As shown in figure ip, multiple opening 130 is formed on the adhesive layer 13 of this semiconductor element 10 periphery with laser mode.
As referring to figure 1e, insert electric conducting material in those openings 130, to form conductive pole 14, then on this adhesive layer 13, form multiple circuit redistribution layer (redistributionlayer, RDL) 15, be electrically connected this conductive pole 14 and semiconductor element 10 to make this circuit redistribution layer 15.
As shown in fig. 1f, remove this second bearing part 12, recycle this Copper Foil 120 and carry out patterned circuit processing procedure, to form line construction 16, carry out again afterwards cutting single processing procedure.
Only, in the method for making of existing semiconductor package part 1, form multiple opening 130 with laser mode, so not only easily damage this Copper Foil 120 and affect the yield of this line construction 16 of follow-up making, and in forming the residue (cull or the copper material etc. that peels off as this adhesive layer 13) produced in the process of this opening 130 and be very easily piled up in the bottom of this opening 130, so that it is inner to need first to clean this opening 130 in successive process, electric conducting material could be inserted in this opening 130.
In addition, the operation of cleaning this opening 130 not only increases cost of manufacture, and has very high depth-to-width ratio because of this opening 130, so be usually difficult to remove the residue in this opening 130 completely, causes residue can affect the yield of the electrical transmission of this conductive pole 14.
Therefore, how to overcome the variety of problems of above-mentioned prior art, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, object of the present invention, for providing a kind of method for making of semiconductor package part, in time making this opening, only can be damaged wall, and can not damage the structure of the second bearing part.
Semiconductor package part of the present invention comprises: provide the first bearing part that is provided with at least one semiconductor element, and this first bearing part has the wall engaging this semiconductor element; Form one and there is the adhesive layer of relative first surface and second surface on the wall of this first bearing part, make this adhesive layer this semiconductor element coated, and this first surface engages this wall; Form at least one being opened on the second surface of this adhesive layer, and this open communication this first and second is surperficial; Form the second bearing part on the second surface of this adhesive layer; And remove this first bearing part and this wall, to expose outside this semiconductor element, the first surface of this adhesive layer and opening.
In the method for making of aforesaid semiconductor package part, this adhesive layer is with mold pressing processing procedure or pressure programming former, and this opening is with laser mode former.
In the method for making of aforesaid semiconductor package part, this second bearing part covers this opening, and this second bearing part is incorporated on the second surface of this adhesive layer by conductive layer.Such as, first form this conductive layer on the second surface of this adhesive layer, then form this second bearing part on this conductive layer; Or, first form this conductive layer on this second bearing part, then this second bearing part be incorporated on the second surface of this adhesive layer with this conductive layer.Comprise again after removing this first bearing part and this wall, remove this second bearing part, recycle this conductive layer and form a line construction.
In addition, in aforesaid semiconductor package part and method for making thereof, also comprise after removing this first bearing part, form conduction material in this opening, and form line construction on the first surface of this adhesive layer, make this line construction be electrically connected this conduction material and this semiconductor element.Such as, this line construction comprises at least one circuit redistribution layer, and the material forming this conduction material at least comprises copper, aluminium, titanium or its at least the two combination.Comprise again after forming this line construction, remove this second bearing part.
As from the foregoing, in the method for making of semiconductor package part of the present invention, by first forming this opening, form this second bearing part again, remove this first bearing part and wall thereof afterwards, so in time making this opening, only can damage the wall of this first bearing part, and the structure of this second bearing part can not be damaged, and in time removing this first bearing part and wall thereof, in the process forming this opening, the residue that produces will drop out this opening voluntarily, thus not need the operation of carrying out cleaning this opening, to reach the object reducing cost of manufacture.
Accompanying drawing explanation
Figure 1A to Fig. 1 F is the generalized section of the method for making of existing semiconductor package part; And
Fig. 2 A to Fig. 2 H is the cross-sectional schematic of the method for making of semiconductor package part of the present invention; Wherein, Fig. 2 C ' is the another way of Fig. 2 C.
Symbol description
1,2 semiconductor package parts
10,20 semiconductor elements
11,21 first bearing parts
110 from shape layer
12,22 second bearing parts
120 Copper Foils
13,23 adhesive layers
130,230 openings
14,24 conductive poles
15,250 circuit redistribution layer
16,25,26 line constructions
210 walls
220 conductive layers
23a first surface
23b second surface
251 conducting elements.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art scholar can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only for coordinating specification to disclose, for understanding and the reading of those skilled in the art, be not intended to limit the enforceable qualifications of the present invention, so the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, quote in this specification as " on ", " first ", the term such as " second " and " ", be also only be convenient to describe understand, but not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, under changing technology contents without essence, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 G is the cross-sectional schematic of the method for making of semiconductor package part 2 of the present invention.
As shown in Figure 2 A, the first bearing part 21 that is provided with at least one semiconductor element 20 is provided, then forms adhesive layer 23 on this first bearing part 21, to make this adhesive layer 23 this semiconductor element 20 coated.
Then, with laser drill, machine drilling, etching or other etc. mode form those openings 230 and form multiple opening 230 on the second surface 23b of this adhesive layer 23, and respectively this opening 230 is positioned at this semiconductor element 20 neighboring area and is communicated with this first and second surperficial 23a, 23b.
In the present embodiment, the first bearing part 21 can select metallic plate, semiconductor crystal wafer or glass plate.
In addition, this first bearing part 21 has the wall 210 just like fractal film, adhesion material, insulation material etc., for this semiconductor element 20 of joint and this adhesive layer 23.
Again, this adhesive layer 23 has relative first surface 23a and second surface 23b, and this first surface 23a is engaged in this first bearing part 21.
In addition, this adhesive layer 23 with mold pressing (molding) resin processing procedure former or pressing film material (LaminateDryFilmType) former, but is not limited to this mode.
As shown in Fig. 2 B to Fig. 2 C, form one second bearing part 22 and cover those openings 230 on the second surface 23b of this adhesive layer 23.
In the present embodiment, this second bearing part 22 is incorporated on the second surface 23b of this adhesive layer 23 by conductive layer 220.Particularly, first pressing if this conductive layer 220 of Copper Foil is on the second surface 23b of this adhesive layer 23, then forms this second bearing part 22 on this conductive layer 220.
Or, as shown in Fig. 2 C ', also can this conductive layer 220 of first pressing on this second bearing part 22, then this second bearing part 22 to be incorporated on the second surface 23b of this adhesive layer 23 with this conductive layer 220.
As shown in Figure 2 D, remove this first bearing part 21 and this wall 210 thereof, to expose outside this semiconductor element 20, the first surface 23a of this adhesive layer 23 and opening 230.
As shown in Fig. 2 E to Fig. 2 F, formed if the conduction material of cupric, aluminium, titanium or its at least combination of the two is in this opening 230, to form multiple conductive pole 24, and form a line construction 25 on the first surface 23a of this adhesive layer 23, make this line construction 25 be electrically connected this conductive pole 24 and this semiconductor element 20.
In the present embodiment, this line construction 25 comprises at least one circuit redistribution layer (redistributionlayer, RDL) 250 and the multiple conducting elements 251 be located in outermost layer circuit redistribution layer 250, and this conducting element 251 comprises soldering tin material.
As shown in Figure 2 G, remove this second bearing part 22, and retain this conductive layer 220.
As illustrated in figure 2h, utilize this conductive layer 220 to carry out RDL processing procedure, to form another line construction 26, carry out again afterwards cutting single processing procedure.
In successive process, this semiconductor package part 2 can connect by those conducting elements 251 and put another semiconductor package part (figure slightly), stacks device to form encapsulation.
In sum, in the method for making of semiconductor package part 2 of the present invention, by first forming this opening 230, form this second bearing part 22 again, remove this first bearing part 21 and wall 210 thereof afterwards, so in time making this opening 230, this wall 210 only can be damaged, and this conductive layer 220 can not be damaged, thus can not affect the yield of this another line construction of follow-up making (figure is slightly).
In addition, although in forming the residue (cull or the wall 210 etc. that peels off as this adhesive layer 23) produced in the process of this opening 230 and be piled up in the bottom of this opening 230, but when removing this first bearing part 21 and wall 210 thereof, those residues will drop out this opening 230 voluntarily, thus the operation of carrying out cleaning this opening 230 is not needed, so compared to prior art, method for making of the present invention effectively can reduce cost of manufacture, and because not having residue in this opening 230, and make the electrical transmission yield of this conductive pole 24 better.
Above-described embodiment only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.
Claims (12)
1. a method for making for semiconductor package part, comprising:
There is provided the first bearing part that is provided with at least one semiconductor element, and this first bearing part has the wall engaging this semiconductor element;
Form one and there is the adhesive layer of relative first surface and second surface on the wall of this first bearing part, make this adhesive layer this semiconductor element coated, and make this first surface engage this wall;
Formed and be at least onely opened on the second surface of this adhesive layer, to make this open communication this first and second surface;
Form the second bearing part on the second surface of this adhesive layer; And
Remove this first bearing part and this wall, to expose outside this semiconductor element, the first surface of this adhesive layer and opening.
2. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this adhesive layer is with mold pressing processing procedure or pressure programming former.
3. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this opening is with laser mode former.
4. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this second bearing part covers this opening.
5. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, this second bearing part is incorporated on the second surface of this adhesive layer by conductive layer.
6. the method for making of semiconductor package part as claimed in claim 5, it is characterized in that, the processing procedure forming this second bearing part is first form this conductive layer on the second surface of this adhesive layer, then forms this second bearing part on this conductive layer.
7. the method for making of semiconductor package part as claimed in claim 5, is characterized in that, form the processing procedure of this second bearing part for first to form this conductive layer on this second bearing part, then be incorporated on the second surface of this adhesive layer with this conductive layer by this second bearing part.
8. the method for making of semiconductor package part as claimed in claim 5, is characterized in that, after this method for making also comprises and removes this first bearing part and this wall, removes this second bearing part, recycles this conductive layer and form a line construction.
9. the method for making of semiconductor package part as claimed in claim 1, it is characterized in that, after this method for making also comprises and removes this first bearing part, form conduction material in this opening, and form line construction on the first surface of this adhesive layer, make this line construction be electrically connected this conduction material and this semiconductor element.
10. the method for making of semiconductor package part as claimed in claim 9, is characterized in that, this method for making removes this second bearing part after also comprising this line construction of formation.
The method for making of 11. semiconductor package parts as claimed in claim 9, it is characterized in that, this line construction comprises at least one circuit redistribution layer.
The method for making of 12. semiconductor package parts as claimed in claim 9, is characterized in that, the material forming this conduction material at least comprises copper, aluminium, titanium or its at least the two combination.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103118944A TWI541912B (en) | 2014-05-30 | 2014-05-30 | Method of fabricating semiconductor package |
| TW103118944 | 2014-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105140135A true CN105140135A (en) | 2015-12-09 |
Family
ID=54725439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410260874.0A Pending CN105140135A (en) | 2014-05-30 | 2014-06-12 | Method for manufacturing semiconductor package |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105140135A (en) |
| TW (1) | TWI541912B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201044930A (en) * | 2009-06-12 | 2010-12-16 | Unimicron Technology Corp | Fabricating method of embedded package structure |
| US20110227220A1 (en) * | 2010-03-22 | 2011-09-22 | Chia-Ching Chen | Stackable semiconductor package and manufacturing method thereof |
| CN102201382A (en) * | 2010-03-26 | 2011-09-28 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
| CN102832181A (en) * | 2011-06-13 | 2012-12-19 | 矽品精密工业股份有限公司 | Chip Scale Package |
| CN103151274A (en) * | 2013-01-31 | 2013-06-12 | 日月光半导体制造股份有限公司 | Semiconductor component and manufacturing method thereof |
| CN103594418A (en) * | 2012-08-13 | 2014-02-19 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN103811360A (en) * | 2012-11-13 | 2014-05-21 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
-
2014
- 2014-05-30 TW TW103118944A patent/TWI541912B/en active
- 2014-06-12 CN CN201410260874.0A patent/CN105140135A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201044930A (en) * | 2009-06-12 | 2010-12-16 | Unimicron Technology Corp | Fabricating method of embedded package structure |
| US20110227220A1 (en) * | 2010-03-22 | 2011-09-22 | Chia-Ching Chen | Stackable semiconductor package and manufacturing method thereof |
| CN102201382A (en) * | 2010-03-26 | 2011-09-28 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece and manufacturing method thereof |
| CN102832181A (en) * | 2011-06-13 | 2012-12-19 | 矽品精密工业股份有限公司 | Chip Scale Package |
| CN103594418A (en) * | 2012-08-13 | 2014-02-19 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN103811360A (en) * | 2012-11-13 | 2014-05-21 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
| CN103151274A (en) * | 2013-01-31 | 2013-06-12 | 日月光半导体制造股份有限公司 | Semiconductor component and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201545245A (en) | 2015-12-01 |
| TWI541912B (en) | 2016-07-11 |
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Application publication date: 20151209 |