CN102201382A - Semiconductor packaging piece and manufacturing method thereof - Google Patents
Semiconductor packaging piece and manufacturing method thereof Download PDFInfo
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- CN102201382A CN102201382A CN2010101556596A CN201010155659A CN102201382A CN 102201382 A CN102201382 A CN 102201382A CN 2010101556596 A CN2010101556596 A CN 2010101556596A CN 201010155659 A CN201010155659 A CN 201010155659A CN 102201382 A CN102201382 A CN 102201382A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000004806 packaging method and process Methods 0.000 title abstract description 5
- 238000007789 sealing Methods 0.000 claims abstract description 92
- 239000010410 layer Substances 0.000 claims description 139
- 238000000034 method Methods 0.000 claims description 38
- 238000005516 engineering process Methods 0.000 claims description 22
- 239000012790 adhesive layer Substances 0.000 claims description 15
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 238000005520 cutting process Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 6
- 238000005304 joining Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000000565 sealant Substances 0.000 claims description 2
- 210000001503 joint Anatomy 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 abstract 9
- 238000003466 welding Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000005553 drilling Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a semiconductor packaging piece and a manufacturing method thereof. The semiconductor packaging piece is provided with a through hole and comprises a chip, a sealing compound, a dielectric layer, a first patterned conductive layer, a through-hole conductive layer, a second patterned conductive layer and a welding wire ball, wherein the chip is provided with an active surface, a chip back surface and a chip side face and comprises a connecting pad, wherein the connecting pad is formed on the active surface; the sealing compound is provided with a first sealing compound surface and a corresponding second sealing compound surface, wherein the first sealing compound surface is exposed out of the connecting pad, and the sealing compound coats the chip back surface and the chip side face; the dielectric layer is formed on the first sealing compound surface and is provided with an opening exposing the through hole; the through-hole conductive layer is formed in the through hole; the first patterned conductive layer is formed in the opening; the second patterned conductive layer is formed on the second sealing compound surface and extends to the through-hole conductive layer; and the welding wire ball is formed on the patterned conductive layer which is positioned on the second sealing compound surface.
Description
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and particularly relevant for a kind of semiconductor package part and manufacture method thereof with bonding wire ball (stud bump).
Background technology
Traditional stacking-type (stacked) semiconductor structure is formed by a plurality of chip stacks.Each chip has several soldered balls (solderball), and those tin balls are formed on the chip in reflow (reflow) mode.With other soldered ball, also adopt the mode of reflow to electrically connect the chip of mutual storehouse between chip and the chip.
Yet, chip before storehouse through a reflow process, mutually during storehouse again through a reflow process, that is each chip passes through the secondary reflow process at least.So, can increase the amount of warpage of chip, cause stack type semiconductor structure gross distortion because of the high temperature of reflow process.
Summary of the invention
The present invention is relevant for a kind of semiconductor package part and manufacture method thereof, and semiconductor package part provides at least one bonding wire ball.This bonding wire ball forms with routing technology (wire bonding), and this bonding wire ball is in order to dock with the semiconductor assembly.Because the joint technology of this semiconductor subassembly and this bonding wire ball can adopt the mode beyond the reflow to finish, and therefore can reduce semiconductor package part because of being subjected to the deflection that high temperature produces.
According to an aspect of the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a chip, a sealing, a perforation, one first dielectric layer, one first patterned conductive layer, a perforation conductive layer, one second patterned conductive layer and one first bonding wire ball.Chip has a chip sides and a relative active surface and a chip back and comprises one first connection pad, and first connection pad is formed on the active surface.Sealing has relative one first sealing surface and one second sealing surface.First connection pad is exposed on the first sealing surface, sealing and the coating chip back side and chip sides.Perforation is through to the second sealing surface from the first sealing surface.First dielectric layer is formed at first sealing surface and has one first perforate of exposing perforation.The perforation conductive layer is formed in the perforation.First patterned conductive layer is formed in first perforate and extends to the perforation conductive layer.Second patterned conductive layer is formed at second sealing surface and extends to the perforation conductive layer.The first bonding wire sphere is formed in second patterned conductive layer.
A kind of manufacture method of semiconductor package part is proposed according to a further aspect in the invention.Manufacture method may further comprise the steps.Support plate with an adhesive layer is provided; Several chips are set on adhesive layer, each chip has a chip sides and a relative active surface and a chip back and comprises one first connection pad, and first connection pad is formed on the active surface and towards adhesive layer; With the chip sides and the chip back of each chip of sealant covers, sealing has relative one first sealing surface and one second sealing surface; Form several perforations in sealing, perforation is through to the second sealing surface from the first sealing surface; Remove support plate and adhesive layer, make first connection pad of first sealing surface exposed chip; Form one first dielectric layer in the first sealing surface, first dielectric layer has several first perforates, and those perforations are exposed in those first perforates; Form a perforation conductive layer in those perforations; Form one first patterned conductive layer in first perforate and extend to the perforation conductive layer; Form one second patterned conductive layer in second sealing surface and extend to the perforation conductive layer; Form one first bonding wire ball in second patterned conductive layer with the routing technology; And the cutting sealing is to separate those chips.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Fig. 1 illustrates the schematic diagram according to the semiconductor package part of first embodiment of the invention.
Fig. 2 illustrates the cutaway view of the semiconductor package part of another embodiment of the present invention.
Fig. 3 illustrates the manufacturing flow chart according to the semiconductor package part of first embodiment of the invention.
Fig. 4 A to 4F illustrates the manufacturing schematic diagram of the semiconductor package part of Fig. 1.
Fig. 5 illustrates the schematic diagram according to the semiconductor subassembly of second embodiment of the invention.
The primary clustering symbol description:
100,200: semiconductor package part
102: chip
104: sealing
106: the first dielectric layers
110: the second dielectric layers
112: the tin ball
114: the first bonding wire balls
116: twist with the fingers disconnected portion
118,318: semiconductor subassembly
120: the second connection pads
122: the first connection pads
124: perforation
126: the first sealing surfaces
128: the second sealing surfaces
Perforate in 130: the first
132: chip protection layer
Perforate in 134: the second
136: the first patterned conductive layers
138: the second patterned conductive layers
140: adhesive layer
142: support plate
144: active surface
146,148,150: the side
152: the perforation conductive layer
154: the connection pad protective layer
156: chip back
158: chip sides
352: the second bonding wire balls
S102-S126: step
Embodiment
Preferred embodiment is below proposed as explanation of the present invention, however the content that embodiment proposed, usefulness only for illustrating, and graphicly illustrating for cooperating of drawing not is the usefulness as limit protection range of the present invention.Moreover the diagram of embodiment is also omitted unnecessary assembly, in order to clear demonstration technical characterstic of the present invention.
First embodiment
Please refer to Fig. 1, it illustrates the schematic diagram according to the semiconductor package part of first embodiment of the invention.Semiconductor package part 100 has perforation 124 and comprises chip 102, sealing 104, first dielectric layer 106, first patterned conductive layer 136, perforation conductive layer 152, second patterned conductive layer 138, second dielectric layer 110, several tin balls 112 and several first bonding wire balls 114.
Second patterned conductive layer 138 is formed on the second sealing surface 128, and the first bonding wire ball 114 can be formed on second patterned conductive layer 138.The position of the first bonding wire ball 114 can overlap with perforation 124, shown in the first bonding wire ball 114 on the left side among Fig. 1.Perhaps, the position of the first bonding wire ball 114 also can be along the bearing of trend on the second sealing surface 128 and perforation 124 distance that staggers, shown in the first bonding wire ball 114 on the right among Fig. 1.
The first bonding wire ball 114 forms with the routing technology, and therefore the first bonding wire ball 114 has a disconnected portion 116 of sth. made by twisting that is standing shape, and it is that bonding wire is twisted with the fingers the formed profile of having no progeny by the routing tool heads.
Please refer to Fig. 2, it illustrates the cutaway view of the semiconductor package part of another embodiment of the present invention.Semiconductor package part 200 more comprises semiconductor assembly 118, and semiconductor subassembly 118 herein can be chip or another semiconductor package part.Semiconductor subassembly 118 comprises several second connection pads 120.
In present embodiment, can adopt reflow joint technology in addition that second connection pad 120 of semiconductor subassembly 118 is bonded on the first bonding wire ball 114 to form stack type semiconductor packaging part 200.Above-mentioned combined process for example is that ultrasonic waves engages (ultrasonic bonding) technology.
The material of the first bonding wire ball 114 can be a metal, for example be gold (Au), aluminium (Al) with copper (Cu) at least one combination.So this is non-in order to restriction the present invention, and the material of the first bonding wire ball 114 also can be made up of other electric conducting material.When the material of the first bonding wire ball 114 is gold,, under the use of ultrasonic waves joining technique, help the associativity of second connection pad 120 of the first bonding wire ball 114 and semiconductor subassembly 118 because the quality of gold is softer.
Because semiconductor subassembly 118 is bonded on the first bonding wire ball 114 with the joint technology beyond the reflow, so can reduce the number of times that semiconductor package part 200 bears high-temperature technology, significantly reduces the deflection of semiconductor package part 200.
In addition, second connection pad 120 of semiconductor subassembly 118 can comprise a connection pad protective layer 154, and it is formed at the outermost layer of second connection pad 120 to be connected with the first bonding wire ball 114 with plating or sputter (sputtering) mode.Connection pad protective layer 154 is except avoiding 120 oxidations of second connection pad destroy the associativity that also can promote second connection pad 120 and the first bonding wire ball 114.Connection pad protective layer 154 can be made up of nickel (Ni) layer and gold (Au) layer.Perhaps, connection pad protective layer 154 can be made up of nickel dam, palladium (Pa) layer and gold layer, and wherein the gold layer of connection pad protective layer 154 can be formed at the outermost layer of second connection pad 120, to be connected with the first bonding wire ball 114.
Please get back to Fig. 1, chip 102 has chip sides 158 and relative active surface 144 with chip back 156 and comprise several first connection pads 122 and chip protection layer 132.First connection pad 122 and chip protection layer 132 are formed on the active surface 144 of chip 102.Wherein, chip sides 158 connects active surface 144 and chip back 156, and chip protection layer 132 exposes first connection pad 122, and the chip back 156 of sealing 104 coating chips 102 and chip sides 158 are also exposed first connection pad 122.
First dielectric layer 106 is formed at first sealing surface 126 and has several first perforates 130, and those perforations 124 and those first connection pads 122 are exposed in those first perforates 130 accordingly.
First patterned conductive layer 136 is formed on first dielectric layer 106 and reaches in those first perforates 130.Perforation conductive layer 152 is formed in the perforation 124.Perforation conductive layer 152 can be a skim, and it is formed at the madial wall of perforation 124; Perhaps, perforation conductive layer 152 also can be a conductive pole, and it fills up whole perforation 124.
Second patterned conductive layer 138 is formed at second sealing surface 128 and extends to perforation conductive layer 152, makes second patterned conductive layer 138 be electrically connected at first patterned conductive layer 136 by perforation conductive layer 152.
Those tin balls 112 are formed in those second perforates 134 accordingly to be electrically connected at the perforation conductive layer 152 and first connection pad 122.Tin ball 112 for example is circuit board (PCB), chip or another semiconductor package part in order to be electrically connected at an external circuit.
Below with Fig. 3 and Da figure 4A to 4F the manufacture method of the semiconductor package part 100 of Fig. 1 is described.Fig. 3 illustrates the manufacturing flow chart according to the semiconductor package part of first embodiment of the invention, and Fig. 4 A to 4F illustrates the manufacturing schematic diagram of the semiconductor package part of Fig. 1.
In step S102, provide the support plate with adhesive layer 140 142 shown in Fig. 4 A.
Then, in step S104, shown in Fig. 4 A, several chips 102 are set on adhesive layer 140.First connection pad 122 of each chip 102 is towards adhesive layer 140.For not making diagram too complicated, Fig. 4 A only shows single chip 102.
Those chips 102 can be in addition in make on the wafer that circuit is finished and cutting and separating after, redistribute in adhesive layer 140.
Come again, in step S106, shown in Fig. 4 B, use encapsulation technology coating sealing 104,, make sealing 104 and chip 102 form an adhesive body with the chip sides 158 and the chip back 156 of coating chip 102.Wherein, first sealing surface 126 flushes haply with active surface 144.
Sealing 104 can comprise phenolic group resin (Novolac-based resin), epoxy (epoxy-basedresin), silicone (silicone-based resin) or other suitable covering.Sealing 104 also can comprise suitable filler, for example is the silicon dioxide of powdery.
In addition, above-mentioned encapsulation technology for example is compression forming (compression molding), injection moulding (injection molding) or metaideophone moulding (transfer molding).
The integral body of those chips 102 of the encapsulation process of present embodiment after with rerouting is as encapsulated object, therefore, the adhesive body level encapsulation (Chip-redistribution Encapsulant LevelPackage) of the technology heavy cloth chip of present embodiment, can make semiconductor package part dependent of dead military hero chip size packages (the Chip Scale Package that produces, CSP) or wafer-level packaging (Wafer Level Package, WLP) grade.
In addition, can make between adjacent two chips 102 and can form the tin ball at a distance of a suitable distance between those chips 102 after the rerouting, i.e. tin ball 112 between the side 146 of chip sides 158 and sealing 104, as shown in Figure 1.So, the semiconductor package part after the cutting 100 can become fan-out type (fan-out) semiconductor package part.
Then, in step S108, shown in Fig. 4 C, use and swash or machine drilling technology formation perforation 124.Perforation 124 is through to the second sealing surface 128 from the first sealing surface 126.
Then, in step S110, shown in Fig. 4 D, remove support plate 142 and adhesive layer 140.After support plate 142 and adhesive layer 140 were removed, first connection pad 122 and chip protection layer 132 were exposed in the first sealing surface 126 of sealing 104.
After in step S110, can be inverted (invert) above-mentioned adhesive body, make the first sealing surface 126 up, shown in Fig. 4 E.
Then; in step S112; shown in Fig. 4 E; after using earlier coating (apply) technology and forming a dielectric material and cover the first sealing surface 126, chip protection layer 132 and first connection pad 122; use patterning techniques again and on this dielectric material, form first perforate 130 of exposing those perforations 124 and exposing those first connection pads 122, to form first dielectric layer 106.
Above-mentioned coating technique for example is printing (printing), spin coating (spinning) or spraying (spraying), and above-mentioned patterning techniques for example is lithography process (photolithography), chemical etching (chemical etching), laser drill (laser drilling), machine drilling (mechanical drilling) or laser cutting.
Then, in step S114, formation one electric conducting material is inserted in the perforation 124 and after covering first dielectric layer 106 (first dielectric layer 106 is illustrated in Fig. 4 E) and the second sealing surface 128 (the second sealing surface 128 is illustrated in Fig. 4 F), is used this electric conducting material of patterning techniques patterning again to form first patterned conductive layer 136 and second patterned conductive layer 138 shown in Fig. 4 F earlier.
The technology that forms above-mentioned this electric conducting material for example is that chemical gaseous phase Shen is long-pending, electroless plating method (electrolessplating), metallide (electrolytic plating), printing, spin coating, spraying, the long-pending method (vacuum deposition) of sputter (sputtering) or vacuum Shen.
The electric conducting material that is formed on first dielectric layer 106 is patterned into first patterned conductive layer 136, first patterned conductive layer 136 is formed to reach in those first perforates 130 (first perforate 130 is illustrated in Fig. 4 E) on first dielectric layer 106 and extend to perforation conductive layer 152 and contacts, and inserts the electric conducting material formation perforation conductive layer 152 of perforation 124.Being formed at electric conducting material on the second sealing surface 128 is patterned into second patterned conductive layer, 138, the second patterned conductive layers 138 and extends to perforation conductive layer 152 and contact.
In this step S114, first patterned conductive layer 136, perforation conductive layer 152 and second patterned conductive layer 138 form simultaneously.So this is non-in order to restriction the present invention, and in other enforcement aspect, first patterned conductive layer 136, perforation conductive layer 152 and second patterned conductive layer 138 also can be finished with identical or different material by the different process technology respectively.
Then, in step S116, use above-mentioned coating technique and arrange in pairs or groups second dielectric layer 110 of above-mentioned patterning techniques formation shown in Fig. 4 F on first patterned conductive layer 136.Second dielectric layer 110 has several second perforates 134, and perforation conductive layer 152 is exposed in some second perforates 134 accordingly, and the some of first patterned conductive layer 136 is exposed in other second perforates 134.The position of second perforate 134 is corresponding to the position of first connection pad 122 among Fig. 4 F, and so this is non-in order to restriction the present invention.In other enforcement aspect, second perforate 134 also can be along the bearing of trend of second dielectric layer 110 and first connection pad 122 distance that staggers.
Because said first dielectric layer 106, first patterned conductive layer 136, perforation conductive layer 152, second patterned conductive layer 138 and second dielectric layer 112 just form after chip 102 is redistributed, so first dielectric layer 106, first patterned conductive layer 136, perforation conductive layer 152, second patterned conductive layer 138 and second dielectric layer, 112 re-distribution layer (Redistributed layer, RDL).
Then, in step S118, form several tin balls 112 shown in Fig. 4 F in those second perforates 134, to be electrically connected at first patterned conductive layer 136.
After step S118, can be inverted the adhesive body of Fig. 4 F, make the second sealing surface 128 up.
Then, in step S120, form several first bonding wire balls 114 as shown in Figure 1 (second patterned conductive layer 138 is illustrated in Fig. 1) on second patterned conductive layer 138 with the routing technology.So far, form a package body structure.
In aspect an enforcement, decide by the operator scheme of wire bonding machine table, and the inversion action of omitting step S118.
Then, in step S122, cut above-mentioned package body structure, to separate those chips 102.So far, formation semiconductor package part 100 as shown in Figure 1.
As shown in Figure 1, because sealing 104, first dielectric layer 106 and second dielectric layer 110 of cutting path through overlapping, therefore, the side 148 of the side 146 of the sealing 104 in the semiconductor package part after the cutting 100, first dielectric layer 106 and the side 150 of second dielectric layer 110 trim haply.Wherein, the side 146 of sealing 104 connects the relative 126 and second sealing surface 128, first sealing surface.
Then, in step S124, provide semiconductor subassembly 118.
Then, in step S126,, dock the first bonding wire ball 114 and second connection pad 120, semiconductor subassembly 118 is stacked on the first bonding wire ball 114 with the technology that ultrasonic waves engages.So far, form the semiconductor package part 200 of stacking-type shown in Figure 2.
Second embodiment
Please refer to Fig. 5, it illustrates the schematic diagram according to the semiconductor subassembly of second embodiment of the invention.Continue to use same numeral with the first embodiment something in common among second embodiment, do not repeat them here.The semiconductor subassembly 318 of second embodiment is that with the difference of above-mentioned semiconductor subassembly 118 semiconductor subassembly 318 more comprises several second bonding wire balls 352.
The technical characterictic of the second bonding wire ball 352 is similar in appearance to the first bonding wire ball 114, in this no longer repeat specification.
Manufacture method similar in appearance to the semiconductor package part 200 of first embodiment, the technology that can utilize ultrasonic waves to engage, first bonding wire ball 114 of docking scheme 1 and the second bonding wire ball 352 of present embodiment semiconductor subassembly 318 are stacked on the first bonding wire ball 114 semiconductor subassembly 318 and form semiconductor package part similar in appearance to stacking-type shown in Figure 2.
In another enforcement aspect, semiconductor subassembly 318 also can be one to have similar in appearance to the semiconductor package part of the structure of semiconductor package part 100.Say that further two semiconductor package parts 100 can dock via the ultrasonic waves joining technique.
Disclosed semiconductor package part of the above embodiment of the present invention and manufacture method thereof, semiconductor package part have the bonding wire ball that forms with the routing technology, and this bonding wire ball can engage with the semiconductor assembly to form stack architecture.Because the joint technology of this semiconductor subassembly and this bonding wire ball can adopt the mode beyond the reflow, so can reduce semiconductor package part because of being subjected to the deflection that high temperature produces.
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (14)
1. semiconductor package part comprises:
One chip has a chip sides and a relative active surface and a chip back and comprises one first connection pad, and this first connection pad is formed on this active surface;
One sealing has one first sealing surface and corresponding one second sealing surface, and this first connection pad is exposed on this first sealing surface, and this sealing also coats this chip back and this chip sides;
One perforation is through to this second sealing surface from this first sealing surface;
One first dielectric layer is formed at this first sealing surface and has one first perforate of exposing this perforation;
One perforation conductive layer is formed in this perforation;
One first patterned conductive layer is formed in this first perforate and extends to this perforation conductive layer;
One second patterned conductive layer is formed at this second sealing surface and extends to this perforation conductive layer; And
One first bonding wire ball is formed at and is positioned at this second patterned conductive layer.
2. semiconductor package part as claimed in claim 1, wherein the material metal of this first bonding wire ball.
3. semiconductor package part as claimed in claim 1 more comprises:
The semiconductor assembly comprises one second connection pad, and this semiconductor subassembly is stacked on this first bonding wire ball and by this second connection pad and is electrically connected at this first bonding wire ball.
4. semiconductor package part as claimed in claim 1 more comprises:
The semiconductor assembly comprises one second bonding wire ball, and this semiconductor subassembly is stacked on this first bonding wire ball and by this second bonding wire ball and is electrically connected at this first bonding wire ball.
5. semiconductor package part as claimed in claim 1, wherein this chip more comprises a chip protection layer, and this chip protection layer is formed at this active surface and exposes this first connection pad, and this semiconductor package part more comprises:
One second dielectric layer is formed on this first patterned conductive layer and has one second perforate, and this perforation conductive layer is exposed in this second perforate; And
One tin ball is formed at this second perforate to be electrically connected at this perforation conductive layer.
6. semiconductor package part as claimed in claim 5, wherein the side of the side of a side of this sealing, this first dielectric layer and this second dielectric layer trims;
Wherein, this side of this sealing connects this first sealing surface and this second sealing surface.
7. the manufacture method of a semiconductor package part comprises:
Support plate with an adhesive layer is provided;
Several chips are set on this adhesive layer, each those chip has a chip sides and a relative active surface and a chip back and comprises one first connection pad, and this first connection pad is formed on this active surface and towards this adhesive layer;
With this chip sides and this chip back of each those chip of a sealant covers, this sealing has relative one first sealing surface and one second sealing surface;
Form several perforations in this sealing, those perforations are through to this second sealing surface from this first sealing surface;
Remove this support plate and this adhesive layer, make this first sealing surface expose those first connection pads of those chips;
Form one first dielectric layer in this first sealing surface, this first dielectric layer has several first perforates, and those perforations are exposed in those first perforates;
Form a perforation conductive layer in those perforations;
Form one first patterned conductive layer in those first perforates and extend to this perforation conductive layer;
Form one second patterned conductive layer in this second sealing surface and extend to this perforation conductive layer;
Form several first bonding wire balls in being positioned at this second patterned conductive layer with the routing technology; And
Cut this sealing, to separate those chips.
8. manufacture method as claimed in claim 7, wherein the material metal of each those first bonding wire ball.
9. manufacture method as claimed in claim 7 more comprises:
The semiconductor assembly is provided, and this semiconductor subassembly comprises several second connection pads; And
Dock those first bonding wire balls and those second connection pads, so that this semiconductor subassembly is stacked on those first bonding wire balls.
10. manufacture method as claimed in claim 9 wherein more comprises in this step of those first bonding wire balls of butt joint and those second connection pads:
With the ultrasonic waves joining technique, dock those first bonding wire balls and those second connection pads.
11. manufacture method as claimed in claim 7, wherein this semiconductor subassembly more comprises:
The semiconductor assembly is provided, and this semiconductor subassembly comprises several second bonding wire balls; And
Dock those first bonding wire balls and those second bonding wire balls, so that this semiconductor subassembly is stacked on those first bonding wire balls.
12. the manufacture method as claim 11 is stated wherein more comprises in this step of those first bonding wire balls of butt joint and those second bonding wire balls:
With the ultrasonic waves joining technique, dock those first bonding wire balls and those second bonding wire balls.
13. as the manufacture method that claim 7 is stated, wherein each those chip more comprises a chip protection layer, this chip protection layer is formed at this active surface and exposes this first connection pad, and this manufacture method more comprises:
Form one second dielectric layer in this first patterned conductive layer, this second dielectric layer has several second perforates, and this perforation conductive layer is exposed in those second perforates; And
Form several tin balls in those second perforates, to be electrically connected at this perforation conductive layer.
14. manufacture method as claimed in claim 7 wherein more comprises in this step of this sealing of cutting:
Cut this sealing along a cutting path, this cutting path this sealing, this first dielectric layer and this second dielectric layer through overlapping trims a side, the side of this first dielectric layer and the side of this second dielectric layer of this sealing after the cutting;
Wherein, this side of this sealing connects this first sealing surface and this second sealing surface.
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| CN2010101556596A CN102201382B (en) | 2010-03-26 | 2010-03-26 | Semiconductor packaging piece and manufacturing method thereof |
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| CN2010101556596A CN102201382B (en) | 2010-03-26 | 2010-03-26 | Semiconductor packaging piece and manufacturing method thereof |
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| CN104979219A (en) * | 2014-04-08 | 2015-10-14 | 矽品精密工业股份有限公司 | Method for manufacturing package structure |
| CN105140135A (en) * | 2014-05-30 | 2015-12-09 | 矽品精密工业股份有限公司 | Method for manufacturing semiconductor package |
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