CN112435965A - Memory card and packaging method thereof - Google Patents

Memory card and packaging method thereof Download PDF

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Publication number
CN112435965A
CN112435965A CN202011296647.5A CN202011296647A CN112435965A CN 112435965 A CN112435965 A CN 112435965A CN 202011296647 A CN202011296647 A CN 202011296647A CN 112435965 A CN112435965 A CN 112435965A
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China
Prior art keywords
layer
chip
control chip
electric connection
electrical connection
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Application number
CN202011296647.5A
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Chinese (zh)
Inventor
赖振楠
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Hosin Global Electronics Co Ltd
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Hosin Global Electronics Co Ltd
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Priority to CN202011296647.5A priority Critical patent/CN112435965A/en
Publication of CN112435965A publication Critical patent/CN112435965A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07724—Physical layout of the record carrier the record carrier being at least partially made by a molding process
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07732—Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The application discloses a memory card and a packaging method thereof, wherein the packaging method of the memory card comprises the following steps: providing a sacrificial layer; fixing a storage chip and a control chip on the surface of the sacrificial layer; forming a plastic packaging layer covering the storage chip and the control chip; removing the sacrificial layer; the bottom of the plastic packaging layer is provided with an electric connection layer, the electric connection layer and the plastic packaging layer jointly wrap the storage chip and the control chip, an electric connection structure is formed in the electric connection layer and is electrically connected with the storage chip and the control chip, the electric connection between the storage chip and the control chip is realized, and the control chip is electrically led out. The packaging method is low in cost.

Description

Memory card and packaging method thereof
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a memory card and a packaging method thereof.
Background
The existing memory card usually comprises a flash memory chip, a control chip and the like, in the packaging structure of the existing memory card, the internal chip is usually fixed on a substrate, the substrate is a PCB circuit board, and is electrically connected with the internal chip through a negative line, and then the whole substrate and the internal chip are wrapped by a plastic packaging layer to expose an external contact pin, so that the packaging is completed, and the whole memory card provides rigid support through the substrate.
The substrate adopted at present is generally a high-precision plate such as a BT resin plate, an FR-4 plate and the like, and the cost is higher.
Disclosure of Invention
In view of this, the present application provides a memory card and a packaging method thereof to solve the problem of high packaging cost of the memory card in the prior art.
The application provides a method for packaging a memory card, which comprises the following steps: providing a sacrificial layer; fixing a storage chip and a control chip on the surface of the sacrificial layer; forming a plastic packaging layer covering the storage chip and the control chip; removing the sacrificial layer; the bottom of the plastic packaging layer is provided with an electric connection layer, the electric connection layer and the plastic packaging layer jointly wrap the storage chip and the control chip, an electric connection structure is formed in the electric connection layer and is electrically connected with the storage chip and the control chip, the electric connection between the storage chip and the control chip is realized, and the control chip is electrically led out.
Optionally, the sacrificial layer is at least one of a photosensitive film layer or a heat-sensitive film layer.
Optionally, the sacrificial layer includes at least one of a blue tape, a UV tape, and a thermosetting material layer.
Optionally, the plastic package layer is formed by a 3D printing or injection molding process.
Optionally, the electrical connection layer includes an insulating layer and the electrical connection structure, and the electrical connection structure includes a wiring layer located in the insulating layer, and a contact pin connected to the wiring layer and exposed to a surface of the insulating layer.
Optionally, the forming method of the electrical connection layer includes: synchronously printing by adopting a 3D printing process to form the insulating layer and the electric connection structure; or, the forming method of the electrical connection layer comprises the following steps: after a plurality of sub insulating layers and sub wiring layers which are alternately stacked layer by layer are formed, a conductive column penetrating through each layer is formed, and electric connection is formed among the sub wiring layers through the conductive column.
Optionally, the method further includes: before the memory chip and the control chip are fixed on the surface of the sacrificial layer, concave regions which are matched with the memory chip and the control chip in size respectively are formed on the surface of the sacrificial layer.
The present application also provides a memory card, comprising: an electrical connection layer in which an electrical connection structure is formed; the memory chip and the control chip are positioned on the surface of the electric connection layer, the electric connection between the memory chip and the control chip is realized through the electric connection structure, and the electric leading-out of the control chip is realized; and the plastic packaging layer covers the electric connection layer, the storage chip and the control chip.
Optionally, the electrical connection layer includes an insulating layer and an electrical connection structure located in the insulating layer; the electric connection structure comprises a wiring layer positioned in the insulating layer and a contact pin which is connected with the wiring layer and exposed to the surface of the insulating layer.
Optionally, the insulating layer and the electrical connection structure in the electrical connection layer are 3D printed structures; or the electric connection layer comprises a plurality of insulating sub-layers and interconnection layers which are alternately stacked layer by layer, and electric conduction columns which form electric connection among the interconnection layers.
The memory card of this application adopts sacrificial layer temporary fixation memory chip and control chip in the packaging process, accomplishes the back at the plastic envelope, gets rid of the sacrificial layer utilizes the plastic envelope layer to provide the rigidity for the memory card and supports, need not to adopt costly base plate to support to can reduce the encapsulation cost of memory card. And after removing the sacrificial layer, form the electric connection layer, draw the electric property of memory chip and control chip out through the intraformational electric connection structure of electric connection, the electric connection layer only needs to play the effect of electric connection, and thickness is lower, can reduce the thickness of whole memory card.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 to 5 are schematic flow charts illustrating a packaging process of a memory card according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. The following embodiments and their technical features may be combined with each other without conflict.
Referring to fig. 1 to 5, a packaging process of a memory card according to an embodiment of the invention is schematically illustrated.
Referring to fig. 1, a sacrificial layer 100 is provided.
The sacrificial layer 100 is used for fixing a memory chip and a control chip of a memory card in subsequent steps, and plays a role in temporary fixation.
In some embodiments, the sacrificial layer 100 may be at least one of a photosensitive film layer or a heat-sensitive film layer, and the physical properties of the sacrificial layer may change under the action of light with a certain wavelength or temperature, and the sacrificial layer may be easily removed in a subsequent process step.
Meanwhile, the surface of the sacrificial layer 100 may have a certain viscosity, which is convenient for fixing a chip on the surface of the sacrificial layer 100 in a subsequent step. In some embodiments, the sacrificial layer 100 may be at least one of a blue tape (blue tape), a UV tape (UV tape), and a thermosetting material layer.
In this embodiment, in order to facilitate the subsequent positioning of the memory chip and the control chip, the first recess region 101 and the second recess region 102 may be formed on the surface of the sacrificial layer 100 by patterning in advance. The first recessed area 101 is located at a packaging position of the memory chip, and has a size matched with that of the memory chip, preferably, slightly larger than that of the fixing surface of the memory chip, and the second recessed area 102 corresponds to a packaging position of the control chip, and has a size matched with that of the control chip, preferably, slightly larger than that of the fixing surface of the control chip. The first recessed region 101 and the second recessed region 102 may be formed by patterned photolithography, imprinting, or the like. The depths of the first recessed area 101 and the second recessed area 102 do not need to be too large, and only need to be able to block the chip placed therein from sliding out. In other embodiments, it may not be necessary to form a recessed region on the surface of the sacrificial layer 100.
Referring to fig. 2, a memory chip 201 and a control chip 202 are fixed on the surface of the sacrificial layer 100.
The memory chip 201 generally adopts a FLASH memory chip, such as a NAND FLASH chip. The control chip 202 is used for executing a chip of a data operation instruction according to an external input signal, controlling a circuit in the memory chip 201, and executing control such as reading, writing, erasing, and the like.
The memory chip 201 and the control chip 202 are respectively fixed on the surface of the sacrificial layer 100.
In one embodiment, the surface of the sacrificial layer 100 has adhesiveness, and the memory chip 201 and the control chip 202 can be directly attached to the surface of the sacrificial layer 100 for fixing.
In another embodiment, the surface of the sacrificial layer 100 is a non-adhesive surface, and the memory chip 201 and the control chip 202 can be fixed to the surface of the sacrificial layer 100 by an additional adhesive layer.
In this embodiment, the memory chip 201 is fixed in the first recess region 101, and the control chip 202 is fixed in the second recess region 102, so that the sidewalls of the memory chip 201 and the control chip 202 are blocked by a sacrificial layer material with a partial height, thereby preventing the memory chip 201 and the control chip 202 from moving laterally, and better fixing the chip position.
In this embodiment, the memory card to be formed includes a memory chip 201 and a corresponding control chip 202. In other embodiments, the memory card to be formed may further include more than two memory chips or more than two control chips, which may be adjusted according to the design of the memory card, and is not limited herein.
In other embodiments, a plurality of memory card areas may be divided on the larger-sized sacrificial layer 100, a corresponding memory chip and a corresponding control chip are respectively fixed in each memory card area, and after the package is completed through a subsequent process, the memory cards are divided into individual memory cards. In this embodiment, only the package of a single memory card is taken as an example.
In some embodiments, the surfaces of the memory chip 201 and the control chip 202 on which the bonding pads are formed are fixed on the surface of the sacrificial layer 100, so as to electrically lead out the memory chip 201 and the control chip 202 subsequently.
Referring to fig. 3, a molding layer 300 is formed to cover the memory chip 201 and the control chip 202.
The plastic package layer 300 is generally made of epoxy plastic package material, and has thermosetting property. The sacrificial layer 100 with the memory chip 201 and the control chip 202 fixed thereto may be placed in a thermal injection mold by using a thermal injection molding process, and after injecting a molten thermoplastic material, the molten thermoplastic material is cured to form the molding layer 300. The plastic package layer 300 is only located on one side surface of the sacrificial layer 100, and the sacrificial layer 100 and the plastic package layer 300 wrap the memory chip 201 and the control chip 202.
In some embodiments, the sacrificial layer 100 is a heat-sensitive material, and the use of a thermoplastic process may cause deformation of the sacrificial layer 100, and during the injection molding process, the memory chip 201 and the control chip 202 cannot be sufficiently fixed. In order to avoid the above problem, the plastic package layer 300 may be formed by a 3D printing process, and the plastic package layer 300 may be formed on the surface of the sacrificial layer 100 by using a 3D printing process and a molten plastic package material.
The control chip 202 and the memory chip 201 are further fixed and protected by forming the molding layer 300.
Referring to fig. 4, the sacrificial layer 100 is removed (see fig. 3).
The sacrificial layer 100 is a thermosensitive or photosensitive film layer, and the material of the sacrificial layer 100 is modified by adopting illumination with specific temperature or specific wavelength and then stripped.
In one embodiment, the sacrificial layer 100 is a UV tape, and the adhesion of the sacrificial layer 100 is reduced by ultraviolet irradiation, and the sacrificial layer is directly torn off from the surfaces of the molding layer 300, the memory chip 201, and the control chip 202. During the process of removing the sacrificial layer 100, and after the sacrificial layer 100 is removed, the memory chip 201 and the control chip 202 are fixed by the molding layer 300 and provide mechanical support.
In other embodiments, the sacrificial layer 100 is a heat-sensitive material, and the sacrificial layer 100 can be modified by heat treatment and then removed.
After the sacrificial layer 100 is removed, one side surfaces of the memory chip 201 and the control chip 202 are exposed.
Referring to fig. 5, an electrical connection layer 400 is formed at the bottom of the molding compound layer 300, the electrical connection layer 400 and the molding compound layer 300 together wrap the memory chip 201 and the control chip 202, and an electrical connection structure 401 is formed in the electrical connection layer 400.
The electrical connection structure 402 is electrically connected to the memory chip 201 and the control chip 202, so as to electrically connect the memory chip 201 and the control chip 202 and electrically lead out the control chip 202 and the memory chip 201. In other embodiments, the electrical connection structure 402 may be implemented to electrically connect only the control chip 202.
The electrical connection layer 400 includes an insulating layer 401 and the electrical connection structure 402, and the electrical connection structure 402 includes a wiring layer 4011 located in the insulating layer 401, and a contact pin 4012 connected to the wiring layer 4011 and exposed on the surface of the insulating layer 401. External circuits can perform data operations on the memory card through the contact pins 4012.
The wiring layer 4011 includes at least one layer of interconnect lines distributed in a horizontal direction, and a vertical conductive structure, such as a conductive pillar, for connecting the interconnect lines in each layer in a vertical direction.
The insulating layer 401 of the electrical connection layer 400 may be made of an insulating hard material such as epoxy resin. The insulating layer 401 and the electrical connection structure 402 may be formed by printing simultaneously through a 3D printing process, and the insulating layer 401 and the electrical connection structure 402 may be formed by printing using at least two print heads.
In an embodiment of the invention, the method for forming the electrical connection layer 400 may further include: and after a plurality of sub insulating layers and sub wiring layers are sequentially and alternately formed layer by layer, forming a conductive column penetrating through each layer, forming electric connection among the sub wiring layers through the conductive column, and forming a contact pin on the surface of the conductive column.
The electrical connection layer 400 not only protects the memory chip 201 and the control chip 202, but also electrically leads out the memory chip 201 and the control chip 202. In the drawings, the electrical connection layer 400 and the molding layer 300 are only schematic and do not represent the actual thickness relationship. The memory card is mainly supported by the molding layer 300, and the thickness of the molding layer 300 is generally larger than that of the electrical connection layer 400.
Because the electrical connection structure in the electrical connection layer 400 is directly connected to the pads of the memory chip 201 and the control chip 202, compared with the electrical connection formed by the traditional wire bonding process, the electrical signal transmission path is shortened, and the signal transmission efficiency is improved. Meanwhile, since the electrical connection layer 400 does not need to provide rigid support for the memory card, the requirement on the hardness of the material of the insulating layer 401 is not high, a material with lower cost, such as epoxy resin, can be selected, so that the packaging cost of the memory card is reduced, and the thickness of the electrical connection layer 400 can be designed to be smaller, so that the thickness of the memory card is further reduced.
The embodiment of the invention also provides a storage card packaging structure.
Fig. 5 is a schematic structural diagram of a memory card according to an embodiment of the invention.
In this embodiment, the memory card includes: an electrical connection layer 400, wherein an electrical connection structure 402 is formed in the electrical connection layer 400; the memory chip 201 and the control chip 202 are positioned on the surface of the electrical connection layer 400, and the memory chip 201 and the control chip 202 are electrically led out by the electrical connection structure 402; and a molding layer 300 covering the electrical connection layer 400, the memory chip 201 and the control chip 202.
The memory chip 201 generally adopts a FLASH memory chip, such as a NAND FLASH chip. The control chip 202 is used for executing a chip of a data operation instruction according to an external input signal, controlling a circuit in the memory chip 201, and executing control such as reading, writing, erasing, and the like.
In this embodiment, the memory card includes a memory chip 201 and a corresponding control chip 202. In other embodiments, the memory card may further include more than two memory chips or more than two control chips, which may be adjusted according to the design of the memory card, and is not limited herein.
The plastic package layer 300 is made of an epoxy plastic package material, and may be formed by a 3D printing process or a thermal injection molding process. The molding layer 300 provides protection and rigid support for the control chip 202 and the memory chip 201.
The electrical connection layer 400 includes an insulating layer 401 and the electrical connection structure 402, and the electrical connection structure 402 includes a wiring layer 4011 located in the insulating layer 401, and a contact pin 4012 connected to the wiring layer 4011 and exposed on the surface of the insulating layer 401. External circuits can perform data operations on the memory card through the contact pins 4012.
In one embodiment, the insulating layer 401 and the electrical connection structure 402 within the electrical connection layer 400 are 3D printed structures; alternatively, the electrical connection layer 400 includes several insulating sub-layers, interconnect layers, and conductive pillars forming electrical connections between the interconnect layers.
Because the electrical connection structure in the electrical connection layer 400 is directly connected with the pads of the memory chip 201 and the control chip 202, the electrical signal transmission path is shortened, and the signal transmission efficiency in the memory card is improved. Meanwhile, since the electrical connection layer 400 does not need to provide rigid support for the memory card, the requirement on the hardness of the material of the insulating layer 401 is not high, a material with lower cost, such as epoxy resin, can be selected, so that the packaging cost of the memory card is reduced, and the thickness of the electrical connection layer 400 can be designed to be smaller, so that the thickness of the memory card is further reduced.
That is, the above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent structures or equivalent flow transformations made by using the contents of the specification and the drawings, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are included in the scope of the present application.

Claims (10)

1. A method for packaging a memory card, comprising:
providing a sacrificial layer;
fixing a storage chip and a control chip on the surface of the sacrificial layer;
forming a plastic packaging layer covering the storage chip and the control chip;
removing the sacrificial layer;
the bottom of the plastic packaging layer is provided with an electric connection layer, the electric connection layer and the plastic packaging layer jointly wrap the storage chip and the control chip, an electric connection structure is formed in the electric connection layer and is electrically connected with the storage chip and the control chip, the electric connection between the storage chip and the control chip is realized, and the control chip is electrically led out.
2. The method of claim 1, wherein the sacrificial layer is at least one of a photosensitive film layer or a thermally sensitive film layer.
3. The method of claim 1, wherein the sacrificial layer comprises at least one of a blue tape, a UV tape, and a thermosetting material layer.
4. The method of claim 1, wherein the molding layer is formed by a 3D printing or injection molding process.
5. The packaging method according to claim 1, wherein the electrical connection layer comprises an insulating layer and the electrical connection structure comprises a wiring layer located in the insulating layer, and a contact pin connected to the wiring layer and exposed to a surface of the insulating layer.
6. The method of claim 5, wherein the forming of the electrical connection layer comprises: synchronously printing by adopting a 3D printing process to form the insulating layer and the electric connection structure; or, the forming method of the electrical connection layer comprises the following steps: after a plurality of sub insulating layers and sub wiring layers which are alternately stacked layer by layer are formed, a conductive column penetrating through each layer is formed, and electric connection is formed among the sub wiring layers through the conductive column.
7. The method of packaging of claim 1, further comprising: before the memory chip and the control chip are fixed on the surface of the sacrificial layer, concave regions which are matched with the memory chip and the control chip in size respectively are formed on the surface of the sacrificial layer.
8. A memory card, comprising:
an electrical connection layer in which an electrical connection structure is formed;
the memory chip and the control chip are positioned on the surface of the electric connection layer, the electric connection between the memory chip and the control chip is realized through the electric connection structure, and the electric leading-out of the control chip is realized;
and the plastic packaging layer covers the electric connection layer, the storage chip and the control chip.
9. The memory card of claim 8, wherein the electrical connection layer includes an insulating layer and an electrical connection structure within the insulating layer; the electric connection structure comprises a wiring layer positioned in the insulating layer and a contact pin which is connected with the wiring layer and exposed to the surface of the insulating layer.
10. The memory card of claim 8, wherein the insulating layer and the electrical connection structure within the electrical connection layer are 3D printed structures; or the electric connection layer comprises a plurality of insulating sub-layers and interconnection layers which are alternately stacked layer by layer, and electric conduction columns which form electric connection among the interconnection layers.
CN202011296647.5A 2020-11-18 2020-11-18 Memory card and packaging method thereof Pending CN112435965A (en)

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Application Number Priority Date Filing Date Title
CN202011296647.5A CN112435965A (en) 2020-11-18 2020-11-18 Memory card and packaging method thereof

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060183269A1 (en) * 2003-07-28 2006-08-17 Edward Fuergut Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
CN102468264A (en) * 2010-11-17 2012-05-23 三星电子株式会社 Bump structure and semiconductor package having the bump structure
CN103219297A (en) * 2012-01-20 2013-07-24 矽品精密工业股份有限公司 Carrier, semiconductor package and fabrication method thereof
CN103367180A (en) * 2012-03-27 2013-10-23 南茂科技股份有限公司 Semiconductor packaging structure and manufacturing method thereof
CN104681457A (en) * 2013-06-29 2015-06-03 英特尔Ip公司 Multiple level redistribution layer for multiple chip integration
CN105336632A (en) * 2014-08-05 2016-02-17 英飞凌科技股份有限公司 Batch process for connecting chips to carrier
CN108630624A (en) * 2017-03-24 2018-10-09 艾马克科技公司 Electronic device and its manufacturing method
CN110504174A (en) * 2019-07-25 2019-11-26 南通通富微电子有限公司 The forming method of encapsulating structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060183269A1 (en) * 2003-07-28 2006-08-17 Edward Fuergut Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
CN102468264A (en) * 2010-11-17 2012-05-23 三星电子株式会社 Bump structure and semiconductor package having the bump structure
CN103219297A (en) * 2012-01-20 2013-07-24 矽品精密工业股份有限公司 Carrier, semiconductor package and fabrication method thereof
CN103367180A (en) * 2012-03-27 2013-10-23 南茂科技股份有限公司 Semiconductor packaging structure and manufacturing method thereof
CN104681457A (en) * 2013-06-29 2015-06-03 英特尔Ip公司 Multiple level redistribution layer for multiple chip integration
CN105336632A (en) * 2014-08-05 2016-02-17 英飞凌科技股份有限公司 Batch process for connecting chips to carrier
CN108630624A (en) * 2017-03-24 2018-10-09 艾马克科技公司 Electronic device and its manufacturing method
CN110504174A (en) * 2019-07-25 2019-11-26 南通通富微电子有限公司 The forming method of encapsulating structure

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