JPH04177753A - Resin sealing type semiconductor device - Google Patents
Resin sealing type semiconductor deviceInfo
- Publication number
- JPH04177753A JPH04177753A JP2303932A JP30393290A JPH04177753A JP H04177753 A JPH04177753 A JP H04177753A JP 2303932 A JP2303932 A JP 2303932A JP 30393290 A JP30393290 A JP 30393290A JP H04177753 A JPH04177753 A JP H04177753A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- gate
- chip
- pattern
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 title claims abstract description 38
- 229920005989 resin Polymers 0.000 title claims abstract description 38
- 238000007789 sealing Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000011889 copper foil Substances 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 claims abstract 7
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 239000010931 gold Substances 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 17
- 238000001721 transfer moulding Methods 0.000 description 4
- 230000013011 mating Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011111 cardboard Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000010186 staining Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は回路基板上に設けられたＩＣ等の電子部品を熱
硬化性樹脂で樹脂封止する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of resin-sealing electronic components such as ICs provided on a circuit board with a thermosetting resin.
近年、ＩＣカードや携帯用電子計算機等の小型で且つ薄
型の電子機器の開発が急速に進歩している。このような
電子機器では、小型・薄型の形状を保つために内部に収
納されているＩＣチップ等の電子部品を小型・薄型に実
装することが要求されている。以下の説明では、従来の
ＩＣカード及びＩＣカードに収納されるＩＣモジ−−ル
を例にして従来の技術を説明する。In recent years, the development of small and thin electronic devices such as IC cards and portable electronic computers has progressed rapidly. In such electronic devices, in order to maintain a small and thin shape, electronic components such as IC chips housed inside are required to be mounted small and thin. In the following description, the conventional technology will be explained using a conventional IC card and an IC module housed in the IC card as examples.
第６図は従来のＩＣカードの外観図、第７図は第６図の
Ａ−Ａ断面図、第８図はＩＣカードのカード基体を示す
外観図、第９図は従来のＩＣチップ樹脂封止構造を示す
断面図、第１０図は従来のＩＣモジュールを示す外観図
である。Fig. 6 is an external view of a conventional IC card, Fig. 7 is a sectional view taken along line A-A in Fig. 6, Fig. 8 is an external view showing the card base of the IC card, and Fig. 9 is a conventional IC chip resin sealing. FIG. 10 is a cross-sectional view showing the stopping structure, and an external view showing a conventional IC module.
第６図において、ＩＣカード６０は表面に複数のデータ
入出力端子ろ３ａが設けられており、全体の形状は第８
図に示したプラスチック製のカード基体６１で決められ
ている。In FIG. 6, an IC card 60 is provided with a plurality of data input/output terminals 3a on its surface, and the overall shape is 8.
This is determined by a plastic card base 61 shown in the figure.
第７図に示すごとく、このカード基体ろ１には、凹部３
１ａが形成されており、この四部３１ａ内には、ＣＰＵ
、メモリチップ等のＩＣチップ４６を回路基板６６にボ
ンディングし、ＩＣチップ４６へ樹脂による封止部６４
を形成したＩＣモジュール６２が収納固定される。As shown in FIG. 7, this card base filter 1 has a recess 3.
1a is formed, and within this four part 31a, a CPU
, an IC chip 46 such as a memory chip is bonded to a circuit board 66, and a resin sealing portion 64 is attached to the IC chip 46.
The IC module 62 formed therein is housed and fixed.
ＩＣカード６０は、カード基体ろ１の凹部３１ａ内にＩ
Ｃモジ−−ル６２を収納固定した後、カード基体３１の
両面をオーバーシート６５で覆って構成される。The IC card 60 is inserted into the recess 31a of the card base filter 1.
After the C module 62 is housed and fixed, both sides of the card base 31 are covered with an oversheet 65.
又第７図に示す各素子の関係は、ＩＣモジュール６２は
、封止部６４の上面が凹部３１ａの底面に当接して厚味
が規制され、又回路基板６６の外周が四部３１ａの内周
に係合して平面位置が規制されている。Furthermore, the relationship between the elements shown in FIG. 7 is that in the IC module 62, the top surface of the sealing portion 64 contacts the bottom surface of the recessed portion 31a to regulate the thickness, and the outer periphery of the circuit board 66 contacts the inner periphery of the four portions 31a. The plane position is regulated by engaging with.
一般にＩＣカード６０は厚さが約０．８ ｍｍであり、
携帯時や使用時に受ける外力によって破壊されないよう
にするため、ある程度の曲げに耐える柔軟性が必要であ
る。そのため、カード基体６１の柔軟性はもちろん必要
であるとともに、ＩＣモジュール３２は、曲げによって
ＩＣチップ４６の割れやボンディングワイヤーの断線等
が生じない様に、剛性が高く、又耐湿性にすぐれた樹脂
で封止する必要がある。Generally, the IC card 60 has a thickness of about 0.8 mm,
In order to prevent damage from external forces during carrying or use, it must be flexible enough to withstand bending to a certain extent. Therefore, it is of course necessary for the card base 61 to be flexible, and the IC module 32 is made of a resin with high rigidity and moisture resistance so that the IC chip 46 does not crack or the bonding wires do not break due to bending. It needs to be sealed.
しかも上記の如く薄いカード基体６１の凹部３１ａの底
面に封止部６４の上面が当接して厚味が規制されるので
、封止部６４は、厚味のバラツキが生じないように外形
形状を管理しなければならない。従って、従来から多用
しているＩＣチップ上に溶融樹脂を滴下させるポンティ
ング封正方法では、封止部６４の厚味にバラツキが生じ
易いので、ＩＣモジュール６２の封止部６４は、形状精
度が良く、かつ剛性の高い熱硬化性樹脂を用いたトラン
スファーモールド方法で形成するのが最適であった。Furthermore, as described above, the upper surface of the sealing portion 64 comes into contact with the bottom surface of the recess 31a of the thin card base 61, and the thickness is regulated. must be managed. Therefore, in the conventionally frequently used ponting sealing method in which molten resin is dropped onto an IC chip, variations in the thickness of the sealing part 64 tend to occur, so the sealing part 64 of the IC module 62 must be formed with precision in shape. The most suitable method was to use a transfer molding method using a thermosetting resin with good hardness and high rigidity.
第９図に基づいて従来のトランスファーモールドによる
ＩＣチップの樹脂封止構造を説明する。A resin sealing structure of an IC chip using a conventional transfer mold will be explained based on FIG.
第９図ＫＩｊＩＳいて、６６は下金型であり、その上面
にはＩＣチップ４６をボンディングした回路基板６６が
載置される。３７はキャビティー３７ａが形成された上
金型であり、」−金型６７はキャビティー３７ａがＩＣ
チップ４６の上面を覆うように下金型３６に固定される
。In FIG. 9, 66 is a lower mold, and a circuit board 66 to which an IC chip 46 is bonded is placed on the upper surface of the lower mold. 37 is an upper mold in which a cavity 37a is formed;
It is fixed to the lower mold 36 so as to cover the upper surface of the chip 46.
上金型６７にはゲート溝３９ａとランナー溝４０ａが形
成されており、この上金型６７と下金型６６の合わせ而
及び上金型６７と回路基板６６の合わせ面には、樹脂６
８をキャビティー３７ａに導くランナー４０及びゲート
６９が構成され、いわゆるサイドゲート方式のトランス
ファーモールド方法になる。A gate groove 39a and a runner groove 40a are formed in the upper mold 67, and a resin 6 is formed on the mating surfaces of the upper mold 67 and the lower mold 66 and the mating surfaces of the upper mold 67 and the circuit board 66.
A runner 40 and a gate 69 are configured to guide 8 into the cavity 37a, resulting in a so-called side gate type transfer molding method.
封止部６４は、加熱、溶融した樹脂６８をプランジャー
４１でランナー４０へ注入し、ゲート６９を通った樹脂
６８をキャビティー３７ａ内に充填することによって形
成され、更に樹脂６８が硬化したら上金型６７を外して
封止部６４が形成されたＩＣモジュール６２が取出され
る。The sealing portion 64 is formed by injecting heated and molten resin 68 into the runner 40 using the plunger 41, and filling the cavity 37a with the resin 68 that has passed through the gate 69. Furthermore, once the resin 68 is hardened, the upper The mold 67 is removed and the IC module 62 with the sealing portion 64 formed therein is taken out.
しかし、前述した如く上金型３７と回路基板６６の合わ
せ面にゲート６９が構成されるため、ＩＣモジュール６
２の回路基板６６上には、第１１図に示す如く封止部６
４につながってゲート残り３４ａが形成されてしまうと
いう問題があった。However, as described above, since the gate 69 is formed on the mating surface of the upper mold 37 and the circuit board 66, the IC module 69
As shown in FIG.
There was a problem in that the remaining gate 34a was formed by connecting to 4.
一般にカード基体６１はポリ塩化ビニルシート（以下Ｐ
ｖＣシートと略記する）を多層に貼り合せて構成されて
おり、ＩＣモジュール６２の封止部６４が収納される凹
部ろ１ａは、ザグリ加工によって形成されている。従っ
て第１１図に示したようにＩＣモジュール６２にゲート
残り３４ａが形成されると、第８図に示す如くカード基
板６１には更にゲート残り６４ａを収納するための溝部
３１ｂを形成しなければならないので、ザグリ加工が大
変面倒なものとなっていた。Generally, the card base 61 is a polyvinyl chloride sheet (hereinafter referred to as P
The recess 1a in which the sealing portion 64 of the IC module 62 is accommodated is formed by counterbore processing. Therefore, when the remaining gate 34a is formed in the IC module 62 as shown in FIG. 11, a groove 31b for accommodating the remaining gate 64a must be formed in the card board 61 as shown in FIG. Therefore, counterbore processing became very troublesome.
そこでカード基体６１に溝部３１ｂを形成しないように
するため、回路基板６６上のゲート残り３４ａを機械的
に除去すると、ゲート残り３４ａと回路基板６６の面３
３Ｃとの接着性が高いので、第１０図に示す如く１点鎖
線で示すゲート残り３４ａを折取る時に、その力がゲー
ト残り３４ａに及び、回路基板６６の面３３Ｃを剥離し
てしまい、場合によっては回路パターンまでも切断して
しまうという問題があった。Therefore, in order to prevent the formation of the groove portion 31b in the card base 61, when the remaining gate 34a on the circuit board 66 is mechanically removed, the remaining gate 34a and the surface 3 of the circuit board 66 are
3C, so when the remaining gate 34a indicated by the dashed-dotted line is broken off as shown in FIG. In some cases, there was a problem in that even the circuit pattern was cut.
そこでカード基体６１に溝部３１ｂを形成しなくても良
いようにするため、ＩＣモジュール６２の回路基板６６
上にゲート残り３４ａを形成しないでＩＣチップ４６を
封止できるトランスファーモールド方法が望まれていた
。Therefore, in order to eliminate the need to form the groove portion 31b in the card base 61, the circuit board 66 of the IC module 62 is
A transfer molding method that can seal the IC chip 46 without forming the gate residue 34a thereon has been desired.
しかるに前記従来の樹脂封止方法の持つ欠点を解決する
樹脂封止方法が特開平２−２００３３号公報に提案され
ている。However, a resin sealing method that solves the drawbacks of the conventional resin sealing method is proposed in Japanese Patent Laid-Open No. 2-20033.
この樹脂封止方法を第１］図、第１２図に基づいて説明
する。尚、前述の第９図と第１０図に示した構成と同一
のものについては、同一番号を付してその説明を省略す
る。This resin sealing method will be explained based on FIGS. 1 and 12. Components that are the same as those shown in FIGS. 9 and 10 described above are given the same numbers and their explanations will be omitted.
第１１図に示す如く上金型６７のゲート溝３９ａ、ラン
ナー溝４０ａに対向するＩＣモジ一シル６２回路基板６
ろ上には、予めシルク印刷等の方法によりソルダレジス
ト４２が形成されている。そして封止樹脂６８はこのフ
ルダレシスト４２上のランナー４０、ゲート３９を通っ
てキャビティー３７ａ内に充填されてＩＣチップ４６を
封止している。従ってソルダレジスト４２上で硬化した
封止樹脂６８は、ＩＣモジ−−ル６２を金型から取り出
した時に切り取られるので、第１３図に一点鎖線で示す
如く、回路基板６６上のゲート残り３４ａは存在せず、
第９図に示したようなカード基体６１の溝部３１ｂは不
要となる。As shown in FIG. 11, the IC module 62 circuit board 6 faces the gate groove 39a and runner groove 40a of the upper mold 67.
A solder resist 42 is previously formed on the filter by a method such as silk printing. The sealing resin 68 passes through the runner 40 on the filler resist 42 and the gate 39, and is filled into the cavity 37a to seal the IC chip 46. Therefore, the sealing resin 68 that has hardened on the solder resist 42 is cut off when the IC module 62 is taken out of the mold, so that the remaining gate 34a on the circuit board 66 is removed, as shown by the dashed line in FIG. does not exist,
The groove portion 31b of the card base 61 as shown in FIG. 9 becomes unnecessary.
しかしながら上記の如く、ＩＣモジュールの回路基板」
二にソルダレジストを形成してゲート残りを取り除く樹
脂封止構造においても、下記の如き問題があった。However, as mentioned above, the circuit board of the IC module
Second, the resin sealing structure in which a solder resist is formed and the remaining gate is removed also has the following problems.
即ち、ソルダレジストに対する封止樹脂の密着カシま、
回路基板に対するそれよりも幾分弱いものの比較的強く
密着するので、完全に取り除こうとすると、結局機械的
な除去処理が必要となり面倒であった。That is, the adhesiveness of the sealing resin to the solder resist,
Although it adheres to the circuit board relatively strongly, it is somewhat weaker than that of the circuit board, so if you try to completely remove it, you end up needing a mechanical removal process, which is troublesome.
又、回路基板上のゲート残りを除去する時に回路基板に
キズをつげたり、ゲート残りが多少残っタマまのＩＣモ
ジ−−ルをカード基体の凹部に接着すると、この部分で
不完全接着となってカード基体からＩＣモジ−−ルが脱
落するという問題があった。Also, if you scratch the circuit board when removing the remaining gate on the circuit board, or if some remaining gate remains and you glue the original IC module into the recessed part of the card base, the adhesion may be incomplete in this area. There was a problem in that the IC module fell off from the card base.
本発明の目的は上記問題点を解決し、サイドゲート方式
のトランスファーモールド方法において、回路基板上に
特別なレジストを形成せずに、しかも機械的な除去処理
をしなくても容易にゲート残りを取り除くことが可能な
樹脂封止構造を提供することである。An object of the present invention is to solve the above-mentioned problems, and to easily remove remaining gates in a side-gate transfer molding method without forming a special resist on a circuit board and without mechanical removal. It is an object of the present invention to provide a resin-sealed structure that can be removed.
以下図面により本発明の実施例を詳述する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図は本発明に於ける回路基板２の平面図であり、回
路基板２のダイパターン２ＣにはＩＣチップ４が接着さ
れており該ＩＣチップ４の接続電極である各パッドはリ
ードパターン２ｂとワイヤーボンデングされている。又
前記ＩＣチップ４のパッドの設けられていない一辺４ａ
に面する回路基板２上にはゲートパターン２ａが形成さ
れている。点線で示す円は後述する封止部乙の範囲を示
しており前記ゲートパターン２ａは回路基板２の外端部
から前記封止部乙の範囲にすこし喰込むように形成され
ている。尚、第２図に示すゲートパターン２ａは電気的
接続を有さない眸パターンになっているが、点線で示す
ごとく細いパターンにてダイパターン２Ｃに接続してお
いてもよい。尚前記ゲートパターン２ａはリードパター
ン２ｂと同一工程によって形成されており該リードパタ
ーン２ｂと同様銅箔上に薄い金メツキ層を形成したもの
である。FIG. 2 is a plan view of the circuit board 2 according to the present invention. An IC chip 4 is bonded to a die pattern 2C of the circuit board 2, and each pad serving as a connection electrode of the IC chip 4 is connected to a lead pattern 2B. and wire bonded. Also, one side 4a of the IC chip 4 on which no pad is provided
A gate pattern 2a is formed on the circuit board 2 facing. A circle indicated by a dotted line indicates a range of a sealing part B, which will be described later, and the gate pattern 2a is formed so as to slightly cut into the range of the sealing part B from the outer end of the circuit board 2. Although the gate pattern 2a shown in FIG. 2 has an eye pattern with no electrical connection, it may be connected to the die pattern 2C with a thin pattern as shown by dotted lines. The gate pattern 2a is formed by the same process as the lead pattern 2b, and like the lead pattern 2b, a thin gold plating layer is formed on copper foil.
次に本発明に於げるＩＣモジ−−ルの樹脂封止構造を第
３図、第４図及び第１図に基づいて説明する。尚、第９
図及び第１１図と同一のものについては同一番号を付し
てその説明を省略する。 ゛第３図に示すごとく
上金型６７のゲート溝３９ａ、ランナー溝４０ａに対向
する丁Ｃモジュール１の回路基板２上には前述のごとく
ゲートパターン２ａが設けられており、封止樹脂６８は
このゲートパターン２ａ上のランナー４ｏ、ゲート６９
を通ってキャビティー３７ａ内に充填されることにより
ＩＣチップ４を封止している。Next, the resin sealing structure of the IC module according to the present invention will be explained based on FIGS. 3, 4, and 1. Furthermore, the 9th
Components that are the same as those in the figures and FIG. 11 are given the same numbers and their explanations will be omitted. 3, the gate pattern 2a is provided on the circuit board 2 of the C module 1 facing the gate groove 39a and the runner groove 40a of the upper mold 67, as described above, and the sealing resin 68 is Runner 4o on this gate pattern 2a, gate 69
The IC chip 4 is sealed by passing through and filling the cavity 37a.
第４図は第３図のＢ−Ｂ断面図でありゲート溝３９ａと
ゲートパターン２ａの断面を示すものである。FIG. 4 is a sectional view taken along the line BB in FIG. 3, showing the cross section of the gate groove 39a and the gate pattern 2a.
すなわちゲートパターン２ａは銅箔層５の表面上に薄い
金層６をメツキ処理したものであり前記リードパターン
２ｂと同一工程によって形成されている。そして前記ゲ
ートパターン２ａ上の金層６は基板やソルダーンジスト
に比べて封止樹脂６８との密着力が著しく低いためゲー
トパターン２ａ上で硬化した封止樹脂６８はＩＣモジュ
ール１を金型から取り出すときに簡単に切り取られてし
まうため第１図に一点鎖線で示す如く回路基板２上には
ゲート残り６ａは存在しない。That is, the gate pattern 2a is formed by plating a thin gold layer 6 on the surface of the copper foil layer 5, and is formed by the same process as the lead pattern 2b. Since the gold layer 6 on the gate pattern 2a has significantly lower adhesion to the sealing resin 68 than the substrate or solder paste, the sealing resin 68 hardened on the gate pattern 2a removes the IC module 1 from the mold. Since it is easily cut off when taken out, there is no remaining gate 6a on the circuit board 2 as shown by the dashed line in FIG.
第５図を土木発明の他の実施例を示す回路基板２の平面
図であり、第２図と同一のものについては同一番号を付
し説明を省略する。FIG. 5 is a plan view of a circuit board 2 showing another embodiment of the civil engineering invention, and the same parts as in FIG. 2 are given the same numbers and the explanation will be omitted.
第５図に於いて第２図と異るところは、第２図のゲート
パターン２ａが電気的な接続を有さない汁パターンであ
るのに対し、第５図のゲートパターン２ａは電源端子等
の電気的機能な有するパターンであり前記丁Ｃチップ４
のパッドとワイヤーボンデングされていることである。The difference between FIG. 5 and FIG. 2 is that the gate pattern 2a in FIG. 2 is a pattern with no electrical connections, whereas the gate pattern 2a in FIG. It is a pattern having an electrical function of the above-mentioned C chip 4.
The pads and wires are bonded.
すなわち第２図に示すＩＣカード用のＩＣモジュールの
場合はＩＣチップ４にパッドを設けない辺が存在するの
で前記ゲートリード２ａを猪パターンとして設けること
が出来るが、第５図に示すメモリカード用のＩＣモジ−
−ルの場合にはパッドを設けない辺が存在しないので、
リードパターンの１つを中広にしてゲートパターンにす
る方式％式％
尚、本実施例に於いてはゲートパターン２ａをリードパ
ターン２ｂと同一工程によって形成可能な金層６とした
が、これに限定されるものではなく、銀、クロム、ニッ
ケル等の面状態が安定した難酸化金属層であれば前記封
止樹脂６８との密着力を低くすることが可能であり、ゲ
ートパターンとして利用することが出来る。That is, in the case of the IC module for an IC card shown in FIG. 2, since there is a side of the IC chip 4 on which no pad is provided, the gate lead 2a can be provided as a boar pattern, but in the case of the IC module for the memory card shown in FIG. IC module
- In the case of a 3-sided case, there are no sides on which no pads are provided, so
A method in which one of the lead patterns is made into a gate pattern by widening it into a gate pattern.In this embodiment, the gate pattern 2a is the gold layer 6 which can be formed in the same process as the lead pattern 2b. The layer is not limited to oxidation-resistant metal layers such as silver, chromium, nickel, etc., which have a stable surface condition, so that the adhesion to the sealing resin 68 can be lowered, and the layer can be used as a gate pattern. I can do it.
」二記のごとく本発明によれば、回路基板上に形成した
金属層をゲートパターンとして封止樹脂のゲート残りを
除去するようにしているため回路基板面をキズにしたり
、汚したりすることなく、又特別な機械的除去処理を必
要とすることなくゲート残りの存在しないＩＣモジ−−
ルを提供することが可能となる。2, according to the present invention, the metal layer formed on the circuit board is used as a gate pattern and the remaining gate of the sealing resin is removed, without damaging or staining the circuit board surface. , and IC modules with no gate residue without the need for special mechanical removal processes.
This makes it possible to provide the following information.
さらにゲートパターンの形成うまリードパターンと同一
丁稚で行うことが出来るため特別な費用を必要としない
等、回路基板を用いたＩＣモジュールの品質向上に犬な
る効果を有する。Furthermore, since the gate pattern can be formed in the same manner as the lead pattern, no special cost is required, which has a significant effect on improving the quality of IC modules using circuit boards.
第１図〜第５図は本発明の実施例を示し、第１図はＩＣ
モジュールの外観図、第２図及び第５図は回路基板の平
面図、第３図はＩＣチップ樹脂封止構造を示す断面図、
第４図（ま第３図のＢ−Ｂ断面図である。
第６図は従来のＩＣカードの外観図、第７図は第６図の
Ａ−Ａ断面図、第８図は丁Ｃカードのカード基体を示す
外観図、第９図及び第１１図は従来のＩＣチップ樹脂封
止構造を示す断面図、第１０図及び第１２図は従来の■
Ｃモジーールを示す外観図である。
Ｌ ３２・・・・・ＩＣモジュール、２．３６・・・
・・・回路基板、
４．４６・・・・・・ＩＣチップ、
２ａ・・・・・ゲートパターン、
６ａ、３４ａ・・・・・・ゲート残り。1 to 5 show embodiments of the present invention, and FIG. 1 shows an IC
An external view of the module, FIGS. 2 and 5 are plan views of the circuit board, and FIG. 3 is a cross-sectional view showing the IC chip resin sealing structure.
Figure 4 (This is a cross-sectional view taken along line B-B in Figure 3. Figure 6 is an external view of a conventional IC card, Figure 7 is a cross-sectional view taken along line A-A in Figure 6, and Figure 8 is a cross-sectional view of a IC card. Figures 9 and 11 are cross-sectional views showing the conventional IC chip resin sealing structure, and Figures 10 and 12 are the conventional IC chip resin sealing structures.
It is an external view showing the C module. L 32...IC module, 2.36...
...Circuit board, 4.46...IC chip, 2a...gate pattern, 6a, 34a...remaining gate.
Claims (5)
搭載した回路基板の前記ＩＣチップを、成型金型を用い
て前記樹脂基板の周縁から離れた内側で樹脂封止してな
る半導体装置において、前記樹脂基板上の前記成型金型
に設けられた封止樹脂注入用のゲート溝に対応する位置
に、金属薄膜層を形成したことを特徴とする樹脂封止型
半導体装置。(1) In a semiconductor device in which the IC chip of a circuit board having an IC chip mounted on a resin substrate having an electrode pattern is resin-sealed using a mold on the inner side away from the periphery of the resin substrate, A resin-sealed semiconductor device, characterized in that a metal thin film layer is formed on the resin substrate at a position corresponding to a gate groove for injection of sealing resin provided in the mold.
ことを特徴とする請求項１記載の樹脂封止型半導体装置
。(2) The resin-sealed semiconductor device according to claim 1, wherein the metal thin film layer is the same metal layer as the electrode pattern.
膜層であることを特徴とする請求項２記載の樹脂封止型
半導体装置。(3) The resin-sealed semiconductor device according to claim 2, wherein the metal thin film layer is a thin film layer obtained by performing oxidation-resistant metal treatment on copper foil.
記金属薄膜層は前記接続電極を有さない一辺に対応した
樹脂基板上に設けられていることを特徴とする請求項１
記載の樹脂封止型半導体装置。(4) The IC chip has one side without a connection electrode, and the metal thin film layer is provided on a resin substrate corresponding to the side without the connection electrode.
The resin-sealed semiconductor device described above.
極パターンであり、かつ他の電極パターンに比べて巾広
に形成されていることを特徴とする請求項１記載の樹脂
封止型半導体装置。(5) The resin-sealed type according to claim 1, wherein the metal thin film layer is an electrode pattern electrically connected to the IC chip, and is formed wider than other electrode patterns. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2303932A JP2706000B2 (en) | 1990-11-13 | 1990-11-13 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2303932A JP2706000B2 (en) | 1990-11-13 | 1990-11-13 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04177753A true JPH04177753A (en) | 1992-06-24 |
| JP2706000B2 JP2706000B2 (en) | 1998-01-28 |
Family
ID=17927020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2303932A Expired - Lifetime JP2706000B2 (en) | 1990-11-13 | 1990-11-13 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2706000B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL9500511A (en) * | 1994-03-16 | 1995-11-01 | Amkor Electronics | Mold runner removal of a substrate-based, encapsulated, electronic building block. |
| FR2734947A1 (en) * | 1995-05-31 | 1996-12-06 | Sgs Thomson Microelectronics | Encapsulation of semiconductor devices partic. those without pin connections |
| FR2734948A1 (en) * | 1995-05-31 | 1996-12-06 | Sgs Thomson Microelectronics | Encapsulation of semiconductor devices partic. those without pin connections |
| CN1081847C (en) * | 1997-06-17 | 2002-03-27 | 三菱电机株式会社 | Method and apparatus for control of pulse width modulation inverter unit |
| US7095115B2 (en) | 2001-04-05 | 2006-08-22 | Micron Technology, Inc. | Circuit substrates, semiconductor packages, and ball grid arrays |
-
1990
- 1990-11-13 JP JP2303932A patent/JP2706000B2/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL9500511A (en) * | 1994-03-16 | 1995-11-01 | Amkor Electronics | Mold runner removal of a substrate-based, encapsulated, electronic building block. |
| FR2734947A1 (en) * | 1995-05-31 | 1996-12-06 | Sgs Thomson Microelectronics | Encapsulation of semiconductor devices partic. those without pin connections |
| FR2734948A1 (en) * | 1995-05-31 | 1996-12-06 | Sgs Thomson Microelectronics | Encapsulation of semiconductor devices partic. those without pin connections |
| CN1081847C (en) * | 1997-06-17 | 2002-03-27 | 三菱电机株式会社 | Method and apparatus for control of pulse width modulation inverter unit |
| US7095115B2 (en) | 2001-04-05 | 2006-08-22 | Micron Technology, Inc. | Circuit substrates, semiconductor packages, and ball grid arrays |
| US7148083B2 (en) | 2001-04-05 | 2006-12-12 | Micron Technology, Inc. | Transfer mold semiconductor packaging processes |
| US7384805B2 (en) * | 2001-04-05 | 2008-06-10 | Micron Technology, Inc. | Transfer mold semiconductor packaging processes |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2706000B2 (en) | 1998-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100551641B1 (en) | A method of manufacturing a semiconductor device and a semiconductor device | |
| KR100587851B1 (en) | A method of manufacturing a semiconductor device | |
| KR100214555B1 (en) | Method for manufacture of semiconductor package | |
| US7141868B2 (en) | Flash preventing substrate and method for fabricating the same | |
| JP3332654B2 (en) | Semiconductor device substrate, semiconductor device, and method of manufacturing semiconductor device | |
| US5981873A (en) | Printed circuit board for ball grid array semiconductor package | |
| US5250470A (en) | Method for manufacturing a semiconductor device with corrosion resistant leads | |
| US5382546A (en) | Semiconductor device and method of fabricating same, as well as lead frame used therein and method of fabricating same | |
| US7435624B2 (en) | Method of reducing mechanical stress on a semiconductor die during fabrication | |
| US5406119A (en) | Lead frame | |
| US8878346B2 (en) | Molded SiP package with reinforced solder columns | |
| JPH04177753A (en) | Resin sealing type semiconductor device | |
| US6891254B2 (en) | Semiconductor device with protrusions | |
| US20070267759A1 (en) | Semiconductor device with a distributed plating pattern | |
| JP2977889B2 (en) | IC resin sealing method | |
| JPH0936155A (en) | Manufacture of semiconductor device | |
| CN111799243A (en) | Chip packaging substrate and manufacturing method thereof, chip packaging structure and packaging method | |
| KR970011135B1 (en) | Ball grid array package with degating area on pcb board and the molding method | |
| JP3713306B2 (en) | Semiconductor chip resin sealing device | |
| JPH0322467A (en) | Molding die for lead of ic | |
| JP2707673B2 (en) | IC module and manufacturing method thereof | |
| CN108831839B (en) | Method for removing burrs generated in semiconductor plastic packaging process | |
| KR0145767B1 (en) | Thin film semiconductor package and the manufacturing method | |
| KR100195514B1 (en) | Chip on board package and ic card using the same | |
| KR100886701B1 (en) | Method for packaging a semiconductor chip in fbga type |