CN110504174A - The forming method of encapsulating structure - Google Patents
The forming method of encapsulating structure Download PDFInfo
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- CN110504174A CN110504174A CN201910675804.4A CN201910675804A CN110504174A CN 110504174 A CN110504174 A CN 110504174A CN 201910675804 A CN201910675804 A CN 201910675804A CN 110504174 A CN110504174 A CN 110504174A
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- layer
- plastic packaging
- metal coupling
- pad
- support plate
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- 239000004065 semiconductor Substances 0.000 claims abstract description 125
- 238000004806 packaging method and process Methods 0.000 claims abstract description 114
- 229920003023 plastic Polymers 0.000 claims abstract description 114
- 239000004033 plastic Substances 0.000 claims abstract description 114
- 229910052751 metal Inorganic materials 0.000 claims description 119
- 239000002184 metal Substances 0.000 claims description 119
- 239000000463 material Substances 0.000 claims description 103
- 230000008878 coupling Effects 0.000 claims description 102
- 238000010168 coupling process Methods 0.000 claims description 102
- 238000005859 coupling reaction Methods 0.000 claims description 102
- 238000002955 isolation Methods 0.000 claims description 45
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- 238000005530 etching Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 239000008187 granular material Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
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- 239000004698 Polyethylene Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
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- 229920000647 polyepoxide Polymers 0.000 description 3
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- 150000000183 1,3-benzoxazoles Chemical class 0.000 description 2
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
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- 229910052802 copper Inorganic materials 0.000 description 2
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- 239000005038 ethylene vinyl acetate Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 229920001707 polybutylene terephthalate Polymers 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
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- 229920001155 polypropylene Polymers 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- 241000208340 Araliaceae Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical group [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
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- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 239000007888 film coating Substances 0.000 description 1
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- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
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- 150000003254 radicals Chemical class 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of forming method of encapsulating structure, several chips for having the first plastic packaging layer are provided, the presence of first plastic packaging layer, so that each semiconductor chip surface all has flat surface, when the first plastic packaging layer on several discrete semiconductor chips is bonded with support plate, since the first plastic packaging layer has flat surface, so that all having higher adhesion strength between each semiconductor chip and support plate, to when forming the second plastic packaging layer for coating several semiconductor chips on support plate, when being molded or turning the compression shock of modeling, all semiconductor chips position on support plate will not all generate offset, to subsequent after removing support plate, form preformed cover plate, when the back side of preformed cover plate forms the wiring layer again connecting with pad, wiring layer will not generate offset with the link position of corresponding pad again, to improve cloth again It is electrically connected performance between line layer and pad, to improve the stability and reliability of encapsulating structure.
Description
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of forming methods of fan-out package structure.
Background technique
The encapsulation of chip fan-in type is to be routed to prepare with solder ball salient point again in whole wafer, is finally cut into list again
A kind of production method of chips.The final encapsulation size of this kind encapsulation is suitable with chip size, and the small-sized of encapsulation may be implemented
Change and lightweight, have a wide range of applications in a portable device.After although encapsulation can be greatly reduced in the encapsulation of chip fan-in type
Chip size, but the plant ball limited amount in single chip, the wafer level packaging form are dfficult to apply to the port high density I/O
On several chips.Thus, chip higher for I/O density ratio, if carrying out wafer level packaging, in order to ensure chip to be packaged
It is capable of forming the packaging pin that interconnects and highdensity I/O must be fanned out to as low-density with printed wiring board, that is, carries out chip
Fan-out package is encapsulated relative to traditional chip fan-in type, the available smaller package dimension of chip fan-out package, more
Good electricity thermal property and higher packaging density.
Currently, the main process of chip fan-out package includes: first that several semiconductor chips after segmentation are positive (just
Face is the one side for being formed with pad) it is bonded on support plate by adhesive tape or adhesive layer；Covering semiconductor chip is formed on support plate
Plastic packaging layer, on support plate several semiconductor chips carry out plastic packaging；Remove the support plate, then semiconductor chip front into
Row is routed again, forms the wiring layer again connecting with pad；The tin ball connecting with wiring layer again is formed on wiring layer again；It is most laggard
Row cutting, forms several discrete encapsulating structures.
But the encapsulating structure that existing chip fan-out package technique is formed, then the electricity company of wiring layer and semiconductor chip
It connects and is easy unstable, affect the performance of encapsulating structure.
Summary of the invention
Cloth again in the encapsulating structure formed the technical problem to be solved by the present invention is to improve chip fan-out package technique
Line layer and semiconductor chip are electrically connected stability, improve the performance of encapsulating structure.
The present invention provides a kind of forming methods of encapsulating structure, comprising:
Several semiconductor chips are provided, each semiconductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces,
There are several pads on the functional surfaces, metal coupling is formed in the bond pad surface, also has first on the functional surfaces
Plastic packaging layer, the surface of the first plastic packaging layer are flushed with the metal coupling top surface；
Support plate is provided；
By on the functional surfaces of several semiconductor chips the first plastic packaging layer and pad be bonded on support plate；
The second plastic packaging layer of the non-functional surface and sidewall surfaces that coat the semiconductor chip is formed on the support plate；
The support plate is removed, preformed cover plate is formed, the preformed cover back exposes the pad；
The external contact structure connecting with metal coupling is formed at the back side of the preformed cover plate.
Optionally, the forming process of the semiconductor chip are as follows: wafer is provided, if being formed with dry semiconductor on the wafer
Chip, the semiconductor chip include functional surfaces, have pad on the functional surfaces；Metal coupling is formed on the pad；
Form the first capsulation material layer for covering the metal coupling and functional surfaces；The first capsulation material layer is planarized, is exposed
The metal coupling top surface, remaining first capsulation material layer is as the first plastic packaging layer；Planarize the first plastic packaging material
After the bed of material, the wafer is cut, forms several discrete semiconductor chips.
Optionally, the material of the first capsulation material layer and the second plastic packaging layer is resin, the first capsulation material layer
Formation process with the second plastic packaging layer is to be molded or turn modeling technique.
Optionally, in the first plastic packaging layer material granule size less than material granule in the second plastic packaging layer size.
Optionally, the first capsulation material layer is planarized by chemical mechanical milling tech, it is convex exposes the metal
Block top surface.
Optionally, the metal coupling further includes being formed positioned at the top surface of metal coupling or top and sidewall surfaces
Isolation sacrificial layer, the surface that the surface of the first plastic packaging layer and the surface that sacrificial layer is isolated flush with sacrificial layer is isolated
Surface flush.
Optionally, the forming process of the semiconductor chip are as follows: wafer is provided, if being formed with dry semiconductor on the wafer
Chip, the semiconductor chip include functional surfaces, have pad on the functional surfaces；Metal coupling is formed on the pad；
Isolation sacrificial layer is formed on metal coupling；Form the first capsulation material layer of the covering isolation sacrificial layer and functional surfaces；It is flat
The smoothization first capsulation material layer exposes the surface of the isolation sacrificial layer, and remaining first capsulation material layer is as the
The surface of one plastic packaging layer, the first plastic packaging layer is flushed with the surface that sacrificial layer is isolated；Planarize the first capsulation material layer
Afterwards, the wafer is cut, several discrete semiconductor chips are formed.
Optionally, after removing the support plate, the isolation sacrificial layer is removed, so that the preformed cover back exposes institute
State pad.
Optionally, the etching technics is wet etching or dry etching.
Optionally, the material of the isolation sacrificial layer is silica, silicon nitride or silicon oxynitride.
Optionally, the external contact structure includes the cloth again connecting on the preformed cover version back side with metal coupling
Line layer and the external contacts being connect on wiring layer again with wiring layer again.
Optionally, the forming process of the wiring layer again and external contacts includes: after removing the support plate, described
Wiring layer again is formed on the back side of preformed cover plate；Insulating layer, the insulation are formed on the back side of wiring layer again and preformed cover version
The opening for exposing wiring layer part of the surface again is formed in layer；External contacts are formed in said opening.
Optionally, the external contact structure is being formed, further includes: cut the preformed cover plate, formed several discrete
Encapsulating structure.
Compared with prior art, technical solution of the present invention has the advantage that
The forming method of encapsulating structure of the invention provides several semiconductor chips, the functional surfaces of each semiconductor chip
It is upper that there is pad, it is formed with metal coupling in the bond pad surface, also there is the first plastic packaging layer on the functional surfaces, described first
The surface of plastic packaging layer is flushed with the metal coupling top surface；By the first modeling on the functional surfaces of several semiconductor chips
Sealing and pad are bonded on support plate；The non-functional surface and sidewall surfaces for coating the semiconductor chip are formed on the support plate
The second plastic packaging layer.The presence of first plastic packaging layer, so that each semiconductor chip surface all has flat surface, if will
When the first plastic packaging layer and support plate on dry discrete semiconductor chip are bonded, since the first plastic packaging layer has flat table
Face, so that higher adhesion strength is all had between each semiconductor chip and support plate, so that it is several to form cladding on support plate
When the second plastic packaging layer of semiconductor chip, when being molded or turning the compression shock of modeling, all semiconductor chips are in support plate
Upper position will not all generate offset, thus subsequent after removing support plate, form preformed cover plate, the back side of preformed cover plate formed with
When the wiring layer again of pad connection, then wiring layer will not generate offset with the link position of corresponding pad, to improve again
It is electrically connected performance between wiring layer and pad, to improve the stability and reliability of encapsulating structure.
Further, the metal coupling further includes being formed positioned at the top surface of metal coupling or top and sidewall surfaces
Isolation sacrificial layer, the first capsulation material layer cover it is described isolation sacrificial layer the first plastic packaging layer, chemical machine can be passed through
Technique removal part the first capsulation material layer and isolation sacrificial layer that both tool grinding technics and subsequent etching technics combine
To expose metal coupling, specifically, first using the first capsulation material layer exposure of chemical mechanical milling tech removal part
Out then the surface of the isolation sacrificial layer, remaining first capsulation material layer are gone as the first plastic packaging layer using etching technics
Except the isolation sacrificial layer on metal coupling top surface, the top surface of metal coupling is exposed, thus can not only be exposed
The top surface of metal coupling out, and due to removing part the first capsulation material layer using chemical mechanical milling tech
When, exposure is isolation sacrificial layer surface, and the grinding pad in milling apparatus will not be contacted with metal coupling, because without to metal
Convex block brings abrasive power, loosens or falls off from pad to preferably prevent metal coupling from generating, further increases subsequent
The precision of link position, it is convex with metal to further improve again wiring layer between the wiring layer again and corresponding metal coupling formed
Block is electrically connected performance.
Further, the forming process of the semiconductor chip are as follows: wafer is provided, if being formed with dry semiconductor on the wafer
Chip, the semiconductor chip include functional surfaces, have pad on the functional surfaces；Metal coupling is formed on the pad；
The first capsulation material layer of the covering metal coupling and functional surfaces is formed by being molded or turning modeling technique；Planarize described first
Capsulation material layer exposes the metal coupling top surface, and remaining first capsulation material layer is as the first plastic packaging layer；It is flat
After changing the first capsulation material layer, the wafer is cut, forms several discrete semiconductor chips.It is carrying out injection molding or is turning modeling
When technique, bottom is fixed in mold, since the area of bottom is larger, wafer is in the mould for being molded or turning modeling equipment
It will not be moved in tool, so that the first capsulation material layer formed has flat surface, the first plastic packaging material described in subsequent planarization
The bed of material, exposes the metal coupling top surface, and remaining first capsulation material layer also has flat as the first plastic packaging layer
Surface, after being cut wafer, several discrete semiconductor chips of formation all have flat surface, and several
The thickness of semiconductor chip is able to maintain unanimously, it is subsequent by several discrete semiconductor chips the first plastic packaging layer and pad with
When support plate is bonded, since the first plastic packaging layer has flat surface, so that between each semiconductor chip and support plate
Adhesion strength with higher.
Further, the size of material granule is less than material in the second plastic packaging layer being subsequently formed in the first plastic packaging layer
The size of grain enables the first plastic packaging layer more preferably to fill between metal coupling and the gap of two sides, so that the first plastic packaging layer and gold
Belong to convex block side contact more closely so that the first plastic packaging layer is more preferable to the fixed effect of metal coupling.
Detailed description of the invention
Fig. 1-Figure 19 is the structural schematic diagram of the forming process of encapsulating structure of the embodiment of the present invention.
Specific embodiment
As described in the background art, the encapsulating structure that existing chip fan-out package technique is formed, then wiring layer and semiconductor
Being electrically connected of chip is easy unstable, affects the performance of encapsulating structure.
The study found that in existing fan-out package structure again wiring layer and semiconductor chip be electrically connected be easy it is unstable
Producing reason are as follows: the link position of the pad of wiring layer and semiconductor chip produces offset again.
Further study show that then the link position of pad of wiring layer and semiconductor chip the reason of producing offset
Are as follows: when carrying out being fanned out to encapsulation, several semiconductor chips are be bonded in load by adhesive tape or adhesive layer on one side with pad
It is different especially when being also formed with metal coupling on pad since different semiconductor chip surface flatness is different on plate
The surface smoothness difference of chip can be bigger, so that different semiconductor chips and support plate pass through adhesive tape or adhesive layer is Nian Jie is glued
When connecing, the bonding force between different semiconductor chips and support plate be it is different, when forming plastic packaging layer, part semiconductor chip due to
Bonding force is insufficient, which can generate offset,
After removing support plate, when forming wiring layer again on the front of plastic packaging layer and semiconductor chip so that again wiring layer with there are positions
The link position for setting the pad of the semiconductor core on piece of offset generates offset, to influence in the fan-out packaging structure to be formed cloth again
Line layer and pad are electrically connected performance.
For this purpose, the present invention provides a kind of encapsulating structure and forming method thereof, the forming method, if providing dry semiconductor
Chip has pad on the functional surfaces of each semiconductor chip, is formed with metal coupling, the functional surfaces in the bond pad surface
On also have the first plastic packaging layer, the surface of the first plastic packaging layer is flushed with the metal coupling top surface；It will be described several
The first plastic packaging layer and pad on the functional surfaces of semiconductor chip are bonded on support plate；Cladding described half is formed on the support plate
The non-functional surface of conductor chip and the second plastic packaging layer of sidewall surfaces.The presence of first plastic packaging layer, so that each semiconductor core
Piece surface all has flat surface, bonds by the first plastic packaging layer on several discrete semiconductor chips with support plate
When, since the first plastic packaging layer has flat surface, so that being all had between each semiconductor chip and support plate higher viscous
Attached power, thus when forming the second plastic packaging layer for coating several semiconductor chips on support plate, in the pressure for being molded or being turned modeling
When impact, all semiconductor chips position on support plate will not all generate offset, thus it is subsequent after removing support plate, it is formed pre-
Cover board, when the back side of preformed cover plate forms the wiring layer again connecting with pad, then the connection of wiring layer and corresponding pad
Position will not generate offset, be electrically connected performance between wiring layer and pad again to improve, to improve encapsulation knot
The stability and reliability of structure.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio
Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in the production of border.
Fig. 1-Figure 19 is the structural schematic diagram of the forming process of encapsulating structure of the embodiment of the present invention.
With reference to Fig. 1-7, several semiconductor chips 160 (with reference to Fig. 7) are provided, each semiconductor chip 160 includes functional surfaces
11 and the non-functional surface 12 opposite with functional surfaces 11, there is several pads 101,101 surface of pad on the functional surfaces 11
On be formed with metal coupling 102, also there is the first plastic packaging layer 103, the surface of the first plastic packaging layer 103 on the functional surfaces 11
It is flushed with 102 top surface of metal coupling.
The semiconductor chip 160 has functional surfaces 11 and the non-functional surface 12 opposite with functional surfaces 11, the functional surfaces
For the one side for being formed with integrated circuit and pad, the integrated circuit is formed in the semiconductor chip 160, several pads
101 are formed on the functional surfaces of the semiconductor chip 160, the pad 101 and the integrated circuit electricity in semiconductor chip 160
Connection, port of the pad 101 as integrated circuit and external electrical connections in semiconductor chip 160.In one embodiment,
Integrated circuit in the semiconductor chip 160 may include several semiconductor devices (such as transistor, memory, sensor,
Diode and/or triode etc.) and by semiconductor devices connect interconnection structure (including metal connecting line and metal plug).It needs
It is noted that surrounded surface is semiconductor chip between the functional surfaces 11 and non-functional surface 12 of the semiconductor chip 160
160 side wall.
The semiconductor chip 160 is formed by semiconductor integration making technology, the tool that the semiconductor chip 160 is formed
Body process is described in detail below with reference to Fig. 1-7.
Firstly, please referring to Fig. 1 and Fig. 2, Fig. 2 is Fig. 1 along the schematic diagram of the section structure in the direction cutting line AB, provides wafer
100, the chip area and the Cutting Road region between chip area that the wafer 100 includes several ranks arrangement；Institute
Several chip areas for stating wafer 100 are correspondingly formed several semiconductor chips 160；In the functional surfaces of the semiconductor chip 160
It is upper to form several pads 101.
In one embodiment, the material of the wafer 100 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe
(GeSi), silicon carbide (SiC)；It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be others
III-V compounds of group such as material, such as GaAs.The material of the pad 101 can be in aluminium, nickel, tin, tungsten, platinum, copper, titanium
One kind.
It is the enlarged structure schematic diagram for forming metal coupling in Fig. 3 on a pad with reference to Fig. 3 and Fig. 4, Fig. 4, described
Metal coupling 102 is formed on 101 surface of pad.
The metal coupling 102 protrudes from the surface of pad 101 and functional surfaces, and in one embodiment, the metal is convex
One or more of the materials of aluminum of block 102, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, silver form the mesh of metal coupling 102
Be pad 101 is drawn into height, be convenient for subsequent wiring, and the metal coupling 102 also has protection pad and heat transfer
Effect.
In one embodiment, the process that the metal coupling 102 is formed includes: the function in the semiconductor chip 160
Insulating layer 150 is formed on face 11, and there is the first opening for exposing 101 part of the surface of pad in the insulating layer 150, it is described exhausted
Edge layer 150 can be single-layer or multi-layer stacked structure, and the material of the insulating layer 150 can be silicon nitride, silica, resinous wood
One or more of material；Convex lower metal layer is formed in the side wall and bottom surface of 150 surface of insulating layer and the first opening
(UBM), the convex lower metal layer can be single-layer or multi-layer stacked structure；Being formed on the convex lower metal layer has second to open
The mask layer of mouth, second opening at least expose the convex lower metal layer surface in the first opening；It is being told by electroplating technology
Metal coupling 102 is formed in the opening of Sohu second；Remove the mask layer；The insulating layer of etching removal 102 two sides of metal coupling
The convex lower metal layer on surface.
With reference to Fig. 5, the first capsulation material layer is formed on the surface of wafer 100 (functional surfaces of semiconductor chip 160)
123, the first capsulation material layer 123 covers the metal coupling 102.
The first capsulation material layer 123 cover top and the sidewall surfaces of the metal coupling 102, the first plastic packaging material
The bed of material 123 has flat surface, and the formation process of the first capsulation material layer 123 is to be molded or turn modeling technique, and described the
The material of one plastic packaging layer 103 is resin, and the resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin, gather
Benzoxazoles resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene,
In polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol
It is one or more of.
Specifically, 100 bottom of wafer is fixed in mold, when be molded or turn modeling technique due to bottom
Area it is larger, wafer be molded or turn modeling equipment mold in will not move so that formed the first capsulation material layer 123 tool
There is flat surface, the first capsulation material layer 123 described in subsequent planarization exposes 102 top surface of metal coupling, remains
The first remaining capsulation material layer also has flat surface, after being cut wafer, formation as the first plastic packaging layer 103
Several discrete semiconductor chips 160 all have flat surface, and the thickness of several semiconductor chips 160 is able to maintain one
Cause, it is subsequent by several discrete semiconductor chips 160 the first plastic packaging layer 103 and pad and support plate bonded when, by
There is flat surface in the first plastic packaging layer 103, so that all having between each semiconductor chip 160 and support plate higher viscous
Attached power, thus it is subsequent when forming the second plastic packaging layer for coating several semiconductor chips 160 on support plate, it is being molded or is being turned modeling
Compression shock when, all semiconductor chips 160 position on support plate will not all generate offset, thus it is subsequent removal support plate
Afterwards, preformed cover plate is formed, when the back side of preformed cover plate forms the wiring layer again connecting with pad, then wiring layer and corresponding weldering
The link position of disk will not generate offset, performance is electrically connected between wiring layer and pad again to improve, to improve
The stability and reliability of encapsulating structure.
In addition, the first plastic packaging layer 103 of the formation is also used to fix the metal coupling 102, planarization described first
Capsulation material layer prevents metal coupling 102 from generating and loosens or fall off from pad 101.
First plastic packaging layer 103 of the formation can be also used for protecting the metal coupling 102, prevent metal coupling 102
It is contaminated or damages in the subsequent process.
In one embodiment, the size of material granule is less than the second plastic packaging being subsequently formed in the first plastic packaging layer 103
The size of material granule in layer enables the first plastic packaging layer 103 more preferably to fill between metal coupling 102 with the gap of two sides, makes
The first plastic packaging layer 103 and the contact of the side of metal coupling 102 more closely so that 103 pairs of metal of the first plastic packaging layer
The fixed effect of convex block 102 is more preferable.
With reference to Fig. 6, the first capsulation material layer is planarized, the top surface of the metal coupling 102 is exposed, it is remaining
The first capsulation material layer as the first plastic packaging layer 103, the surface of the first plastic packaging layer 103 and the top of metal coupling 102
Surface flushes.
The first capsulation material layer 103 is planarized using chemical mechanical milling tech.
With reference to Fig. 7, after planarizing the first capsulation material layer 103, the 100 (ginseng of wafer is cut along Cutting Road region
Examine Fig. 6), form several discrete semiconductor chips 160 with the first plastic packaging layer 103.
In other embodiments, referring to FIG. 8, the metal coupling of the formation further includes being located at the metal coupling 102
Top surface or the isolation sacrificial layer 120 that is formed of top and sidewall surfaces；After forming isolation sacrificial layer 120, formation is covered
Cover the first capsulation material layer 123 of the isolation sacrificial layer 120 and 160 functional surfaces of the semiconductor chip.It is flat with reference to Fig. 9
Change the first capsulation material layer 123, expose the surface of the isolation sacrificial layer 120, remaining first capsulation material layer is made
Surface for the first plastic packaging layer 103, the first plastic packaging layer 103 is flushed with the surface that sacrificial layer 120 is isolated on metal coupling.
The wafer is cut, several discrete semiconductor chips are formed after planarizing the first capsulation material layer with reference to Figure 10.
The study found that if the first capsulation material layer 123 formed directly covers the top surface of metal coupling 102, In
Part the first capsulation material layer 123 is removed by planarization (chemical mechanical milling tech) to expose metal coupling 102
Top surface when, during planarization (chemical mechanical milling tech) first capsulation material layer 123, abrasive power is likely to
Part metals convex block 102 is generated to loosen or fall off from pad 101.Thus in the present embodiment, the first plastic packaging material is being formed
Before the bed of material 103, isolation sacrificial layer 120 is formed in the top surface of the metal coupling 102 or top and sidewall surfaces
(a part that the isolation sacrificial layer 120 is metal coupling 102), can pass through chemical mechanical milling tech and subsequent etching
Technique removal part the first capsulation material layer and isolation sacrificial layer 120 that both technique combines are to expose metal coupling, tool
Body, the table of the isolation sacrificial layer is first exposed using chemical mechanical milling tech removal part the first capsulation material layer
Then face, remaining first capsulation material layer remove 102 top surface of metal coupling using etching technics as the first plastic packaging layer
On the isolation sacrificial layer, expose the top surface of metal coupling, thus the top table of metal coupling can not only be exposed
Face, and when the first capsulation material layer described due to use chemical mechanical milling tech removal part, exposure is that isolation is sacrificed
Layer surface, the grinding pad in milling apparatus will not be contacted with metal coupling, because without bringing abrasive power to metal coupling, thus
It preferably prevents from metal coupling 102 from generating to loosen or fall off from pad 101, further increases the wiring layer again being subsequently formed
The precision of link position between corresponding metal coupling, the electricity for further improving again wiring layer and metal coupling 102 connect
Connect performance.
In addition, the formation isolation sacrificial layer 120 can also improve between the first plastic packaging layer 103 and metal coupling 102
Adhesion strength.
In one embodiment, the material of the isolation sacrificial layer 120 is silica, silicon nitride or silicon oxynitride.
With reference to Figure 10, the wafer 100 (referring to Fig. 9) is cut along Cutting Road region, several discrete having is formed and is isolated
The semiconductor chip 160 of sacrificial layer 120 and the first plastic packaging layer 103.
With reference to Figure 11 or Figure 13, support plate 107 is provided；By the first modeling on the functional surfaces of several semiconductor chips 160
Sealing 103 and pad 102 are bonded on support plate 107.
Offer support platform of the support plate 107 as subsequent technique, the support plate 107 can carry for glass support plate, silicon
The support plate of plate or metal support plate, the support plate 107 or other suitable materials.
The first plastic packaging layer 103 and pad 102 on the semiconductor chip 160 are bonded in support plate 107 by an adhesive layer
Surface, the adhesive surface of functional surfaces (or pad 101) towards support plate 107 of the semiconductor chip 160.
There are many available materials of adhesive layer, and in one embodiment, adhesive layer uses UV glue.UV glue is a kind of energy
To the aitiogenic glueing material of the ultraviolet light of special wavelength.UV glue can be divided into according to variation sticky after ultraviolet light
Two kinds, one is UV solidification glue, i.e. photoinitiator in material or photosensitizer produces after absorbing ultraviolet light under ultraviolet irradiation
Liveliness proof free radical or cation cause monomer polymerization, are crosslinked and connect branch chemical reaction, make ultraviolet cured adhesive within the several seconds
Solid-state is converted by liquid, so that the body surface being in contact with it be bonded；Another UV glue without ultraviolet light when irradiating
Viscosity is very high, and the crosslinking chemical bond after ultraviolet light in material is interrupted viscosity is caused to decline to a great extent or disappear.This
In adhesive layer used by UV glue be the latter.It can be formed by film coating process, print adhesive process or plastic roll technique described viscous
Close layer.
In other embodiments, the adhesion-layer materials can also for epoxide-resin glue, polyimides glue, polyethylene glue,
Benzocyclobutene glue or polybenzoxazoles glue.
Several semiconductor chips 160 are uniformly bonded on support plate 107 in ranks arrangement.
With reference to Figure 12 or Figure 13, non-functional surface and the side for coating the semiconductor chip 160 are formed on the support plate 107
Second plastic packaging layer 109 of wall surface.
The second plastic packaging layer 109 is for sealing and fixing the semiconductor chip 160, to be subsequently formed preformed cover
Plate.The second plastic packaging layer 109 also covers 103 sidewall surfaces of 107 surface of support plate and the first plastic packaging layer.
The material of the second plastic packaging layer 109 can be epoxy resin, polyimide resin, benzocyclobutane olefine resin, gather
Benzoxazoles resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene,
In polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol
It is one or more of.
Forming the second plastic packaging layer 109 can be using Shooting Technique (injection molding) or turn modeling technique
(transfer molding) or other suitable techniques.
When forming the second plastic packaging layer 109, the presence of the first plastic packaging layer 103, so that each 160 surface of semiconductor chip
Flat surface is all had, is bonded by the first plastic packaging layer 103 on several discrete semiconductor chips 160 with support plate
When, due to the first plastic packaging layer 103 have flat surface so that all had between each semiconductor chip 160 and support plate compared with
High adhesion strength, to infused when forming the second plastic packaging layer 109 for coating several semiconductor chips 160 on support plate 107
Modeling or turn modeling compression shock when, all semiconductor chips 160 position on support plate will not all generate offset, thus it is subsequent
After removing support plate 107, preformed cover plate is formed, when the back side of preformed cover plate forms the wiring layer again connecting with pad, then is routed
Layer will not generate offset with the link position of corresponding pad, to improve the being electrically connected property between wiring layer and pad again
Can, to improve the stability and reliability of encapsulating structure.
Figure 15 and Figure 16 is referred to reference to Figure 14 or combination, Figure 14 is carried out on the basis of Figure 12, and Figure 15 is on the basis of Figure 13
Upper progress, Figure 16 are carried out on the basis of Figure 15, are removed the support plate 107 (with reference to Figure 12 or Figure 13), are formed preformed cover plate 21,
Expose the pad 103 in 21 back side of preformed cover plate.
By removal adhesive layers such as chemical attack, mechanical stripping, CMP, mechanical lapping, heat bakings, so that 107 quilt of support plate
Removing.
In one embodiment, when not formed isolation sacrificial layer, after removing the support plate, it is convex directly to expose the metal
Block 102.
In another embodiment, when formed be isolated sacrificial layer 120 when, with reference to Figure 15, first remove the support plate, expose every
From 120 surface of sacrificial layer；With reference to Figure 16, using the isolation sacrifice on etching technics removal 102 top surface of metal coupling
Layer 120 (refers to Figure 15), exposes the top surface of metal coupling 102, specifically, the position of the removal isolation sacrificial layer 120
The opening 121 being correspondingly formed in the first plastic packaging layer 103 is set, the opening 121 exposes the top of the metal coupling 102
Surface.The present embodiment first can remove part described first using chemical mechanical milling tech by forming isolation sacrificial layer 120
Capsulation material layer exposes isolation sacrificial layer surface, then using the institute on etching technics removal 102 top surface of metal coupling
Isolation sacrificial layer is stated, exposes the top surface of metal coupling 102, thus passes through aforementioned specific structure and specific technique
In conjunction with the top surface that can not only expose metal coupling, and due to using chemical mechanical milling tech removal part described the
When one plastic packaging plastic packaging layer, exposure is isolation sacrificial layer surface, and the grinding pad in milling apparatus will not be contacted with metal coupling, because
Without bringing abrasive power to metal coupling, loosens or taken off from pad 101 to preferably prevent metal coupling 102 from generating
It falls, further increases the precision of link position between the wiring layer again and corresponding metal coupling being subsequently formed, further increase
Wiring layer and metal coupling 102 are electrically connected performance again.
The etching technics for removing the isolation sacrificial layer 120 is wet etching or dry etching.In one embodiment, work as institute
When the material for stating isolation sacrificial layer 120 is silicon nitride, the isolation sacrificial layer 120 is removed using wet etching, wet etching is adopted
Etching solution is phosphoric acid solution.
With reference to Figure 17 and Figure 18, the external contact connecting with metal coupling 102 is formed at the back side of the preformed cover plate 21
Structure.
The external contact structure includes being routed again of being connect on 21 back side of preformed cover plate with metal coupling 102
Layer 110 and the external contacts 112 being connect on wiring layer 110 again with wiring layer 110 again, each semiconductor chip
Metal coupling 102 on 160 is connected with corresponding external contact structure.The external contacts 112 are soldered ball or described
External contacts 112 also may include metal column and the soldered ball positioned at metal column surface.
In a specific embodiment, the forming process of the wiring layer again 110 and external contacts 112 includes: to shell
After the support plate, wiring layer 110 again are formed on the back side of the preformed cover plate 21；In wiring layer 110 again and preformed cover version
Insulating layer 111 is formed on 21 back side, forms the opening for exposing again 110 part of the surface of wiring layer, institute in the insulating layer 111
Stating 121 material of insulating layer can be with silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass；It is formed in said opening external
Contact 112.
With reference to Figure 19, after forming the external contact structure, further includes: cut the preformed cover plate, form several points
Vertical encapsulating structure 22.
It should be noted that it is outer to form formation in the process and Figure 17-Figure 18 of external contact structure on the basis of Figure 16
The process of portion's contact structures is essentially identical, and details are not described herein.
One embodiment of the invention additionally provides a kind of encapsulating structure, please refers to Figure 12 or Figure 13, comprising:
Support plate 107；
Several semiconductor chips 160 being bonded on the support plate 107, each semiconductor chip 160 include functional surfaces 11
The non-functional surface 12 opposite with functional surfaces 11, has several pads 101 on the functional surfaces 11, on 101 surface of pad
Be formed with metal coupling 102, also there is the first plastic packaging layer 103 on the functional surfaces 11, the surface of the first plastic packaging layer 103 with
The metal coupling top surface flushes, the first plastic packaging layer 103 and pad 101 on the functional surfaces of the semiconductor chip 160
It is bonded on support plate 107；
The non-functional surface of the semiconductor chip 160 and the second plastic packaging of sidewall surfaces are coated on the support plate 107
Layer 109.
In one embodiment, the semiconductor chip 160 is formed by integration making technology, comprising steps of providing brilliant
It is round, several semiconductor chips are formed on the wafer, the semiconductor chip includes functional surfaces, has weldering on the functional surfaces
Disk；Metal coupling is formed on the pad；Form the first capsulation material layer for covering the metal coupling and functional surfaces；It is flat
Change the first capsulation material layer, exposes the surface of the isolation sacrificial layer, remaining first capsulation material layer is as first
The surface of plastic packaging layer, the first plastic packaging layer is flushed with the surface that sacrificial layer is isolated；After planarizing the first capsulation material layer,
The wafer is cut, several discrete semiconductor chips are formed.
In one embodiment, the material of the first capsulation material layer and the second plastic packaging layer 109 is resin, first modeling
The formation process of closure material layer and the second plastic packaging layer 109 is to be molded or turn modeling technique.
In one embodiment, in the first plastic packaging layer 103 size of material granule less than material in the second plastic packaging layer 109
The size of particle.
In one embodiment, Figure 13 is please referred to, the metal coupling 102 further includes the top table positioned at metal coupling 102
The isolation sacrificial layer 120 that face or top and sidewall surfaces are formed, sacrifice is isolated with described in the surface of the first plastic packaging layer 103
The surface of layer 120 flushes.
In one embodiment, the semiconductor chip 160 is formed by integration making technology, comprising steps of providing brilliant
It is round, several semiconductor chips are formed on the wafer, the semiconductor chip includes functional surfaces, has weldering on the functional surfaces
Disk；Metal coupling is formed on the pad；Isolation sacrificial layer is formed on metal coupling；It is formed and covers the isolation sacrificial layer
With the first capsulation material layer of functional surfaces；The first capsulation material layer is planarized, the surface of the isolation sacrificial layer is exposed,
The remaining first capsulation material layer is as the first plastic packaging layer；After planarizing the first capsulation material layer, the crystalline substance is cut
Circle, forms several discrete semiconductor chips.
The material of the isolation sacrificial layer 120 is silica, silicon nitride or silicon oxynitride.
It should be noted that please referring to aforementioned encapsulation knot about other restrictions or description of encapsulating structure in the present embodiment
The corresponding restriction or description of the forming process part of structure, are not repeating in the present embodiment.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (13)
1. a kind of forming method of encapsulating structure characterized by comprising
There is provided several semiconductor chips, each semiconductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces, described
There are several pads on functional surfaces, metal coupling is formed in the bond pad surface, also there is the first plastic packaging on the functional surfaces
Layer, the surface of the first plastic packaging layer is flushed with the metal coupling top surface；
Support plate is provided；
By on the functional surfaces of several semiconductor chips the first plastic packaging layer and pad be bonded on support plate；
The second plastic packaging layer of the non-functional surface and sidewall surfaces that coat the semiconductor chip is formed on the support plate；
The support plate is removed, preformed cover plate is formed, the preformed cover back exposes the pad；
The external contact structure connecting with metal coupling is formed at the back side of the preformed cover plate.
2. the forming method of encapsulating structure as described in claim 1, which is characterized in that the forming process of the semiconductor chip
Are as follows: wafer is provided, is formed with several semiconductor chips on the wafer, the semiconductor chip includes functional surfaces, the function
There is pad on face；Metal coupling is formed on the pad；Form the first plastic packaging for covering the metal coupling and functional surfaces
Material layer；The first capsulation material layer is planarized, the metal coupling top surface, remaining first capsulation material are exposed
Layer is used as the first plastic packaging layer；After planarizing the first capsulation material layer, the wafer is cut, forms several discrete semiconductors
Chip.
3. the forming method of encapsulating structure as claimed in claim 2, which is characterized in that the first capsulation material layer and second
The material of plastic packaging layer is resin, and the formation process of the first capsulation material layer and the second plastic packaging layer is to be molded or turn modeling technique.
4. the forming method of encapsulating structure as claimed in claim 3, which is characterized in that material granule in the first plastic packaging layer
Size less than material granule in the second plastic packaging layer size.
5. the forming method of encapsulating structure as claimed in claim 2, which is characterized in that flat by chemical mechanical milling tech
Change the first capsulation material layer, exposes the metal coupling top surface.
6. the forming method of encapsulating structure as described in claim 1, which is characterized in that the metal coupling further includes being located at gold
The isolation sacrificial layer that the top surface or top and sidewall surfaces for belonging to convex block are formed, the surface of the first plastic packaging layer with it is described
The surface that the surface of isolation sacrificial layer flushes is flushed with the surface that sacrificial layer is isolated.
7. the forming method of encapsulating structure as claimed in claim 6, which is characterized in that the forming process of the semiconductor chip
Are as follows: wafer is provided, is formed with several semiconductor chips on the wafer, the semiconductor chip includes functional surfaces, the function
There is pad on face；Metal coupling is formed on the pad；Isolation sacrificial layer is formed on metal coupling；It is formed described in covering
The first capsulation material layer of sacrificial layer and functional surfaces is isolated；The first capsulation material layer is planarized, it is sacrificial to expose the isolation
The surface of domestic animal layer, remaining first capsulation material layer as the first plastic packaging layer, the surface of the first plastic packaging layer with sacrifice is isolated
The surface of layer flushes；After planarizing the first capsulation material layer, the wafer is cut, forms several discrete semiconductor cores
Piece.
8. the forming method of encapsulating structure as claimed in claim 7, which is characterized in that after removing the support plate, described in removal
Sacrificial layer is isolated, so that the preformed cover back exposes the pad.
9. the forming method of encapsulating structure as claimed in claim 8, which is characterized in that the etching technics be wet etching or
Dry etching.
10. the forming method of encapsulating structure as claimed in claim 6, which is characterized in that it is described isolation sacrificial layer material be
Silica, silicon nitride or silicon oxynitride.
11. the forming method of encapsulating structure as described in claim 1, which is characterized in that the external contact structure includes position
It is connect in the wiring layer again being connect on the preformed cover version back side with metal coupling and on wiring layer again with wiring layer again
External contacts.
12. the forming method of encapsulating structure as claimed in claim 11, which is characterized in that the wiring layer again and external contact
The forming process of part includes: to form wiring layer again on the back side of the preformed cover plate after removing the support plate；It is being routed again
Insulating layer is formed on the back side of layer and preformed cover version, forms the opening for exposing wiring layer part of the surface again in the insulating layer；
External contacts are formed in said opening.
13. the forming method of encapsulating structure as described in claim 1, which is characterized in that the external contact structure is being formed,
Further include: the preformed cover plate is cut, several discrete encapsulating structures are formed.
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| CN201910675804.4A CN110504174A (en) | 2019-07-25 | 2019-07-25 | The forming method of encapsulating structure |
| US17/629,040 US20220278075A1 (en) | 2019-07-24 | 2020-07-17 | Packaging structure and formation method thereof |
| PCT/CN2020/102767 WO2021013097A1 (en) | 2019-07-25 | 2020-07-17 | Packaging structure and formation method thereof |
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