JP2001077142A - Semiconductor device and manufacture of it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain cracks on the interface between a solder and a bump electrode in a semiconductor device. SOLUTION: A bump electrode enclosed with a sealing film 7 is composed of a lower electrode 6a consisting of copper and an upper electrode 6b consisting of solder. As a result, the interface between the lower electrode 6a and the upper electrode 6b is located inside the surface of the sealing film 7. Accordingly, the stress concentration does not occur on the interface and the production of cracks can be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bump electrode and a method for manufacturing the same.

[0002]

2. Description of the Related Art For example, when manufacturing a semiconductor device called a CSP (Chip Size Package), as an example, first, as shown in FIG. 18, a connection pad 2 is formed on an upper surface of a silicon substrate (semiconductor substrate) 1 in a wafer state. Then, an insulating film 3 is formed on a portion of the upper surface of the connection pad 2 other than the central portion, and an upper surface of the connection film 2 is exposed from an upper surface of the connection pad 2 exposed through an opening 4 formed in the insulating film 3. A wire 5 is formed over a predetermined location, and a wire 5 in which a protruding electrode 6 made of metal is formed on the upper surface of the tip of the wire 5 is prepared.

[0003] Next, as shown in FIG. 19, a sealing film 7 made of epoxy resin is formed on the entire upper surface of the silicon substrate 1 including the protruding electrodes 6 so as to be slightly thicker than the height of the protruding electrodes 6 by a dispenser method or the like. It forms so that it may become. Therefore,
In this state, the upper surface of the bump electrode 6 is covered with the sealing film 7. Next, the upper surface of the sealing film 7 is appropriately polished to expose the upper surface of the bump electrode 6 as shown in FIG. Next, through a dicing step, individual semiconductor devices 10 are obtained as shown in FIG.

FIG. 22 shows a semiconductor device 1 shown in FIG.
FIG. 2 is a cross-sectional view illustrating an example of a state in which 0 is mounted on a circuit board 11. In this case, the lower end surface of the protruding electrode 6 of the semiconductor device 10 is connected to the connection terminal 12 provided at a predetermined position on the upper surface of the circuit board 11 by solder (paste) previously provided on the connection terminal 12 by a screen printing method. 13).

[0005]

In the conventional semiconductor device 10 described above, the exposed surface of the protruding electrode 6 is flush with the surface of the sealing film 7. Stress concentration will occur at the interface. As a result, when a temperature cycle test or the like is performed after the semiconductor device 10 is mounted on the circuit board 11, the protrusion due to the stress generated due to the difference in thermal expansion coefficient between the silicon substrate 1 and the circuit board 11 causes There is a problem that a crack may be generated at the interface between the electrode 6 and the solder 13. An object of the present invention is to make it difficult for cracks to be generated at an interface between a bump electrode and solder.

[0006]

According to the present invention, there is provided a semiconductor device in which a sealing film is formed on the semiconductor substrate in a region other than the protruding electrode formed on the semiconductor substrate, wherein the protruding electrode includes a lower electrode and the lower electrode. An upper electrode made of a metal having a lower melting point than the lower electrode, wherein an upper surface of the lower electrode is lower than an upper surface of the sealing film. According to the invention,
Since the upper surface of the lower electrode is lower than the upper surface of the sealing film, the interface between the lower electrode and the upper electrode is located inside the surface of the sealing film, so that stress concentration occurs at the interface. Therefore, it is possible to prevent cracks from being generated at the interface.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS. 1 to 7 show respective manufacturing steps of a semiconductor device according to a first embodiment of the present invention. Therefore, the structure of the semiconductor device according to the present embodiment will be described together with its manufacturing method with reference to these drawings in order. First, as shown in FIG. 1, a connection pad 2 is formed on an upper surface of a silicon substrate (semiconductor substrate) 1 in a wafer state, and an insulating film 3 made of silicon oxide or the like is formed on a portion of the upper surface except for the center of the connection pad 2 Is formed, and a wiring forming layer 5A made of copper, aluminum, or the like is formed on the entire upper surface of the insulating film 3 including the upper surface of the connection pad 2 exposed through the opening 4 formed in the insulating film 3. Prepare

Next, as shown in FIG. 2, a plating resist layer 21 is formed. In this case, an opening 22 is formed in a portion of the plating resist layer 21 corresponding to the bump electrode formation region. Next, the lower electrode 6a is formed on the upper surface of the wiring forming layer 5A in the opening 22 of the plating resist layer 21 by performing copper electrolytic plating using the wiring forming layer 5A as a plating current path. Next, solder (metal having a lower melting point than lower electrode 6a) using wiring forming layer 5A as a plating current path.
By performing electrolytic plating of the plating resist layer 21
The upper electrode 6b is formed on the upper surface of the lower electrode 6a in the opening 22 of FIG. Before forming the upper electrode 6b, the upper surface of the lower electrode 6a may be subjected to a surface treatment by electrolytic plating nickel / gold, nickel / solder, nickel / tin, or the like. This surface treatment layer has a function as a diffusion preventing layer. Next, the plating resist layer 2
1 is peeled off.

[0009] Next, as shown in FIG.
A resist layer 23 is formed at a predetermined position on the upper surface of A. Next, unnecessary portions of the wiring forming layer 5A are removed by etching using the resist layer 23 and the electrodes 6a and 6b as a mask, and as shown in FIG. 4, wirings are formed below the resist layer 23 and the electrodes 6a and 6b. 5 are formed. That is, in this state, the wiring 5 is formed from the upper surface of the connection pad 2 exposed through the opening 4 formed in the insulating film 3 to a predetermined portion of the upper surface of the insulating film 3, and the leading end of the wiring 5 is formed. A lower electrode 6a and an upper electrode 6b are formed on the upper surface. Next, the resist layer 23 is peeled off.

Next, as shown in FIG. 5, a sealing film 7 made of epoxy resin is formed on the entire upper surface of the silicon substrate 1 including the lower electrode 6a and the upper electrode 6b by a dispenser method, a screen printing method, a transfer molding method or the like. The thickness is formed to be slightly thicker than the total height of both electrodes 6a and 6b. Therefore, in this state, the upper surface of the upper electrode 6b is covered with the sealing film 7. Next, by appropriately polishing the upper surface side of the sealing film 7, as shown in FIG.
The upper surface of the upper electrode 6b is exposed. In this state, the upper surface of the lower electrode 6a is lower than the upper surface of the sealing film 7. Next, through a dicing step, individual semiconductor devices 10 are obtained as shown in FIG.

FIG. 8 is a sectional view showing an example of a state in which the semiconductor device 10 shown in FIG. 7 is mounted on a circuit board 11. In this case, the upper electrode 6b of the semiconductor device 10
Is connected to a connection terminal 12 provided at a predetermined position on the upper surface of the circuit board 11 via a solder (paste) 13 previously provided on the connection terminal 12 by a screen printing method or the like. . By the way, since the upper electrode 6b is formed of solder, the upper electrode 6b made of the solder and the solder 13 are melted and then solidified integrally.

As described above, since the upper electrode 6b made of solder and the solder 13 are melted and solidified integrally, the interface between the lower electrode 6a made of copper and the solders 6b and 13 is Since it is located inside the surface, stress concentration does not occur at the interface, so that cracks are less likely to occur at the interface. That is, stress concentration occurs on a surface along the surface of the sealing film 7, but since the upper electrode 6b made of solder and the solder 13 are melted with each other and then solidified integrally, Cracks do not occur even if stress concentration occurs in

In the case of the conventional semiconductor device 10 shown in FIG. 21, since the upper surface of the bump electrode 6 made of, for example, copper is exposed, it is necessary to perform a surface treatment for preventing oxidation of the exposed surface. There is. On the other hand, in the case of the semiconductor device 10 of this embodiment shown in FIG.
Since the upper surface of a is not exposed and the upper surface of the upper electrode 6b made of solder is exposed, it is not necessary to perform the above-described surface treatment for preventing oxidation.

(Second Embodiment) In the first embodiment,
As shown in FIG. 2, the upper electrode 6b is
Although the case in which the upper electrode 6b is formed only in the opening 22 of the plating resist layer 21 is described in the second embodiment of the present invention shown in FIG. It may be formed in a shape. In this case, as shown in FIG. 10, after forming the wiring 5,
Although the sealing film 7 is formed by a dispenser method, the lower surface of the umbrella portion of the upper electrode 6b functions as a dam, so that the sealing film 7 is formed on the silicon substrate 1 in a region excluding the electrodes 6a and 6b. Thus, it is formed under the umbrella portion of the upper electrode 6b. In this case, the upper electrode 6b
Since the umbrella portion is projected onto the sealing film 7, the polishing process is not performed. Further, referring to FIG. 8, it is not necessary to provide the solder 13 on the connection terminals 12 of the circuit board 11 in advance.

(Third Embodiment) Next, a structure of a semiconductor device according to a third embodiment of the present invention will be described together with a method of manufacturing the same. First, the one shown in FIG. 20 is prepared.
However, in this case, the projecting electrode 6 is hereinafter referred to as a lower electrode 6a.
That. Next, as shown in FIG. 11, the upper surface of the lower electrode 6a is removed by etching using the sealing film 7 as a mask. In this case, the etching solution may be Enplate A
A solution prepared by dissolving the D-458 ionic compound (100%) in pure water at 30 g / L is used. The etching depth is 2
To about 10 μm. Next, as shown in FIG. 12, an upper electrode 6b made of a solder ball or a solder paste by screen printing or the like is provided on the upper surface of the lower electrode 6a with a sealing film 7.
It is formed so as to protrude upward. Therefore, also in this case, referring to FIG. 8, it is not necessary to provide the solder 13 on the connection terminals 12 of the circuit board 11 in advance. Before forming the upper electrode 6b, the upper surface of the lower electrode 6a may be subjected to a surface treatment with nickel / gold, nickel / solder, nickel / tin or the like.

(Fourth Embodiment) Next, the structure of a semiconductor device according to a fourth embodiment of the present invention will be described together with a method of manufacturing the same. First, the one shown in FIG. 20 is prepared.
However, also in this case, the projecting electrode 6 is hereinafter referred to as the lower electrode 6.
called a. Next, as shown in FIG.
To form In this case, the lower electrode 6a of the resist layer 24
An opening 25 slightly smaller than the upper surface of the lower electrode 6a is formed in a portion corresponding to the center of the upper surface of the lower electrode 6a. Next, as shown in FIG. 14, the concave portion 8 is formed in the central portion of the upper surface of the lower electrode 6a by removing the central portion of the upper surface of the lower electrode 6a by etching using the resist layer 24 as a mask. Next, the resist layer 24 is peeled off. Next, FIG.
As shown in FIG. 7, an upper electrode 6b made of a solder ball or a solder paste by screen printing or the like is formed on the upper surface of the lower electrode 6a so as to protrude above the sealing film 7. Therefore, also in this case, referring to FIG. 8, it is not necessary to provide the solder 13 on the connection terminals 12 of the circuit board 11 in advance. In this case, the presence of the concave portion 8
Since the bonding area between the lower electrode 6a and the upper electrode 6b increases, the bonding strength can be increased by dispersing the stress. Before forming the upper electrode 6b, the upper surface of the lower electrode 6a may be subjected to a surface treatment with nickel / gold, nickel / solder, nickel / tin or the like.
Further, the resist layer 24 may be left without being stripped.

(Fifth Embodiment) In each of the above embodiments, the case where the protruding electrode is formed by the lower electrode 6a made of copper and the upper electrode 6b made of solder has been described. The fifth embodiment of the present invention shown in FIG. As in the embodiment, the protruding electrode 6 may be formed only by solder. Then, as shown in FIG.
Is connected to the connection terminal 12 of the circuit board 11 via the solder 13 provided on the connection terminal 12 in advance. In this case, since the protruding electrode 6 is formed of solder, the protruding electrode 6 made of the solder and the solder 13 are melted and then solidified integrally. Therefore, in this case, even if the stress concentration occurs on the surface along the surface of the sealing film 7, on the surface, the protruding electrode 6 made of solder and the solder 13 melt and then solidify integrally. Cracks do not occur.

(Other Embodiments) In the above embodiments, the case where the lower electrode 6a is formed by electrolytic plating of copper has been described. However, the lower electrode 6a may be formed by electrolytic plating of nickel, gold, or the like. Also, for example, FIG.
Alternatively, in the state shown in FIG. 7, an external electrode made of a solder ball or a solder paste by screen printing or the like may be formed on the upper electrode 6b. Also,
In the state shown in FIG. 20 or FIG. 21, an external electrode (second layer) made of a solder ball or a solder paste by screen printing or the like may be formed on the bump electrode (first layer) 6. In this case, FIG.
Referring to FIG. 2, it is not necessary to provide the solder 13 on the connection terminals 12 of the circuit board 11 in advance.

[0019]

As described above, according to the present invention, since the upper surface of the lower electrode is lower than the upper surface of the sealing film, the interface between the lower electrode and the upper electrode is higher than the surface of the sealing film. Are also located on the inside, so that stress concentration does not occur at the interface, and cracks are less likely to occur at the interface.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a device initially prepared for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the manufacturing process following FIG. 1;

FIG. 3 is a sectional view of the manufacturing process following FIG. 2;

FIG. 4 is a sectional view of the manufacturing process following FIG. 3;

FIG. 5 is a sectional view of the manufacturing process following FIG. 4;

FIG. 6 is a sectional view of the manufacturing process following FIG. 5;

FIG. 7 is a sectional view of the manufacturing process following FIG. 6;

8 is a cross-sectional view illustrating an example of a state where the semiconductor device illustrated in FIG. 7 is mounted on a circuit board.

FIG. 9 is a cross-sectional view of a predetermined manufacturing step in manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a sectional view of the manufacturing process following FIG. 9;

FIG. 11 is a cross-sectional view of a predetermined manufacturing step in manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a sectional view of the manufacturing process following FIG. 11;

FIG. 13 is a cross-sectional view of a predetermined manufacturing step in manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a sectional view of the manufacturing process following FIG. 13;

FIG. 15 is a sectional view of the manufacturing process continued from FIG. 14;

FIG. 16 is a sectional view illustrating a semiconductor device according to a fifth embodiment of the present invention;

17 is a cross-sectional view illustrating an example of a state where the semiconductor device illustrated in FIG. 16 is mounted on a circuit board.

FIG. 18 is a cross-sectional view of a device initially prepared for manufacturing an example of a conventional semiconductor device.

FIG. 19 is a sectional view of the manufacturing process continued from FIG. 18;

FIG. 20 is a sectional view of the manufacturing process continued from FIG. 19;

FIG. 21 is a sectional view of the manufacturing process continued from FIG. 20;

22 is a cross-sectional view illustrating an example of a state where the semiconductor device illustrated in FIG. 21 is mounted on a circuit board.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 connection pad 3 insulating film 5 wiring 6a lower electrode 6b upper electrode 7 sealing film 10 semiconductor device 11 circuit board 12 connection terminal 13 solder

Claims (10)

[Claims] 1. A semiconductor device in which a sealing film is formed on a semiconductor substrate in a region other than a projection electrode formed on a semiconductor substrate, wherein the projection electrode includes a lower electrode and a metal having a lower melting point than the lower electrode. And an upper electrode comprising: a lower electrode, wherein an upper surface of the lower electrode is lower than an upper surface of the sealing film. 2. The semiconductor device according to claim 1, wherein an upper surface of said upper electrode and an upper surface of said sealing film are flush with each other. 3. The semiconductor device according to claim 1, wherein an upper portion of said upper electrode protrudes from an upper surface of said sealing film. 4. The semiconductor device according to claim 3, wherein the upper electrode has a mushroom shape, and an umbrella portion protrudes from an upper surface of the sealing film. 5. The semiconductor device according to claim 3, wherein a recess is formed on an upper surface of the lower electrode. 6. A semiconductor device in which a sealing film is formed on the semiconductor substrate in a region excluding a bump electrode formed on a semiconductor substrate, wherein the bump electrode has a first surface flush with an upper surface of the sealing film. A semiconductor device comprising a layer and a second layer formed on the first layer so as to protrude from the sealing film, wherein the first layer and the second layer are made of a low melting point metal. 7. A protruding electrode comprising a lower electrode and an upper electrode made of a metal having a lower melting point than the lower electrode is formed on a semiconductor substrate, and a sealing film is formed on the semiconductor substrate including the protruding electrode. And polishing the upper surface of the sealing film so that the upper surface of the upper electrode is flush with the upper surface of the sealing film. 8. A semiconductor device comprising a first substrate made of a low-melting metal on a semiconductor substrate.
A sealing film is formed on the semiconductor substrate in a region excluding the first layer so as to be flush with an upper surface of the first layer, and a sealing film is formed on the upper surface of the first layer from the sealing film. A method for manufacturing a semiconductor device, comprising: forming a second layer made of a protruding low melting point metal. 9. An upper surface of the lower electrode by forming a lower electrode on the semiconductor substrate, forming a sealing film on the semiconductor substrate including the lower electrode, and polishing an upper surface of the sealing film. And exposing the exposed upper surface of the lower electrode to remove it, thereby forming an upper electrode made of a low melting point metal on the lower electrode. 10. The lower electrode by forming a columnar lower electrode on a semiconductor substrate, forming a sealing film on the semiconductor substrate including the lower electrode, and polishing an upper surface of the sealing film. Forming a concave portion on the exposed upper surface of the lower electrode, and forming an upper electrode made of a low melting point metal on the lower electrode.