JP2000228420A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JP2000228420A
JP2000228420A JP11029032A JP2903299A JP2000228420A JP 2000228420 A JP2000228420 A JP 2000228420A JP 11029032 A JP11029032 A JP 11029032A JP 2903299 A JP2903299 A JP 2903299A JP 2000228420 A JP2000228420 A JP 2000228420A
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Prior art keywords
forming
electrode
layer
upper surface
plating
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JP4131595B2 (en
Inventor
Yukihiro Takao
幸弘 高尾
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Sanyo Electric Co Ltd
三洋電機株式会社
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Priority to JP02903299A priority Critical patent/JP4131595B2/en
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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To improve reliability when a chip-size package is mounted. SOLUTION: An upper electrode 12 having an upper surface of an area larger than the upper surface of a metal post 9 is provided on the upper surface of the metal post 9, and a solder ball 15 is mounted thereon. Consequently, the contact area between the solder ball 15 and the metal post 9 can be made large. Therefore, the strength against the shearing stress can be improved.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】 本発明は、半導体装置及びその製造方法に関する。 The present invention relates to relates to a semiconductor device and a manufacturing method thereof. さらに、詳しく言えば、チップサイズパッケージの信頼性を向上させる技術に関する。 Furthermore, speaking in detail, a technique for improving the reliability of the chip-size package.
チップサイズパッケージ(Chip Size Package)は、C Chip size package (Chip Size Package) is, C
SPとも呼ばれ、チップサイズと同等か、わずかに大きいパッケージの総称であり、高密度実装を目的としたパッケージである。 Also referred to as SP, chip size and equal to or, it is a generic term for a slightly larger package, a package for the purpose of high-density mounting. 本発明は、チップサイズパッケージの信頼性を向上させる技術に関する。 The present invention relates to a technique for improving the reliability of the chip-size package.

【0002】 [0002]

【従来の技術】従来、この分野では、一般にBGA(Ba Conventionally, in this field, generally BGA (Ba
ll Grid Array)と呼ばれ、面状に配列された複数のハンダボールを持つ構造、ファインピッチBGAと呼ばれ、BGAのボールピッチをさらに狭ピッチにしてPK ll called Grid Array), a structure having a plurality of solder balls arranged in a planar, called fine pitch BGA, and further narrow pitch ball pitch BGA PK
G外形がチップサイズに近くなった構造等が知られている。 G outline is known like structure is close to the chip size.

【0003】また、最近では、「日経マイクロデバイス」1998年8月号 44頁〜71頁に記載されたウエハーCSPがある。 [0003] In addition, in recent years, there is a wafer CSP, which is described in "Nikkei Microdevices" August 44 pp to 71, 1998. このウエハーCSPは、基本的には、チップのダイシング前に配線やアレイ状のパッドをウエハープロセス(前工程)で作り込むCSPである。 The wafer CSP is basically a CSP to fabricate the chip pads of the wiring and an array before dicing in a wafer process (pre-process).
この技術によって、ウエハープロセスとパッケージ・プロセス(後工程)が一体化され、パッケージ・コストが大幅に低減できるようになることが期待されている。 This technique, wafer processing and packaging process (post-process) are integrated, the package cost is expected to be able to significantly reduce.

【0004】ウエーハCSPの種類には、封止樹脂型と再配線型がある。 [0004] The types of wafer CSP, there is a sealing resin type and rewiring type. 封止樹脂型は、従来のパッケージと同様に表面を封止樹脂で覆った構造であり、チップ表面の配線層上に柱状の端子(メタル・ポスト)を形成し、その周囲を封止樹脂で固める構造である。 Sealing resin mold is a surface similar to the conventional package structure covered with a sealing resin to form a columnar pin (metal posts) on the wiring layer of the chip surface, the periphery thereof with a sealing resin it is a structure to consolidate. パッケージをプリント基板に搭載すると、プリント基板との熱膨張差によって発生した応力がメタル・ポストに集中する。 When mounting the package on a printed circuit board, the stress generated by the difference in thermal expansion between the printed circuit board is concentrated on the metal post. 一般に、このメタルポストを長くするほど応力が分散されることが知られている。 In general, it stresses the longer the metal post has been known to be distributed.

【0005】一方、再配線型は、図11に示すように、 On the other hand, the rewiring type, as shown in FIG. 11,
封止樹脂を使わず、再配線を形成した構造である。 Without a sealing resin is formed a structure rewiring. チップ51の表面にAl電極52、配線層53、絶縁層54 Al electrode 52 on the surface of the chip 51, the wiring layer 53, insulating layer 54
が積層され、配線層53上にはメタル・ポスト55が形成され、その上に半田バンプ56(半田ボールとも呼ばれる)が形成されている。 There are laminated, on the wiring layer 53 is formed the metal posts 55, the solder on bump 56 (also referred to as solder balls) are formed thereof. 配線層53は、半田バンプ5 Wiring layer 53, the solder bump 5
6をチップ上に所定のアレイ状に配置するための再配線として用いられる。 6 is used as the rewiring for arranging a predetermined array on the chip.

【0006】封止樹脂型は、メタル・ポストを100μ [0006] The sealing resin type, 100μ a metal post
m程度と長くし、これを封止樹脂で補強することにより、高い信頼性が得られる。 Long and about m, the by reinforced by a sealing resin which high reliability is obtained. しかしながら、封止樹脂を形成するプロセスは、後工程において金型を用いて実施する必要があり、プロセスが複雑になる。 However, the process of forming the sealing resin should be carried out using a mold in a subsequent step, the process becomes complicated. 一方、再配線型では、プロセスは比較的単純であり、しかも殆どの工程をウエーハプロセスで実施できる利点がある。 On the other hand, in the rewiring type, the process is relatively simple, yet there is an advantage capable of performing most of the steps in the wafer process. しかし、なんらかの方法で応力を緩和し信頼性を高めることが必要とされている。 However, there is a need to increase the reliability and reduce stress in some way.

【0007】 [0007]

【発明が解決しようとする課題】図12は、上記のようなチップサイズパッケージ57をプリント基板上に実装した場合の断面図を示している。 12 [SUMMARY OF THE INVENTION] shows a cross-sectional view of a case of mounting a chip size package 57 as described above on a printed circuit board. 半田ボール56は、プリント基板61上に配線された銅電極60上に当接される。 The solder balls 56 are in contact on the copper electrode 60 that is wired on the printed circuit board 61. しかしながら、プリント基板とチップサイズパッケージ57の熱膨張係数に差があるために、実装状態で温度サイクル試験を行うと、半田ボール56が破断することがある。 However, because of the difference in the thermal expansion coefficient of the printed circuit board and the chip size package 57, when a temperature cycle test in the mounted condition, there is the solder ball 56 is broken. 特に、半田バンプ56とメタルポスト55の界面には大きなせん断応力が生じることがわかっている。 In particular, it has been found that a large shear stress occurs at the interface between the solder bump 56 and the metal post 55.

【0008】本発明は、上記の課題に鑑みて為されたものであり、チップサイズパッケージの応力耐性を向上し、実装時の信頼性を高めることを目的としている。 [0008] The present invention has been made in view of the above problems, and aims to improve the stress tolerance of a chip size package, improving the reliability of mounting.

【0009】 [0009]

【課題を解決するための手段】本発明の半導体装置は、 The semiconductor device of the present invention According to an aspect of the
半導体基板上に形成された金属電極パッドと、この金属電極パッドに接続され前記半導体基板の表面に延在する配線層と、この配線層を含む半導体基板表面を被覆する絶縁層と、この絶縁層に形成された開口部と、この開口部に形成され前記配線層と接続された柱状端子と、この柱状端子の上面に設けられた上部電極と、この上部電極上に搭載された半田ボールとを有し、前記上部電極の上面の面積を前記柱状端子の上面の面積よりも大きくしたことを特徴としている。 A metal electrode pad formed on a semiconductor substrate, a wiring layer this is connected to the metal electrode pad extending to the surface of the semiconductor substrate, an insulating layer covering the semiconductor substrate surface including the wiring layer, the insulating layer an opening formed in a columnar terminal formed connected to the wiring layer in the opening, and an upper electrode provided on the upper surface of the columnar pin and a solder ball mounted on the upper electrode a, it is characterized in that the area of ​​the upper surface of the upper electrode is larger than the area of ​​the upper surface of the pole terminals.

【0010】柱状端子と半田ボールとの界面のせん断応力に対する強度は、これらの接触面積に比例する。 [0010] strength against shear stress at the interface between the columnar pin and the solder ball is proportional to these contact areas. したがって、この柱状端子に上面の面積の大きな上部電極を設け、この上部電極上に半田ボールを搭載することにより、接触面積が増加でき、せん断応力に対する強度を向上することができる。 Therefore, a large upper electrode area of ​​the upper surface of this columnar terminal is provided, by mounting the solder balls on the upper electrode, the contact area can be increased, it is possible to improve the strength against shear stress.

【0011】また、配線層の微細化に伴いメタルポストは細くなる傾向にあるので、従来例のメタルポストでは、柱状端子と半田ボールとの接触面積が減少してしまうが、本発明によれば、メタルポスト自体は細くなっても、上面の面積の大きな上部電極を具備しているので接触面積を十分確保することができる。 Further, since the metal post with the miniaturization of the wiring layer tends to be thinner, the metal posts of the prior art, although the contact area between the columnar pin and the solder ball is reduced, according to the present invention even thinner the metal post itself, the contact area because it includes a large upper electrode of the area of ​​the upper surface can be sufficiently secured.

【0012】 [0012]

【発明の実施の形態】次に、本発明の実施形態について、図1乃至図10を参照しながら説明する。 DETAILED DESCRIPTION OF THE INVENTION Next, embodiments of the present invention will be described with reference to FIGS. 1-10.

【0013】まず、図1に示すように、Al電極パッド2を有するLSIが形成された半導体基板1(ウエーハ)を準備し、半導体基板1の表面をSiN膜などのパッシベーション膜3で被覆する。 [0013] First, as shown in FIG. 1, to prepare a semiconductor substrate 1 on which an LSI is formed (wafer) having the Al electrode pad 2, the surface of the semiconductor substrate 1 is coated with a passivation film 3, such as SiN film. Al電極パッド2はL Al electrode pad 2 is L
SIの外部接続用のパッドである。 SI is a pad for external connection.

【0014】次に、図2に示すように、平坦化のためにポリイミド膜4を全面に形成する。 [0014] Next, as shown in FIG. 2, to form a polyimide film 4 on the entire surface for planarization. そして、Al電極パッド2上のパッシベーション膜3及びポリイミド膜4をエッチングによって取り除く。 Then, remove the passivation film 3 and the polyimide film 4 on the Al electrode pads 2 by etching.

【0015】次に、図3に示すように、Cu層から成る第1のメッキ用電極層5(シード層とも呼ばれる)をスパッタにより形成する。 [0015] Next, as shown in FIG. 3, (also referred to as a seed layer) a first plating electrode layer 5 made of Cu layer is formed by sputtering.

【0016】次に、Al電極パッド2に接続する配線層を形成する。 Next, a wiring layer connected to the Al electrode pad 2. この配線層は機械的強度を確保するために5μm程度に厚く形成する必要があり、メッキ法を用いて形成するのが適当である。 The wiring layer has to be formed thick to about 5μm in order to ensure the mechanical strength, it is appropriate to form by plating. 図4に示すように、第1のメッキ用電極層5上に第1のホトレジストパターン層6 As shown in FIG. 4, the first photoresist pattern layer on the first plating electrode layer 5 6
を形成し、図5に示すように、電解メッキ法により、第1のホトレジストパターン層6の形成されていない領域にCu層から成る配線層7を形成する。 Forming a, as shown in FIG. 5, the electrolytic plating method to form a wiring layer 7 made of Cu layer in a region not formed with the first photoresist pattern layer 6. この後、第1のホトレジストパターン層6は除去する。 Thereafter, the first photoresist pattern layer 6 is removed.

【0017】次に、図6に示すように、配線層7上のメタルポスト形成領域に開口部を有する第2のホトレジストパターン層8を形成する。 [0017] Next, as shown in FIG. 6, to form a second photoresist pattern layer 8 having an opening in the metal post forming region on the wiring layer 7. そして、電解メッキ法により、Cu層から成る柱状端子としてメタルポスト9をこの開口部に形成する。 Then, an electroplating method to form a metal post 9 in the opening as a pole terminals of Cu layer.

【0018】次に、図7に示すように、全面にCu層から成る第2のメッキ用電極層10を形成する。 Next, as shown in FIG. 7, a second plating electrode layer 10 made of Cu layer on the entire surface. そして、 And,
第2のメッキ用電極層10上に第3のホトレジストパターン層11を形成する。 On the second plating electrode layer 10 to form a third photoresist pattern layer 11. 第3のホトレジストパターン1 The third photoresist pattern 1
1は、メタルポスト9上に開口部を有する。 1 has an opening on the metal post 9. この開口部は、メタルポスト9の上面部を囲み、それよりも広がって開口されている。 This opening surrounds the upper surface portion of the metal posts 9, are opened wider than it.

【0019】そして、電解メッキ法により、この開口部にCu層から成る上部電極12を形成する。 [0019] Then, an electroplating method to form the upper electrode 12 made of Cu layer in the opening. 上部電極1 Upper electrode 1
2の上面には、さらにNi層/Au層から成るバリア層13が形成される。 The second upper surface, the barrier layer 13 is formed further made of Ni layer / Au layer. なお、このNi層/Au層から成るバリア層10は、樹脂封止後、メタルポスト9の上面を露出し、無電解メッキによって形成してもよい。 The barrier layer 10 made of the Ni layer / Au layer, after resin sealing, to expose the upper surface of the metal posts 9 may be formed by electroless plating.

【0020】次に、図8に示すように、第2及び第3のホトレジストパターン8、11と第2のメッキ用電極層10を、レジスト剥離液を用いて除去する。 Next, as shown in FIG. 8, the second and third photoresist pattern 8, 11 and the second plating electrode layer 10 is removed using a resist stripping solution. さらに、第1のメッキ用電極層5について、例えば硝酸と酢酸の混合液を用いて配線層7の下にある部分を除き除去する。 Furthermore, the first plating electrode layer 5, for example, except for removing the underlying portions of the wiring layer 7 using a mixture of nitric acid and acetic acid.

【0021】この後は、ポリイミド層またはモールド樹脂層から成る絶縁層14によって上記のように形成した構造体を封止する。 [0021] Thereafter, to seal the structure formed as described above by the insulating layer 14 of polyimide layer or the mold resin layer. 少なくとも上部電極12の上面については、絶縁層14を研磨するなどして露出されており、この露出した面に半田ボール15を真空吸着法などの公知の方法を用いて搭載、圧着する。 For at least the upper surface of the upper electrode 12 are exposed, such as by polishing the insulating layer 14, equipped with solder balls 15 on the exposed surface using a known method such as vacuum adsorption method, crimping.

【0022】このようにして形成された半導体装置は、 [0022] Such a semiconductor device formed by the,
メタルポスト9の上面よりも大きな上面の面積を有する上部電極12を有している。 It has an upper electrode 12 having an area larger upper surface than the top surface of the metal posts 9. 図10は、メタルポストと半田ボールの部分を従来例と比較して示した斜視図である。 Figure 10 is a perspective view showing a portion of the metal posts and the solder balls as compared with the prior art. この図からも明らかなように、本発明では、半田ボール15とメタルポスト9との接触面積S'が従来例の接触面積Sに比して大きくできる。 As is apparent from this figure, in the present invention, the contact area between the solder balls 15 and the metal post 9 S 'can be larger than the contact area S of the conventional example. このように、上部電極12形成用のレジストマスクの寸法の選択により、せん断応力に対する強度を適正化することができる。 Thus, it is possible by the selection of the size of the resist mask for an upper electrode 12 formed, optimizing the strength against shear stress.

【0023】 [0023]

【発明の効果】本発明によれば、柱状端子と半田ボールとの接触面積が増加でき、せん断応力に対する強度を向上し、チップサイズパッケージの実装時における信頼性を高めることができる。 According to the present invention, it is possible to be increased contact area between the columnar pin and the solder ball, to improve the strength against shear stress, enhance the reliability during mounting of the chip-size package.

【0024】また、本発明によれば、半導体装置の微細化によってメタルポスト自体は細くなっても、上面の面積の大きな上部電極を具備しているので接触面積を十分確保することができる利点がある。 Further, according to the present invention, even thinner the metal post itself miniaturization of the semiconductor device, the advantage of being able to secure a sufficient contact area because comprises a large upper electrode area of ​​the upper surface is there.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施形態に係る半導体装置及びその製造方法を示す第1の断面図である。 1 is a first sectional view showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図2】本発明の実施形態に係る半導体装置及びその製造方法を示す第8の断面図である。 2 is a eighth cross-sectional view of showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図3】本発明の実施形態に係る半導体装置及びその製造方法を示す第3の断面図である。 3 is a third sectional view showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図4】本発明の実施形態に係る半導体装置及びその製造方法を示す第4の断面図である。 4 is a fourth sectional view showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図5】本発明の実施形態に係る半導体装置及びその製造方法を示す第5の断面図である。 5 is a fifth cross-sectional view showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図6】本発明の実施形態に係る半導体装置及びその製造方法を示す第6の断面図である。 6 is a sixth cross sectional view of showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図7】本発明の実施形態に係る半導体装置及びその製造方法を示す第7の断面図である。 7 is a seventh cross-sectional view of showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図8】本発明の実施形態に係る半導体装置及びその製造方法を示す第8の断面図である。 8 is a eighth cross-sectional view of showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図9】本発明の実施形態に係る半導体装置及びその製造方法を示す第9の断面図である。 9 is a ninth sectional view of showing a semiconductor device and a manufacturing method thereof according to embodiments of the present invention.

【図10】本発明の実施形態に係る半導体装置の構造を示す斜視図である。 Is a perspective view showing a structure of a semiconductor device according to the embodiment of the present invention; FIG.

【図11】従来例に係るチップサイズパッケージを示す断面図である。 11 is a cross-sectional view of a chip size package according to a conventional example.

【図12】実装された状態のチップサイズパッケージを説明する断面図である。 12 is a cross-sectional view illustrating a chip size package of the mounting state.

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体基板上に形成された金属電極パッドと、この金属電極パッドに接続され前記半導体基板の表面に延在する配線層と、この配線層を含む半導体基板表面を被覆する絶縁層と、この絶縁層に形成された開口部と、この開口部に形成され前記配線層と接続された柱状端子と、この柱状端子の上面に設けられた上部電極と、 And 1. A metal electrode pad formed on a semiconductor substrate, a wiring layer this is connected to the metal electrode pad extending to the surface of the semiconductor substrate, an insulating layer covering the semiconductor substrate surface including the wiring layer When an opening formed in the insulating layer, the columnar terminal formed in the opening is connected to the wiring layer, and an upper electrode provided on the upper surface of the columnar pin,
    この上部電極上に搭載された半田ボールとを有し、前記上部電極の上面の面積を前記柱状端子の上面の面積よりも大きくしたことを特徴とする半導体装置。 And a solder ball mounted on the upper electrode, a semiconductor device which is characterized in that the area of ​​the upper surface of the upper electrode is larger than the area of ​​the upper surface of the pole terminals.
  2. 【請求項2】半導体基板上にLSIの金属電極パッドを形成する工程と、この金属電極パッドを被覆する第1の絶縁層を形成する工程と、前記金属電極パッドを露出する工程と、前記半導体基板上の全面に第1のメッキ用電極層を形成する工程と、前記第1のメッキ用電極上に第1のホトレジストパターンを形成し電解メッキ法により前記金属電極パッドと接続された配線層を形成する工程と、前記第1のホトレジストパターンを除去する工程と、前記配線層上に第2のホトレジストパターンを形成し電解メッキにより柱状端子を形成する工程と、全面に第2のメッキ用電極層を形成する工程と、この第2のメッキ用電極層上に第3のホトレジストパターンを形成し電解メッキ法により、前記柱状端子の上面の面積より大きい上面の面積を有 2. A process for forming a metal electrode pads of the LSI on a semiconductor substrate, forming a first insulating layer covering the metal electrode pad, and the step of exposing the metal electrode pad, the semiconductor forming on the entire surface first plating electrode layer on the substrate, said first forming a first photoresist pattern on the plating electrode wiring layer in which the connected with the metal electrode pad by electroplating forming, said removing the first photoresist pattern, forming a columnar pin by forming electrolytically plating a second photoresist pattern on the wiring layer, the entire surface of the second plating electrode layer forming a by forming electrolytically plating a third photoresist pattern on the second plating electrode layer, it has a surface area of ​​greater upper surface than the area of ​​the upper surface of the columnar pin る上部電極を形成する工程と、前記第2及び第3のホトレジストパターンと前記第2のメッキ用電極層を除去する工程と、前記第1のメッキ用電極の不要部分を除去する工程と、前記上部電極の上面に半田ボールを搭載する工程とを有することを特徴とする半導体装置の製造方法。 That forming an upper electrode, a step of removing the second and third photoresist pattern and the second plating electrode layer, and removing unnecessary portions of the first plating electrode, wherein the method of manufacturing a semiconductor device characterized by a step of loading solder balls on the upper surface of the upper electrode.
  3. 【請求項3】前記半田ボールを搭載した後に、LSIのスクライブラインに沿ってチップに分割する工程を有することを特徴とする請求項2に記載の半導体装置の製造方法。 After wherein mounting the solder balls, a method of manufacturing a semiconductor device according to claim 2, characterized in that it comprises a step of dividing into chips along the scribe line of LSI.
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