KR100345075B1 - Chip size package - Google Patents
Chip size package Download PDFInfo
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- KR100345075B1 KR100345075B1 KR1019990058387A KR19990058387A KR100345075B1 KR 100345075 B1 KR100345075 B1 KR 100345075B1 KR 1019990058387 A KR1019990058387 A KR 1019990058387A KR 19990058387 A KR19990058387 A KR 19990058387A KR 100345075 B1 KR100345075 B1 KR 100345075B1
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- metal film
- size package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 칩 사이즈 패키지에 관한 것으로서,반도체 칩은 그의 본딩 패드가 중앙에 배치된 제 1 표면과, 제 1 표면과반대면인제 2 표면을 갖는다. 서로반대면인제 1 및 제 2 표면을 갖는 기판의 제 2 표면이 도전성 접착제를 매개로 반도체 칩의 제 1 표면에 접착된다. 기판에는본딩 패드와연직선을 이루지 않는 위치에 수 개의 관통공이 형성되고, 이 관통공의 내벽 전체와 기판의 제 1 및 제 2 표면에 금속막이 도금된다. 따라서, 기판의 제 2 표면에 도금된 금속막이 도전성 접착제를 매개로 반도체 칩의 본딩 패드에 전기적으로 연결된다. 본딩 패드와 전기적으로 연결된 금속막 부분과 관통공 주위에 형성된 금속막 부분을 제외한 금속막의 나머지 부분은 솔더 레지스트로 절연된다. 한편, 반도체 칩의 하부와 측부는 봉지제로 몰딩된다. 관통공에는 솔더 볼이 삽입되어, 관통공 내벽에 도금된 금속막과 전기적 접촉을 이루게 된다.The present invention relates to a chip size package , wherein a semiconductor chip has a first surface with its bonding pad disposed centrally and a second surface opposite to the first surface. A second surface of the substrate having first and second surfaces opposite to each other is bonded to the first surface of the semiconductor chip via the conductive adhesive. Several through holes are formed in the board | substrate in the position which does not make a perpendicular line with a bonding pad , and the metal film is plated on the whole inner wall of this through hole, and the 1st and 2nd surface of a board | substrate. Thus, the metal film plated on the second surface of the substrate is electrically connected to the bonding pad of the semiconductor chip via the conductive adhesive. The remaining portion of the metal film except for the metal film portion electrically connected to the bonding pad and the metal film portion formed around the through hole is insulated with solder resist. On the other hand, the lower and side portions of the semiconductor chip are molded with an encapsulant. Solder balls are inserted into the through holes to make electrical contact with the metal film plated on the inner wall of the through holes.
Description
본 발명은 칩 사이즈 패키지에 관한 것으로서, 보다 구체적으로는 전체 크기에 비해 반도체 칩의 크기가 80% 정도 이상으로 구현되는 칩 사이즈 패키지에 관한 것이다.The present invention relates to a chip size package, and more particularly, to a chip size package in which the size of a semiconductor chip is about 80% or more relative to the total size.
반도체 패키지는 소형화, 고속화, 고기능화라는 전자 기기의 요구에 대응하기 위해, 새로운 형태가 계속해서 개발되어 종류가 다양해 지고 있다. 거기에 전자 기기의 용도에 대응하여 반도체 패키지의 적절한 사용이 중요하게 되었다. 메모리 반도체 제품에 있어서는 패키지의 소형, 박형화가 중요한 과제이며, 메모리로서는 대용량의 반도체 칩을 고밀도로 패키징하고 싶다는 요구가 강하다. 이러한 관점에서 1.0 mm 두께를 갖는 TSOP(thin small outlead package)와 같은 패키지가 개발되었다.In order to meet the demands of electronic devices such as miniaturization, high speed, and high functionality, semiconductor packages have been continuously developed in new forms and diversified types. In addition, the proper use of semiconductor packages has become important in response to the use of electronic devices. In memory semiconductor products, the miniaturization and thinning of packages is an important subject, and as a memory, there is a strong demand for high-density packaging of large-capacity semiconductor chips. In this respect, a package such as a thin small outlead package (TSOP) with a thickness of 1.0 mm has been developed.
그러나, 기존의 패키지는 그 크기가 너무 크기 때문에, 최근에는 경박단소의 추세에 따라 반도체 칩 정도의 크기를 갖는 칩 스캐일 패키지가 개발되었다.However, since the existing package is too large in size, a chip scale package having a size similar to that of a semiconductor chip has recently been developed in accordance with the trend of light and thin.
칩 스캐일 패키지는 패키지의 크기를 칩의 크기로 설정할 수 있다는 장점이 있기 때문에, 경박단소화되는 패키지 경향에 따라 연구가 계속되고 있는 추세이다. 이러한 칩 스캐일 패키지 중 기판을 이용한 종래의 칩 스캐일 패키지의 한 예가 도 1에 도시되어 있다.Chip scale packages have the advantage that the size of the package can be set to the size of the chip, the research is being continued in accordance with the trend of light and short package. An example of a conventional chip scale package using a substrate among such chip scale packages is shown in FIG. 1.
도 1에 도시된 바와 같이, 반도체 칩(1)은 그의 본딩 패드가 하부를 향하게 배치되어 있다. 중앙에 슬롯(2a)이 형성된 기판(2)이 접착제(4)를 매개로 반도체 칩(1)의 밑면에 접착되어 있다. 기판(2)의 밑면에는 금속 패턴(미도시)이 형성되어 있고, 금속 패턴의 일부분만이 노출되도록 기판(2) 밑면에는 절연성인 솔더 레지스트(3)가 도포되어 있다. 한편, 금속 패턴과 본딩 패드는 슬롯(2a)을 통해 인출되는 금속 와이어(5)에 의해 전기적으로 연결되어 있다. 전체 결과물의 상부가 봉지제(6)로 몰딩되어 있고, 솔더 레지스트(3)로부터 노출된 금속 패턴 부분에 솔더 볼(7)이 마운트되어 있다.As shown in Fig. 1, the semiconductor chip 1 is disposed with its bonding pads facing downward. The board | substrate 2 in which the slot 2a was formed in the center is adhere | attached on the bottom surface of the semiconductor chip 1 via the adhesive agent 4. A metal pattern (not shown) is formed on the bottom of the substrate 2, and an insulating solder resist 3 is coated on the bottom of the substrate 2 so that only a part of the metal pattern is exposed. On the other hand, the metal pattern and the bonding pads are electrically connected by the metal wires 5 drawn out through the slots 2a. The upper part of the whole resultant is molded with the sealing agent 6, and the solder ball 7 is mounted in the metal pattern part exposed from the soldering resist 3.
그런데, 도 1에 도시된 종래의 칩 사이즈 패키지는 솔더 볼이 기판으로부터 대부분 노출되어 있기 때문에, 봉지제의 표면으로부터 솔더 볼의 하단까지의 거리인 패키지의 전체 두께가 두꺼워진다는 단점이 있다. 즉, 실장 높이가 높아지게 된다.However, the conventional chip size package shown in FIG. 1 has the disadvantage that since the solder balls are mostly exposed from the substrate, the overall thickness of the package, which is the distance from the surface of the encapsulant to the bottom of the solder balls, becomes thick. That is, mounting height becomes high.
또한, 기판과 반도체 칩을 금속 와이어를 매개로 하여 전기적으로 연결시키는데, 이 금속 와이어가 수백 ㎛ 이상이 되고 또한 금속 패턴의 길이와 각 전기적 연결 계면에서의 접촉 저항이 증가되어, 고속화 추세인 반도체 패키지에는 부적합한 면이 많다.In addition, the substrate and the semiconductor chip are electrically connected through a metal wire, which is hundreds of micrometers or more, and the length of the metal pattern and the contact resistance at each electrical connection interface are increased, thereby increasing the speed of semiconductor packages. There are many inadequacies.
특히, 도 1에 도시된 패키지는 금속 와이어를 이용해서 반도체 칩의 본딩 패드와 기판의 금속 패턴을 전기적으로 연결시키도록 되어 있다. 따라서, 전술된 바와 같이 금속 와이어를 인출하기 위한 슬롯이 기판에 사전에 형성되어야 한다. 그런데, 슬롯의 위치는 항상 기판의 중앙에만 형성되어야만 하므로, 이러한 구조의 기판을 사용하는 패키지에는 본딩 패드가 중앙에 배치된 반도체 칩만이 적용되는 단점도 있다.In particular, the package shown in FIG. 1 is configured to electrically connect the bonding pads of the semiconductor chip and the metal pattern of the substrate using metal wires. Thus, as described above, slots for drawing metal wires must be formed in advance in the substrate. However, since the position of the slot should always be formed only in the center of the substrate, there is a disadvantage that only a semiconductor chip having a bonding pad disposed in the center is applied to a package using the substrate having such a structure.
따라서, 본 발명은 상기된 종래의 칩 사이즈 패키지가 안고 있는 제반 문제점들을 해소하기 위해 안출된 것으로서, 솔더 볼의 노출 정도를 줄여서, 실장 높이를 낮출 수 있는 칩 사이즈 패키지를 제공하는데 목적이 있다.Accordingly, an object of the present invention is to provide a chip size package capable of reducing mounting height by reducing the exposure degree of solder balls, which is devised to solve various problems of the conventional chip size package described above.
본 발명의 다른 목적은, 와이어 본딩 방식을 배제하여 접촉 저항을 줄일 수있게 하는데 있다.Another object of the present invention is to eliminate the wire bonding method to reduce the contact resistance.
본 발명의 또 다른 목적은, 본딩 패드의 위치에 구애받지 않고 여러 가지 형태의 반도체 칩에 적용이 가능하게 하는데 있다.Still another object of the present invention is to enable application to various types of semiconductor chips regardless of the position of the bonding pads.
도 1은 종래의 칩 사이즈 패키지를 나타낸 단면도.1 is a cross-sectional view showing a conventional chip size package.
도 2는 본 발명의 실시예 1에 따른 칩 사이즈 패키지를 나타낸 단면도.2 is a sectional view showing a chip size package according to a first embodiment of the present invention.
도 3은 본 발명의 실시예 2에 따른 칩 사이즈 패키지를 나타낸 단면도.3 is a cross-sectional view showing a chip size package according to a second embodiment of the present invention.
도 4는 본 발명의 실시예 3에 따른 칩 사이즈 패키지를 나타낸 단면도.4 is a sectional view showing a chip size package according to a third embodiment of the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 ; 반도체 칩 11,12 ; 본딩 패드10; Semiconductor chips 11,12; Bonding pads
20 ; 기판 21,23 ; 금속막20; Substrates 21,23; Metal film
22 ; 솔더 레지스트 30,31 ; 접착제22; Solder resists 30,31; glue
40 ; 봉지제 50 ; 솔더 볼40; Sealing agent 50; Solder ball
60 ; 접합 보조층 70 ; 도전성 범프60; Bonding auxiliary layer 70; Conductive bump
상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 칩 사이즈 패키지는 다음과 같은 구성으로 이루어진다.In order to achieve the above object, the chip size package according to the present invention has the following configuration.
실시예 1로서, 반도체 칩은 그의 본딩 패드가 중앙에 배치된 제 1 표면과, 제 1 표면과반대면인제 2 표면을 갖는다. 서로반대면인제 1 및 제 2 표면을 갖는 기판의 제 2 표면은 도전성 접착제를 매개로 반도체 칩의 제 1 표면에 접착된다. 기판에는본딩 패드와연직선을 이루지 않는 위치에 수 개의 관통공이 형성되고, 이 관통공의 내벽 전체와 기판의 제 1 및 제 2 표면에 금속막이 도금된다. 따라서, 기판의 제 2 표면에 도금된 금속막이 도전성 접착제를 매개로 반도체 칩의 본딩 패드에 전기적으로 연결된다. 본딩 패드와 전기적으로 연결된 금속막 부분과 관통공 주위에 형성된 금속막 부분을 제외한 금속막의 나머지 부분은 솔더 레지스트로 절연된다. 한편, 반도체 칩의 하부와 측부는 봉지제로 몰딩된다. 관통공에는 솔더 볼이 삽입되어, 관통공 내벽에 도금된 금속막과 전기적 접촉을 이루게 된다.As a first embodiment, a semiconductor chip has a first surface whose bonding pad is disposed in the center and a second surface opposite to the first surface. The second surface of the substrate having the first and second surfaces opposite to each other is adhered to the first surface of the semiconductor chip via the conductive adhesive. Several through holes are formed in the board | substrate in the position which does not make a perpendicular line with a bonding pad , and the metal film is plated on the whole inner wall of this through hole, and the 1st and 2nd surface of a board | substrate. Thus, the metal film plated on the second surface of the substrate is electrically connected to the bonding pad of the semiconductor chip via the conductive adhesive. The remaining portion of the metal film except for the metal film portion electrically connected to the bonding pad and the metal film portion formed around the through hole is insulated with solder resist. On the other hand, the lower and side portions of the semiconductor chip are molded with an encapsulant. Solder balls are inserted into the through holes to make electrical contact with the metal film plated on the inner wall of the through holes.
실시예 2로서, 반도체 칩은 그의 본딩 패드가 제 1 표면의 가장자리에 배치된다. 관통공은 본딩 패드의 연직 상부인 기판 부분에 형성된다. 따라서, 본딩 패드는 관통공을 통해 노출된다. 금속막은 관통공의 내벽과 그의 주위 부분에만 도금된다. 반도체 칩은 실시예 1과 마찬가지로 봉지제로 몰딩된다. 솔더 볼은 관통공에삽입되어, 직접 본딩 패드에 접촉하는 것에 의해 전기적 연결을 이루게 된다. 한편, 솔더 볼과 본딩 패드가 직접 접촉하게 되므로, 기판은 도전성이 아닌 절연성 접착제를 매개로 반도체 칩의 제 1 표면에 접착된다.In Embodiment 2, the semiconductor chip has its bonding pads disposed at the edge of the first surface. The through hole is formed in the portion of the substrate that is perpendicular to the bonding pads. Thus, the bonding pads are exposed through the through holes. The metal film is plated only on the inner wall of the through hole and its surrounding portion. The semiconductor chip is molded with an encapsulant as in Example 1. Solder balls are inserted into the through holes, making electrical connections by directly contacting the bonding pads. On the other hand, since the solder ball and the bonding pad are in direct contact, the substrate is adhered to the first surface of the semiconductor chip through an insulating adhesive that is not conductive.
실시예 3에 따른 패키지는 실시예 1과 거의 유사하다. 다만, 도전성 접착제가 사용되지 않고 대신에 도전성 범프가 사용된다. 즉, 도전성 범프가 본딩 패드에 형성되고, 기판의 금속막이 직접 도전성 범프에 접촉하여 전기적 연결을 이루게 된다. 따라서, 기판과 반도체 칩 사이에는 갭이 형성되는데, 이 갭은 봉지제에 의해 충진된다. 다른 부분은 실시예 1과 동일하다.The package according to Example 3 is almost similar to Example 1. However, no conductive adhesive is used and instead conductive bumps are used. That is, the conductive bumps are formed on the bonding pads, and the metal film of the substrate directly contacts the conductive bumps to make electrical connections. Thus, a gap is formed between the substrate and the semiconductor chip, which is filled by the sealing agent. The other part is the same as Example 1.
상기된 본 발명의 구성에 의하면, 솔더 볼이 기판에 형성된 관통공에 삽입되어 일부분만이 노출되므로, 패키지의 전체 두께가 종래의 패키지보다 줄어들게 된다. 또한, 금속 와이어가 사용되지 않고 기판의 금속막이 본딩 패드에 직접 전기적으로 연결되므로, 신호 전달 경로가 대폭 단축된다. 아울러, 본딩 패드의 위치에 따라 관통공의 형성 위치를 변경할 필요없이 금속막을 본딩 패드 위치에 따라 적절하게 형성하기만 하면 되므로, 본딩 패드의 위치에 구애받지 않고 적용이 가능하다.According to the configuration of the present invention described above, since the solder ball is inserted into the through-hole formed in the substrate to expose only a portion, the overall thickness of the package is reduced than the conventional package. In addition, since no metal wire is used and the metal film of the substrate is directly electrically connected to the bonding pad, the signal transmission path is greatly shortened. In addition, since the metal film needs to be appropriately formed according to the bonding pad position without changing the formation position of the through hole according to the position of the bonding pad, application can be made regardless of the position of the bonding pad.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
[실시예 1]Example 1
도 2는 본 발명의실시예 1에따른 칩 사이즈 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a chip size package according to Embodiment 1 of the present invention.
도시된 바와 같이, 본실시예 1에적용되는 반도체 칩(10)은 그의 본딩 패드(11)가 중앙에 배치된다. 보다 구체적으로, 반도체 칩(10)의 제 1 표면과 이에 반대되는 제 2 표면을 갖고, 본딩 패드(11)는 제 1 표면의 중앙에 배치된다.As shown, the bonding pad 11 of the semiconductor chip 10 applied to the first embodiment is disposed at the center. More specifically, having a first surface of the semiconductor chip 10 and a second surface opposite thereto, the bonding pad 11 is disposed at the center of the first surface.
기판(20)이 전기적 연결 매개체인 전도성 접착제(30)를 매개로 반도체 칩(10)의 제 1 표면에 접착되는데, 기판(20)도 제 1 표면과 이에 반대되는 제 2 표면을 갖는다. 즉, 기판(20)의 제 2 표면이 반도체 칩(10)의 제 1 표면에 접착된다. 기판(20)의 양측에는 수 개의 관통공이 형성된다. 따라서, 관통공과 본딩 패드(11)는 연직선상에 위치하지 않게 된다. 한편, 기판(20)의 제 1 및 제 2 표면에는 금속막(21)이 도금되고, 이 금속막(21)은 관통공의 내벽에도 도금되어서, 상하의 금속막(21)이 서로 전기적으로 연결된다. 특히, 기판(20)의 제 2 표면에 도금된 금속막(21)은 기판(20)의 중앙으로부터 관통공까지만 이어지도록 패터닝되고, 또한 기판(20)의 제 1 표면에 도금된 금속막(21)은 관통공의 주위에만 위치하게 패터닝된다. 패터닝된 금속막(21)만이 노출되도록, 기판(20)의 제 1 및 제 2 표면에는 절연성인 솔더 레지스트(22)가 도포된다. 따라서, 기판(20)의 제 2 표면에 도금된 금속막(21)은 도전성 접착제(30)를 매개로 본딩 패드(11)에 전기적으로 연결된다.The substrate 20 is adhered to the first surface of the semiconductor chip 10 via a conductive adhesive 30 which is an electrical connection medium. The substrate 20 also has a first surface and a second surface opposite thereto. That is, the second surface of the substrate 20 is adhered to the first surface of the semiconductor chip 10. Several through holes are formed at both sides of the substrate 20. Therefore, the through hole and the bonding pad 11 are not positioned on the vertical line. On the other hand, a metal film 21 is plated on the first and second surfaces of the substrate 20, and the metal film 21 is also plated on the inner wall of the through hole, so that the upper and lower metal films 21 are electrically connected to each other. . In particular, the metal film 21 plated on the second surface of the substrate 20 is patterned to extend only from the center of the substrate 20 to the through hole, and also the metal film 21 plated on the first surface of the substrate 20. ) Is patterned to be located only around the through hole. An insulating solder resist 22 is applied to the first and second surfaces of the substrate 20 so that only the patterned metal film 21 is exposed. Therefore, the metal film 21 plated on the second surface of the substrate 20 is electrically connected to the bonding pad 11 through the conductive adhesive 30.
반도체 칩(10)을 보호하기 위해서, 반도체 칩(10)의 하부와 측부가 봉지제(40)로 몰딩된다. 솔더 볼(50)이 각 관통공에 삽입되어, 관통공 내벽에 도금된 금속막(21)에 접촉하므로써, 솔더 볼(50)과 금속막(21)이 전기적 연결 상태를 이루게 된다. 특히, 솔더 볼(50)은 관통공으로부터 1/3 정도만이 노출되도록 관통공에 삽입된다. 따라서, 관통공은 솔더 볼(50)이 완전 삽입이 가능하도록 솔더 볼(50)의 직경과 거의 동일한 직경을 갖게 되고, 한편 기판(20)의 두께는 솔더 볼(50) 직경의 2/3 정도가 된다. 기판(20) 두께가 상기 조건이 되어야만, 솔더볼(50)의 1/3 정도가 관통공으로부터 노출될 수가 있게 된다.In order to protect the semiconductor chip 10, the lower and side portions of the semiconductor chip 10 are molded with the encapsulant 40. The solder ball 50 is inserted into each through hole, and comes into contact with the metal film 21 plated on the inner wall of the through hole, whereby the solder ball 50 and the metal film 21 form an electrical connection state. In particular, the solder ball 50 is inserted into the through hole so that only about one third of the solder ball 50 is exposed. Therefore, the through hole has a diameter substantially equal to the diameter of the solder ball 50 so that the solder ball 50 can be fully inserted, while the thickness of the substrate 20 is about 2/3 of the diameter of the solder ball 50. Becomes Only when the thickness of the substrate 20 is at this condition, about one third of the solder balls 50 can be exposed from the through hole.
[실시예 2]Example 2
도 3은 본 발명의 실시예 2에 따른 칩 사이즈 패키지를 나타낸 단면도이다.3 is a cross-sectional view illustrating a chip size package according to Embodiment 2 of the present invention.
도시된 바와 같이, 본 실시예 2에 적용되는 반도체 칩(10)은 그의 본딩 패드(12)가 중앙이 아니라 가장자리에 배치된다. 그리고, 기판(20)에 형성된 관통공은 본딩 패드(12)의 연직 상부에 배치되는데, 여기서 관통공의 형성 위치는 실시예 1 및 2에서 모두 동일하다. 즉, 실시예 1에서 사용되었던 기판(20)과 동일한 기판(20)이 본 실시예 2에서도 사용된다. 따라서, 본딩 패드(12)는 관통공을 통해서 상부로 노출된다.As shown, in the semiconductor chip 10 applied to the second embodiment, its bonding pads 12 are arranged at the edges, not at the center thereof. And, the through hole formed in the substrate 20 is disposed on the vertical upper portion of the bonding pad 12, where the formation position of the through hole is the same in both the first and second embodiments. That is, the same substrate 20 as that used in the first embodiment is used in the second embodiment. Thus, the bonding pads 12 are exposed upward through the through holes.
또한, 기판(20)은 실시예 1에서 사용되었던 도전성 접착제(30)가 아니라 비도전성 접착제(31)를 매개로 반도체 칩(10)의 제 1 표면에 접착되는데, 그 이유는 후술한다. 그리고, 금속막(23)은 오직 관통공의 내벽에만 도금되고, 솔더 레지스트(22)는 기판(20)의 제 1 및 제 2 표면에 도포된다. 봉지제(40)는 실시예 1과 같이 반도체 칩(10)의 하부와 측부를 몰딩하게 된다.Further, the substrate 20 is adhered to the first surface of the semiconductor chip 10 via the non-conductive adhesive 31 rather than the conductive adhesive 30 used in the first embodiment, which will be described later. The metal film 23 is plated only on the inner wall of the through hole, and the solder resist 22 is applied to the first and second surfaces of the substrate 20. The encapsulant 40 molds the lower and side portions of the semiconductor chip 10 as in the first embodiment.
솔더 볼(50)은 실시예 1과 같은 조건으로 관통공에 삽입되어서, 그의 하부가 본딩 패드(12)에 직접 접촉하면서 관통공의 측벽에 도금된 금속막(23)에도 접촉하게 된다. 이와 같이, 솔더 볼(50)이 직접 본딩 패드(12)에 접촉하는 것에 의해 전기 신호 전달 경로가 구현되므로, 접착제를 실시예 1과는 달리 비전도성을 사용하게 된다. 즉, 본 실시예 2에서는 실시예 1과 같이 전기적 연결 매개체가 필요없게 된다.The solder balls 50 are inserted into the through holes under the same conditions as those of the first embodiment, so that the lower parts of the solder balls 50 also contact the metal film 23 plated on the sidewalls of the through holes while the lower parts thereof directly contact the bonding pads 12. As such, since the electrical signal transmission path is implemented by directly contacting the solder pads 50 with the bonding pads 12, the adhesive uses non-conductivity unlike the first embodiment. That is, in the second embodiment, no electrical connection medium is required as in the first embodiment.
한편, 본 실시예 2에서 관통공의 내벽에 도금된 금속막(23)은 전기 신호 전달 경로의 역할을 하지 않는다. 그 대신에, 솔더 볼(50)은 적외선을 이용한 가열 공정, 즉 리플로우 공정에 의해 용융 및 경화 공정을 통해 형성되므로, 금속막(23)은 이러한 리플로우 공정시 솔더 볼(50)과 금속 반응을 일으켜서, 솔더 볼(50)을 견고히 지지하는 역할을 하게 된다. 이러한 금속막(23)의 기능은 실시예 1에서도 마찬가지로 발휘된다.Meanwhile, in the second embodiment, the metal film 23 plated on the inner wall of the through hole does not serve as an electric signal transmission path. Instead, the solder balls 50 are formed through the melting and hardening process by the heating process using infrared rays, that is, the reflow process, so that the metal film 23 reacts with the solder balls 50 and the metal during the reflow process. To cause a role of firmly supporting the solder ball 50. The function of the metal film 23 is similarly exhibited in the first embodiment.
또한, 본딩 패드(12)에는 솔더 볼(50)의 접합력 강화를 위해 접합 보조층(60:UBM)이 형성되는 것이 바람직하다. 접합 보조층(60)은 공지된 기술로서, 통상적으로 니켈/금의 이중층으로 이루어진다.In addition, it is preferable that the bonding auxiliary layer 60 (UBM) is formed on the bonding pad 12 to enhance the bonding strength of the solder ball 50. Bonding auxiliary layer 60 is a well-known technique, and typically consists of a bilayer of nickel / gold.
[실시예 3]Example 3
도 4는 본 발명의 실시예 3에 따른 칩 사이즈 패키지를 나타낸 단면도이다.4 is a sectional view showing a chip size package according to a third embodiment of the present invention.
도시된 바와 같이, 본 실시예 3은 실시예 1과 동일하게, 본딩 패드(11)가 중앙에 배치된 반도체 칩(10)이 적용된다. 다만, 실시예 1과 다른 점은 전기적 연결 매개체로서 도전성 접착제(30)가 사용되지 않고 대신에 도전성 범프(70)가 사용된다는 것이다.As shown, in the third embodiment, the semiconductor chip 10 having the bonding pads 11 disposed in the center is applied in the same manner as in the first embodiment. However, the difference from the first embodiment is that the conductive adhesive 30 is not used as the electrical connection medium, and the conductive bumps 70 are used instead.
보다 구체적으로 설명하면, 본딩 패드(11)에는 도전성 범프(70)가 형성되고, 기판(20)의 제 2 표면에 도금된 금속막(21)이 직접 도전성 범프(70)에 열압착 방식으로 접합된다. 따라서, 기판(20)과 반도체 칩(10) 사이에는 갭이 형성되는데, 봉지제(40)로 몰딩시, 이 갭 공간도 봉지제(40)로 채워지게 된다.In more detail, the conductive pads 70 are formed on the bonding pads 11, and the metal film 21 plated on the second surface of the substrate 20 is directly bonded to the conductive bumps 70 by thermocompression bonding. do. Accordingly, a gap is formed between the substrate 20 and the semiconductor chip 10. When molding with the encapsulant 40, the gap space is also filled with the encapsulant 40.
다른 구성요소들은 실시예 1과 동일하므로, 더 이상의 반복 설명은 생략한다.Since the other components are the same as those in Embodiment 1, further description will be omitted.
한편, 실시예 1 내지 3에서 금속막(21,23)의 재질은 구리/니켈/금으로 이루어지는 것이 바람직하다.On the other hand, in Examples 1 to 3, the material of the metal films 21 and 23 is preferably made of copper / nickel / gold.
이상에서 설명한 바와 같이 본 발명에 의하면, 솔더 볼이 관통공에 2/3 정도가 수용되므로써, 솔더 볼의 노출 정도가 줄어들게 되어, 패키지의 두께가 그만큼 감소하게 된다. 따라서, 패키지 실장 높이를 줄일 수가 있게 된다.As described above, according to the present invention, the solder ball is accommodated in the through hole by about 2/3, so that the exposure degree of the solder ball is reduced, and the thickness of the package is reduced by that amount. Therefore, the package mounting height can be reduced.
또한, 전기적 연결 매개체로서 금속 와이어가 사용되지 않고 금속막과 도전성 접착제 또는 도전성 범프, 또는 솔더 볼이 직접 본딩 패드에 전기적으로 접촉하게 되므로써, 길이 축소로 전기적 신호 전달 경로가 대폭 단축된다.In addition, since the metal wire is not used as the electrical connection medium and the metal film, the conductive adhesive or the conductive bump, or the solder ball are in direct contact with the bonding pad, the length of the electrical signal transmission path is greatly shortened.
특히, 본딩 패드의 위치에 따라 기판을 재제작하지 않고 그대로 호환하여 사용할 수가 있게 되므로, 본딩 패드 위치에 따라 기판 적용이 제한되지 않게 된다.In particular, since the substrate can be used as it is without remanufacturing according to the position of the bonding pad, application of the substrate is not limited according to the position of the bonding pad.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.
Claims (12)
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| KR1019990058387A KR100345075B1 (en) | 1999-12-16 | 1999-12-16 | Chip size package |
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| KR1019990058387A KR100345075B1 (en) | 1999-12-16 | 1999-12-16 | Chip size package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100649709B1 (en) * | 2005-10-10 | 2006-11-27 | 삼성전기주식회사 | A void-free type circuit board and semiconductor package having the same |
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| JP4072677B2 (en) | 2003-01-15 | 2008-04-09 | セイコーエプソン株式会社 | Semiconductor chip, semiconductor wafer, semiconductor device and manufacturing method thereof, circuit board, and electronic equipment |
| KR100748558B1 (en) | 2006-06-19 | 2007-08-10 | 삼성전자주식회사 | Chip size package and method of fabricating the same |
| KR100934268B1 (en) * | 2008-03-04 | 2009-12-28 | 한국과학기술원 | Bonding method of conductive pattern film |
| KR101517598B1 (en) | 2008-07-21 | 2015-05-06 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| KR100980454B1 (en) * | 2009-11-02 | 2010-09-07 | 한국과학기술원 | Bonding method of conductive pattern film |
| KR100980455B1 (en) * | 2009-11-02 | 2010-09-07 | 한국과학기술원 | Conductive pattern film and its bonding method |
| KR102373809B1 (en) | 2014-07-02 | 2022-03-14 | 삼성전기주식회사 | Package structure and manufacturing method thereof |
| KR102436220B1 (en) | 2015-09-18 | 2022-08-25 | 삼성전기주식회사 | Package substrate and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335606A (en) * | 1995-06-05 | 1996-12-17 | Nitto Denko Corp | Semiconductor device |
| JPH09306950A (en) * | 1996-05-16 | 1997-11-28 | Sony Corp | Semiconductor device, mounting board and mounting method |
| JPH09326415A (en) * | 1996-06-07 | 1997-12-16 | Matsushita Electric Ind Co Ltd | Ball grid array package |
| JPH1098071A (en) * | 1996-09-24 | 1998-04-14 | Mitsubishi Electric Corp | Semiconductor device and its production |
| JPH10189808A (en) * | 1996-12-24 | 1998-07-21 | Hitachi Chem Co Ltd | Chip-support structure for semiconductor package |
-
1999
- 1999-12-16 KR KR1019990058387A patent/KR100345075B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08335606A (en) * | 1995-06-05 | 1996-12-17 | Nitto Denko Corp | Semiconductor device |
| JPH09306950A (en) * | 1996-05-16 | 1997-11-28 | Sony Corp | Semiconductor device, mounting board and mounting method |
| JPH09326415A (en) * | 1996-06-07 | 1997-12-16 | Matsushita Electric Ind Co Ltd | Ball grid array package |
| JPH1098071A (en) * | 1996-09-24 | 1998-04-14 | Mitsubishi Electric Corp | Semiconductor device and its production |
| JPH10189808A (en) * | 1996-12-24 | 1998-07-21 | Hitachi Chem Co Ltd | Chip-support structure for semiconductor package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100649709B1 (en) * | 2005-10-10 | 2006-11-27 | 삼성전기주식회사 | A void-free type circuit board and semiconductor package having the same |
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