KR100359789B1 - Flip Chip Package - Google Patents
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- KR100359789B1 KR100359789B1 KR1020000083039A KR20000083039A KR100359789B1 KR 100359789 B1 KR100359789 B1 KR 100359789B1 KR 1020000083039 A KR1020000083039 A KR 1020000083039A KR 20000083039 A KR20000083039 A KR 20000083039A KR 100359789 B1 KR100359789 B1 KR 100359789B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 반도체 칩의 범프와 접촉되는 지점에 요홈부를 형성한 기판구조를 채용하여 패키지의 두께를 줄이면서도 범프와 범프 사이의 쇼트를 제거할 수 있는 플립칩 패키지를 제공한다.The present invention provides a flip chip package employing a substrate structure having a recessed portion formed in contact with a bump of a semiconductor chip to reduce the thickness of the package while removing a short between the bump and the bump.
본 발명의 플립칩 패키지는 전자회로가 집적되어 있는 반도체 칩과;The flip chip package of the present invention includes a semiconductor chip in which an electronic circuit is integrated;
상기 반도체 칩의 전기신호를 기판에 접속시키는 스터드 범프와;A stud bump for connecting an electrical signal of the semiconductor chip to a substrate;
저면에 패드가 설치된 요홈부를 구비하는 기판과;A substrate having a recess provided with a pad at a bottom thereof;
상기 기판 표면에 형성되어 반도체 칩과 기판의 접착력을 부여하는 동시에 통전기능을 갖는 이방성 도전성 접착수지와;An anisotropic conductive adhesive resin formed on the surface of the substrate to impart adhesion between the semiconductor chip and the substrate and having a current carrying function;
상기 기판의 배면에 융착되는 솔더볼;을 포함하며 상기 반도체 칩의 스터드 범프가 기판의 요홈부에 요철(凹凸)결합되어 통전되는 구성으로 이루어진다.And a solder ball fused to the back surface of the substrate, wherein the stud bumps of the semiconductor chip are concavely convex and energized.
Description
본 발명은 플립칩 패키지에 관한 것으로서, 보다 상세하게는 반도체 칩의 범프와 기판의 패드를 통전시키는 수단으로서 이방성 도전성 접착수지를 채용한 플립칩 패키지에 관한 것이다.The present invention relates to a flip chip package, and more particularly, to a flip chip package employing an anisotropic conductive adhesive resin as a means for energizing the bumps of the semiconductor chip and the pad of the substrate.
일반적으로 반도체패키지는 그 종류에 따라 수지밀봉 패키지, TCP(Tape Carrier Package)패키지, 글래스밀봉 패키지, 금속밀봉 패키지 등이 있다. 이와 같은 반도체 패키지는 실장방법에 따라 삽입형과 표면실장(Surface Mount Technology,SMT)형으로 분류하게 되는데, 삽입형으로서 대표적인 것은 DIP(Dual In-line Package), PGA(Pin Grid Array) 등이 있고, 표면실장형으로서 대표적인 것은 QFP(Quad Flat Package), PLCC(Plastic Leaded Chip Carrier), CLCC(Ceramic LeadedChip Carrier), BGA(Ball Grid Array) 등이 있다.In general, semiconductor packages may include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into insert type and surface mount technology (SMT) type according to the mounting method. Representative types include insert type dual in-line package (DIP) and pin grid array (PGA). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).
최근에는 전자제품의 소형화에 따라 인쇄회로기판의 부품 장착도를 높이기 위해서 삽입형 반도체패키지 보다는 표면실장형 반도체패키지가 널리 사용되고 있는데, 이러한 종래의 패키지에 대한 구조를 도 1과 도 2를 참조하여 QFP와, BGA패키지에 대하여 설명하면 다음과 같다.Recently, in order to increase the mounting degree of components of a printed circuit board according to the miniaturization of electronic products, surface mount type semiconductor packages are widely used rather than insert type semiconductor packages. The structure of such a conventional package is described with reference to FIGS. 1 and 2. The following describes the BGA package.
도 1은 종래의 일반적인 반도체 패키지의 QFP로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(11)과, 상기 반도체칩(11)이 에폭시(16)에 의해 부착되는 탑재판(15)과, 상기 반도체칩(11)의 신호를 외부로 전달할 수 있는 다수의 리드(12)와, 상기 반도체칩(11)과 리드(12)를 연결시켜 주는 와이어(13)와, 상기 반도체칩(11)과 그 외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 봉지수지(14)로 이루어지는 것이다.1 is a QFP of a conventional general semiconductor package, the structure of which is a semiconductor chip 11 in which an electronic circuit is integrated, a mounting plate 15 to which the semiconductor chip 11 is attached by an epoxy 16, and A plurality of leads 12 capable of transmitting signals of the semiconductor chip 11 to the outside, wires 13 connecting the semiconductor chips 11 and the leads 12, the semiconductor chips 11, In order to protect other peripheral components from external oxidation and corrosion, it is made of a sealing resin 14 wrapped around the outside thereof.
이러한 구성에 의한 종래의 QFP는 반도체칩(11)으로부터 출력된 신호와 와이어(13)를 통해 리드(12)로 전달되며, 상기 리드(12)는 마더보드에 연결되어 있어리드(12)로 전달된 신호가 마더보드를 주변소자로 전달된다. 주변소자에서 발생된 신호가 반도체칩(11)으로 전달되는 경우에는 위에서 설명한 경로의 역순으로 신호가 전달되는 것이다.The conventional QFP by such a configuration is transmitted to the lead 12 through the signal and the wire 13 output from the semiconductor chip 11, the lead 12 is connected to the motherboard is transferred to the lead 12 Signal is transmitted to the motherboard. When the signal generated from the peripheral device is transferred to the semiconductor chip 11, the signal is transmitted in the reverse order of the path described above.
그러나, 상기의 QFP는 반도체칩이 점차적으로 고성능화되어 가면서 핀의 수가 더욱더 많아지게 되는데 비하여, 핀과 핀사이의 거리를 일정치 이하로 좁히는 것은 기술적으로 어려움이 있기 때문에 많은 핀을 모두 수용하기 위해서는 패키지가 커지게 되는 단점이 있다. 이것은 반도체패키지의 소형화 추세에 역행하는 결과를 낳는 문제점이 있는 것이다.However, the QFP has a higher number of pins as the semiconductor chip becomes more and more high-performance, while it is technically difficult to narrow the distance between the pins to a certain value or less. There is a disadvantage that becomes large. This is a problem that results in the contrary to the trend of miniaturization of semiconductor packages.
이러한 문제점을 개선하고자 개발된 것이 플립칩(Flip Chip) 패키지이다. 도 2 에 상기 플립칩 패키지의 단면을 도시하였다.To improve this problem, a flip chip package has been developed. 2 is a cross-sectional view of the flip chip package.
도면을 참조하면, 상기 플립칩 패키지는 반도체 칩(21)의 배면에 통전 매개물인 범프(bump)(22)가 형성되어 있으며, 상기 범프(22)는 기판(substrate)(23) 표면에 설치된 패드(24)와 접촉된다. 상기 기판(23)의 내부에는 각 패드(24)로부터 기판(23)의 하면에 부착된 솔더볼(25)로 다수의 리드선(도시 생략)이 형성되어 있다.Referring to the drawings, the flip chip package includes a bump 22, which is a conduction medium, formed on a rear surface of the semiconductor chip 21, and the bump 22 is a pad provided on a surface of a substrate 23. Contact with (24). A plurality of lead wires (not shown) are formed in each of the pads 23 and the solder balls 25 attached to the bottom surface of the board 23 from each pad 24.
최근에는 이와 같은 구조에서 반도체 칩(21)과 기판(23)을 접착시키는 접착제 역할을 하는 동시에 이물질 침투를 방지하는 접착수지(26)로서 이방성전도성 필름(Anisotropic Conductive Film)(26a)이나 이방성전도성 어드헤시브(Anisotropic Conductive Adhesive)(26b)를 많이 사용한다.Recently, an anisotropic conductive film 26a or anisotropic conductive ad as an adhesive resin 26 that serves as an adhesive for bonding the semiconductor chip 21 and the substrate 23 in such a structure and at the same time prevents foreign matter from penetrating. Anisotropic Conductive Adhesive (26b) is often used.
상기 이방성전도성 필름(이하 ACF)이나 이방성전도성 어드헤시브(이하 ACA)는 수~수십 마이크로 단위의 얇은 접착 수지의 내부에 대략 5㎛의 직경으로 된 수백개의 금속성 알맹이에 폴리머(Polymer)가 코팅된 것으로, 이러한 ACF, ACA는 열압착시 도전체 사이에서 압착된 부분은 열로 인하여 금속성 알맹이에 코팅된 폴리머가 녹게 되어 통전상태를 유지하고, 그 외 부분은 절연상태를 유지한다.The anisotropic conductive film (hereinafter referred to as ACF) or anisotropic conductive adjuvant (hereinafter referred to as ACA) is a polymer coated with hundreds of metallic kernels having a diameter of approximately 5 μm in a thin adhesive resin of several to several tens of micro units. In this case, the ACF, ACA, the heat-compression-bonded portion between the conductors melt the polymer coated on the metallic kernel due to the heat to maintain the energized state, the other portion maintains the insulation state.
그러나 상기와 같은 플립칩 패키지를 제조하는 과정에서 반도체 칩(21)을 기판에 본딩할 때 접착수지 중 일례로 ACF에 포함되어 있는 금속성 도전입자(27)가 반도체 칩(21)의 범프(22)와 기판의 패드(24)사이에 들어오지 못하여 도전입자(27)간의 연속적인 배열이 생성되지 않아 범프(22)와 패드(24)간의 접속이 불량해지는 문제점이 발생한다.However, when the semiconductor chip 21 is bonded to the substrate in the process of manufacturing the flip chip package as described above, the metallic conductive particles 27 included in the ACF may be bumps 22 of the semiconductor chip 21. There is a problem in that the connection between the bump 22 and the pad 24 is poor because the continuous array between the conductive particles 27 is not generated because it does not enter between the pad 24 of the substrate.
또한, 반도체 칩(21)의 크기가 초소형일 경우에는 범프(22)와 범프(22)사이 간격이 너무 가까워 ACF의 도전입자가 범프(22)와 범프(22) 사이에서 연속적으로 배열됨으로써, 범프간에 쇼트가 발생하여 공정 불량 및 신뢰성 저하 등의 문제점을 수반한다.In addition, when the size of the semiconductor chip 21 is very small, the gap between the bump 22 and the bump 22 is so close that the conductive particles of the ACF are continuously arranged between the bump 22 and the bump 22, thereby causing bumps. Shorts occur between them, which entails problems such as process failure and reliability deterioration.
본 발명은 상술한 종래 기술의 문제점을 해결하고자 안출된 발명으로서, 반도체 칩의 범프와 접촉되는 지점에 홈을 형성한 기판구조를 채용하여 패키지의 두께를 줄이면서도 범프와 범프 사이의 쇼트를 제거할 수 있는 플립칩 패키지를 제공하는 것을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and employs a substrate structure in which grooves are formed in contact with bumps of a semiconductor chip, thereby reducing the thickness of the package and removing shorts between bumps and bumps. It is an object of the present invention to provide a flip chip package.
도 1 은 종래 반도체 칩 패키지 구조를 도시한 단면도.1 is a cross-sectional view showing a conventional semiconductor chip package structure.
도 2 는 종래 플립칩 패키지 구조를 도시한 단면도.Figure 2 is a cross-sectional view showing a conventional flip chip package structure.
도 3 은 본 발명에 의한 플립칩 패키지의 반도체 칩을 도시한 단면도.3 is a cross-sectional view showing a semiconductor chip of a flip chip package according to the present invention.
도 4 는 본 발명에 의한 플립칩 패키지의 기판을 도시한 단면도.4 is a cross-sectional view showing a substrate of a flip chip package according to the present invention.
도 5 는 본 발명에 관련된 이방성 도전성 접착수지를 도시한 단면도.5 is a cross-sectional view showing an anisotropic conductive adhesive resin according to the present invention.
도 6 은 본 발명에 의한 플립칩 패키지를 도시한 단면도.6 is a cross-sectional view showing a flip chip package according to the present invention.
** 도면의 주요부분에 대한 부호의 설명 **** Explanation of symbols for main parts of drawings **
21: 반도체 칩 22: 범프21: semiconductor chip 22: bump
30: 기판 31: 요홈부30: substrate 31: groove portion
31a: 요홈부의 측벽 32: 패드31a: side wall of recessed portion 32: pad
36: 이방성도전성 접착수지 37: 도전입자36: anisotropic conductive adhesive resin 37: conductive particles
상기 목적을 달성하기 위하여 본 발명의 플립칩 패키지는,Flip chip package of the present invention to achieve the above object,
전자회로가 집적되어 있는 반도체 칩과;A semiconductor chip in which electronic circuits are integrated;
상기 반도체 칩의 전기신호를 기판에 접속시키는 스터드 범프와;A stud bump for connecting an electrical signal of the semiconductor chip to a substrate;
저면에 패드가 설치된 요홈부를 구비하는 기판과;A substrate having a recess provided with a pad at a bottom thereof;
상기 기판 표면에 형성되어 반도체 칩과 기판의 접착력을 부여하는 동시에 통전기능을 갖는 이방성 도전성 접착수지와;An anisotropic conductive adhesive resin formed on the surface of the substrate to impart adhesion between the semiconductor chip and the substrate and having a current carrying function;
상기 기판의 배면에 융착되는 솔더볼;을 포함하며 상기 반도체 칩의 스터드 범프가 기판의 요홈부에 요철(凹凸)결합되어 통전(通電)되는 구성으로 이루어진다.And a solder ball fused to the back surface of the substrate, wherein the stud bumps of the semiconductor chip are unevenly coupled to the recesses of the substrate to conduct electricity.
상기 이방성 도전성 접착수지는 이방성 도전성 필름 또는 이방성 도전성 어드헤시브인 것을 특징으로 한다.The anisotropic conductive adhesive resin is characterized in that the anisotropic conductive film or anisotropic conductive additive.
상기 이방성 도전성 필름이나 이방성 도전성 어드헤시브는 두 개의 층을 가지되 상층은 일반 접착 수지층이며 하층에는 도전입자가 포함된 것을 특징으로 한다.The anisotropic conductive film or anisotropic conductive adjuvant has two layers, the upper layer is a general adhesive resin layer, and the lower layer is characterized in that the conductive particles are included.
본 발명의 구성에 대하여 첨부한 도면을 참조하면서 보다 상세하게 설명한다. 참고로 본 발명의 설명에 앞서, 설명의 중복을 피하기 위하여 종래 기술과 일치하는 부분에 대해서는 종래 도면부호를 그대로 인용하기로 한다.The structure of this invention is demonstrated in detail, referring an accompanying drawing. For reference, prior to the description of the present invention, in order to avoid duplication of description, reference numerals of the prior art reference numerals are used as they are.
도 3 은 본 발명에 관련된 반도체 칩의 단면을 도시한 도면이다.3 is a view showing a cross section of a semiconductor chip according to the present invention.
도면을 참조하면, 상기 반도체 칩(21)은 대략 평판형의 직각육면체로서, 내부에는 집적회로(도시 생략)가 구비되어 있으며 상기 집적회로의 인출단자 부분에 범프(22)가 형성된다. 상기 범프(22)는 골드(Au), 솔더(solder) 혹은 니켈 합금 등의 전도성 물질로서 융착되며, 반도체 칩(21)의 외부로 입,출력 신호를 전달하는통로 역할을 한다.Referring to the drawings, the semiconductor chip 21 is a substantially flat rectangular parallelepiped, and has an integrated circuit (not shown) therein and a bump 22 is formed in a lead terminal portion of the integrated circuit. The bump 22 is fused as a conductive material such as gold (Au), solder, or a nickel alloy, and serves as a path for transmitting input and output signals to the outside of the semiconductor chip 21.
상기 반도체 칩(21)은 통상 원형으로 제조된 웨이퍼를 잘라낸 것으로 그 두께가 보통 수 mil 정도로 초박형이다. 이러한 초박형의 반도체 칩에 형성되는 범프(22) 역시 대략 30~40㎛의 두께를 갖는다.The semiconductor chip 21 is cut from a wafer, which is usually manufactured in a circular shape, and is extremely thin, usually several mils thick. The bumps 22 formed on such ultra-thin semiconductor chips also have a thickness of approximately 30 to 40 μm.
도 4 에는 상기 반도체 칩(21)이 부착되는 기판(30)을 도시하였다.4 illustrates a substrate 30 to which the semiconductor chip 21 is attached.
상기 기판(30)은 범프(22)로 인출되는 반도체 칩(21)의 입출력 전기 신호를 기판의 패드(32)와 접속시키고, 상기 패드(32)에서 기판(30) 내부로 다수의 리드선(도시 생략)을 설치하여 기능에 맞게 분산하고 기판 배면에 설치될 솔더볼(도 6 참조)을 통해 마더 보드(도시 생략)와 입출력 신호체계를 유지하도록 하는 역할을 한다.The substrate 30 connects the input / output electrical signal of the semiconductor chip 21 drawn out to the bump 22 with the pad 32 of the substrate, and a plurality of lead wires (not shown) inside the substrate 30 at the pad 32. And the solder ball (see FIG. 6) to be installed on the back of the board to maintain the motherboard (not shown) and the input / output signal system.
상기 기판(30)에는 반도체 칩(21)의 범프(22)가 맞닿는 위치에 요홈부(31)가 형성되어 있다. 상기 요홈부(31)는 대략 사발형태의 홈으로서, 상기 요홈부(31)의 저면에는 패드(32)가 설치되어 있다. 상기 패드(32)는 전극단자로서 기판(30)의 배면에 부착되는 솔더볼과 전기적으로 통전되어 있다.A recess 31 is formed in the substrate 30 at a position where the bump 22 of the semiconductor chip 21 abuts. The recess 31 is an approximately bowl-shaped groove, and a pad 32 is provided on the bottom of the recess 31. The pad 32 is electrically connected to a solder ball attached to the rear surface of the substrate 30 as an electrode terminal.
상기 요홈부(31)는 솔더 마스크 등을 이용하여 반 에칭(half etching)방법등으로 제작이 가능하다.The recess 31 may be manufactured by a half etching method using a solder mask or the like.
기판의 상면에는 이방성 도전성 접착수지가 도포되는바, 도 5에 상기 이방성 도전성 접착수지(36)의 단면을 도시하였다.Anisotropic conductive adhesive resin is applied to the upper surface of the substrate, and FIG. 5 shows a cross section of the anisotropic conductive adhesive resin 36.
상기 이방성 도전성 접착수지(36)는 두 개의 층을 갖는다. 상기 이방성 도전성 접착수지는 도전성과 함께 접착성을 갖는 접착물질로서, 상층은 단순히 접착기능을 갖는 접착수지(36a)이며, 하층은 도전입자가 포함된 도전수지(36b)이다. 하층의 도전수지에 포함된 도전입자(37)는 직경이 대략 5㎛의 금속성알맹이로 표면에 폴리머가 코팅되어 있어 자연상태에서는 도전성을 갖지 않으나 도전체 사이에서 열압착을 받게 되면 도전입자(37)의 폴리머가 녹게 되어 도전체 사이를 통전시키는 기능을 한다.The anisotropic conductive adhesive resin 36 has two layers. The anisotropic conductive adhesive resin is an adhesive material having adhesiveness with conductivity, the upper layer is simply an adhesive resin 36a having an adhesive function, and the lower layer is a conductive resin 36b including conductive particles. The conductive particles 37 included in the conductive resin in the lower layer are metallic particles having a diameter of approximately 5 μm, and a polymer is coated on the surface thereof, so that the conductive particles 37 are not conductive in the natural state, but the conductive particles 37 are thermally compressed between the conductors. The polymer is melted to function to conduct electricity between the conductors.
이하 도 6을 참조하여 본 발명의 플립칩 패키지에 관하여 보다 상세히 설명한다.Hereinafter, the flip chip package of the present invention will be described in more detail with reference to FIG. 6.
도 6 에는 상기 반도체 칩이 기판에 접착된 상태를 보여주는 단면도를 도시하였다.6 is a cross-sectional view illustrating a state in which the semiconductor chip is bonded to a substrate.
도면에서 보는 바와 같이, 반도체 칩(21)의 범프(22)가 접착수지층(36a)과 도전수지층(36b)의 두 개의 층을 가진 이방성 도전성 접착수지층(36)을 통과하여 기판(30)의 요홈부(31)에 삽입된다. 비록 이방성 도전성 접착수지(36)가 ACA가 아닌 ACF일지라도 열압착하는 과정에 의해 용이하게 요홈부(31)로 삽입될 수 있다.As shown in the figure, the bumps 22 of the semiconductor chip 21 pass through the anisotropic conductive adhesive resin layer 36 having two layers of the adhesive resin layer 36a and the conductive resin layer 36b to form the substrate 30. It is inserted into the recess 31 of the. Although the anisotropic conductive adhesive resin 36 is ACF instead of ACA, the anisotropic conductive adhesive resin 36 may be easily inserted into the recess 31 by the process of thermocompression bonding.
상기 기판(30)의 요홈부(31) 저면에는 패드(32)가 설치되어 있어 범프(22)와 패드(32)사이에 형성되어 있던 이방성 도전성 수지층(36)은 반도체 칩(21)과 기판(30)을 열압착시 열과 함께 압축력을 받게 된다.The pad 32 is provided on the bottom surface of the recess 31 of the substrate 30 so that the anisotropic conductive resin layer 36 formed between the bump 22 and the pad 32 is formed of the semiconductor chip 21 and the substrate. When 30 is thermally pressed, the compressive force is received along with the heat.
이에 따라 도전입자(37)의 표면에 코팅된 폴리머가 녹으면서 도전입자(37)가 배열하여 범프(22)와 패드(32)사이를 통전시킨다.Accordingly, the polymer coated on the surface of the conductive particles 37 is melted and the conductive particles 37 are arranged to conduct electricity between the bumps 22 and the pads 32.
상기 기판(30)의 요홈부(31)의 경사진 측벽(31a)은 범프(22)가 삽입되면서 주변의 도전입자가 포함된 수지층과 범프 하부의 도전입자층을 분리시키는 역할을한다. 이와 같이 요홈부(31)의 측벽(31a)이 범프(22) 하부와 범프(22) 주위를 분리시키는 분리수단이 되어 도전입자(37)의 연결을 차단함으로써 범프(22)와 범프(22)간의 쇼트 발생 가능성을 없앨 수 있다.The inclined sidewall 31a of the recess 31 of the substrate 30 serves to separate the resin layer including the surrounding conductive particles and the conductive particle layer under the bump while the bump 22 is inserted. As such, the side wall 31a of the recess 31 serves as a separating means for separating the lower portion of the bump 22 from the periphery of the bump 22 to block the connection of the conductive particles 37 to the bump 22 and the bump 22. It can eliminate the possibility of short liver.
또한, 범프(22)와 패드(32) 사이의 도전입자(37)가 이탈할 통로가 요홈부(31)의 측벽(31a)에 의해 차단되므로 보다 안정적으로 통전효과를 높일 수 있다.In addition, since the passageway from which the conductive particles 37 are separated between the bumps 22 and the pads 32 is blocked by the side wall 31a of the recess 31, the energization effect can be more stably increased.
기존의 플립칩 본딩방식과 달리 범프가 기판의 표면과 접촉하는 것이 아니라 기판의 함몰된 요홈부에 안착되므로 범프가 삽입되는 높이만큼 두께가 절약되어 전체 패키지의 높이를 감소시킴으로써, 박형화된 플립칩 패키지를 구현할 수 있게 된다.Unlike the conventional flip chip bonding method, the bumps are not placed in contact with the surface of the substrate, but are seated in the recessed recesses of the substrate, thereby reducing the thickness of the entire package by reducing the height of the bumps, thereby reducing the height of the entire package. Can be implemented.
첫째, 기판에 형성된 요홈부의 내측벽이 범프와 범프간 도전입자들의 분리수단이 되어 범프와 범프 사이의 쇼트발생을 없앨 수 있다.First, the inner wall of the recess formed in the substrate serves as a separation means of the conductive particles between the bumps and the bumps, thereby eliminating the occurrence of short between the bumps and the bumps.
둘째, 범프가 요홈부의 내부로 삽입되는 결합으로 구조적 특성상 패키지의 전체 높이를 낮출 수 있다.Second, the bumps are inserted into the recesses to lower the overall height of the package due to its structural characteristics.
셋째, 범프와 패드 사이의 도전입자층이 압착될 때 요홈부의 측벽이 도전입자의 이탈을 방지하여 접속 안정성이 향상된다.Third, when the conductive particle layer between the bump and the pad is compressed, the side wall of the recess prevents the conductive particles from being separated, thereby improving the connection stability.
상기에서 본 발명의 특정한 실시 예가 설명 및 도시되었지만 본 발명이 당업자에 의해 다양하게 변형되어 실시될 가능성이 있는 것은 자명한 일이다.Although specific embodiments of the present invention have been described and illustrated above, it is obvious that the present invention may be variously modified and implemented by those skilled in the art.
이와 같이 변형된 실시 예들은 본 발명의 기술적 사상이나 전망으로부터 개별적으로 이해되어져서는 안되며, 이와 같은 변형된 실시 예들은 본 발명에 기술된 특허청구범위 안에 속한다 해야 할 것이다.Such modified embodiments should not be individually understood from the technical spirit or the prospect of the present invention, and such modified embodiments should fall within the claims described in the present invention.
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