JPS63276235A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the manufacturing yield of an IC for TAB by a method wherein the widths of leads for bonding other than the widths on bumps are made smaller than the lead widths on the bumps to prevent the leads from coming into contact with the bumps. CONSTITUTION:A semiconductor integrated circuit device is formed of a plurality of bumps 3 for electrode (TAB) formed on a semiconductor substrate 1 and leads 4 for TAB, which are connected to the bumps and are used for bonding. At that time, a part, which corresponds to a bump 3, of the widths of each lead 4 is formed wider (about 100 mum) and the part other than that part is formed narrower (about 50 mum). Whereupon, the width of the lead parts, which pass through between the bumps 3 on the outer side, of the leads 4 formed in two rows becomes narrow and a sufficient margin is given for the contact of the leads 4 with the bumps 3. Thereby, the manufacturing yield of an IC for TAB is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having leads for tape automatic bonding (hereinafter referred to as TAB).

[Conventional technology]

Conventionally, TAB leads in this type of semiconductor integrated circuit device have been configured to have a uniform width.

FIGS. 3(a) and 3(b) are a top view and an X-Y sectional view of a semiconductor integrated circuit device in which conventional TAB leads are formed, respectively.

As shown in FIG. 3(a), this semiconductor integrated circuit device includes an integrated circuit device (not shown) formed on a semiconductor substrate 1,
A surface protective insulating film 2 is coated thereon. Next, gold bumps 3 with a height of 20 μm are placed on this insulating film 2 as electrode pads.
A lead (copper plated with gold) 5 is formed to be used for bonding the TAB IC formed on the two sides by a plating method. The structure of the lead 5 is such that the width of the lead portion corresponding to the bump portion 3 and the width of the lead-out lead portion are the same (approximately 100 μm).

Also, as can be seen from the X, -Y cross section of the integrated circuit device in FIG. 3(a) shown in FIG. There is little margin for the lead 5 to pass between the bumps formed on the outside, and precision is required to connect the bump 3 to the lead 5.

[Problem that the invention seeks to solve]

The conventional structure described above has the following drawbacks. That is, with the progress of higher integration of TAB ICs, the distance between bumps has become narrower, and in particular, the distance between bumps arranged on the outside has become approximately 100 μm or less. In such a case, the leads bonded to the bumps arranged on the inside are extremely close to the bumps on the outside, and even if the bonding position becomes slightly large, the leads and bumps will come into electrical contact. Therefore, there is a drawback that the yield of TAB ICs is reduced.

In addition, as a measure to prevent such electrical contact, it is possible to narrow the width of the lead entirely, but in this case, the bonding part also becomes narrower, which has the disadvantage that the bonding strength decreases due to the small bonding area. .

An object of the present invention is to prevent contact between leads and bumps, which tends to occur as integrated circuit devices become denser, and thereby
It is an object of the present invention to provide a semiconductor integrated circuit device that also improves the manufacturing yield of AB ICs.

[Means for solving problems]

The present invention provides a semiconductor integrated circuit device having a plurality of electrode bumps formed on a semiconductor substrate and a bonding lead connected to the bumps, in which the width of the bonding lead excluding the area above the bump is It is configured to include at least a portion that is smaller than the lead width.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a top view of a semiconductor integrated circuit device and an X
-Y sectional view.

As shown in Figure 1(a), regarding the TAB IC,
Same as conventional case, but TA for bonding
The width of the B lead 4 is set to be wide (approximately 100 μm) in the part corresponding to the TAB bump 3 and narrow (approximately 50 μm) in other parts.
μm) What they did is different. That is, such a semiconductor integrated circuit device includes a plurality of electrode bumps 3 formed on two sides of each side on an insulating film 2 that protects a semiconductor substrate 1, and a TAB for bonding connected to these bumps 3.
It has a lead 4 for use. In particular, this TAB lead 4 is configured to have a portion in which the width of the bonding lead excluding the part above the bump 3 is smaller than the lead width above the bump 3.

Next, as shown in FIG. 1(b), the width of the lead portion of the TAB lead 4 that passes between the outer bumps 3 of the leads formed on the two sides becomes narrower, and the contact between the lead and the bump becomes smaller. can also have sufficient margin. This makes it possible to stabilize and improve the yield of TAB ICs.

, FIG. 2 is a top view of a semiconductor integrated circuit device for explaining a second embodiment of the present invention.

As shown in FIG. 2, such an integrated circuit device has a lead width narrowed (approximately
0 μm), and the other lead portions 5 are wide (approximately 100 μm).
m) Also in this embodiment, a sufficient degree of margin for contact between the bump 3 and the lead 4 can be obtained. This makes it possible to stabilize and improve the yield of TAB ICs.

Although the embodiments have been described above, the present invention has the advantage that the width of the TAB lead portion located between the two sides, particularly the outer bumps of the bumps formed in a staggered manner, is the same as that of the other lead portions.
For example, this is achieved by making the area narrower than the portion above the bump.

〔Effect of the invention〕

As explained above, the present invention prevents electrical contact between the lead and other bumps by partially narrowing the width of the TAB lead, and improves the yield of TAB IC even if some bonding position shift occurs. It has the effect of stabilizing and improving the Furthermore, since the lead area to be bonded is the same size as the conventional one, the bonding strength can be kept the same as the conventional one.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a top view of a semiconductor integrated circuit device and an X
-Y sectional view, FIG. 2 is a top view of a semiconductor integrated circuit device for explaining a second embodiment of the present invention, and FIGS.
b) is a top view and an X-Y cross-sectional view of a semiconductor integrated circuit device, respectively, for explaining an example of the conventional technology. 1... Semiconductor substrate, 2... Insulating film, 3... Bump for TAB, 4, 5... Lead for TAB. 2 accented doctor cow IV

Claims (1)

[Claims] In a semiconductor integrated circuit device having a plurality of electrode bumps formed on a semiconductor substrate and bonding leads connected to the bumps, the width of the bonding leads except on the bumps is wider than the lead width on the bumps. A semiconductor integrated circuit device comprising at least a reduced portion.