JP3367826B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounted semiconductor memory device having a structure in which a semiconductor memory element is connected to a mounting substrate through a bump electrode composed of a solder bump, and more particularly, it has a bump density considering assembly property. The present invention relates to an arrangement structure of solder bumps.

[0002]

2. Description of the Related Art Conventionally, in order to mount a semiconductor memory device (hereinafter referred to as a chip) on a mounting board such as a circuit board, a plurality of lead tips derived from the chip are electrically connected to a wiring pattern on the mounting board. Alternatively, the semiconductor memory device is directly mounted on the mounting substrate, and wire bonding,
There is a method of electrically connecting by TAB (Tape Automated Bonding). However, projecting the leads from the chip and mounting them on the mounting board is a major obstacle to high-density mounting of the semiconductor memory device. Particularly, in recent years, the applications of semiconductor memory devices have been diversified, and high-density mounting has been progressing. For example, a thin mounting substrate such as a memory card is used, and the number of mounted semiconductor memory elements is also increasing. There is a limit to mounting a chip using leads. Therefore, a flip-chip mounting method, which directly connects a plurality of connection electrodes (hereinafter, referred to as pads) formed on a chip to a wiring pattern of a mounting board, is currently receiving attention.

12 to 14 show a conventional semiconductor memory in which a silicon chip is flip-chip connected to a mounting substrate. The chip 1 of FIGS. 12 and 13 has a pad 7 made of Al or the like electrically connected to an internal integrated circuit on the surface thereof, and a low-voltage pad mainly composed of Pb, Sn or the like connected to the pad 7. The bump 3 having a height of about 100 μm and composed of a solder bump of a melting point metal is provided. A plurality of chips 1 are mounted on the mounting board 2. The plurality of bumps 3 on the chip are mounted on the mounting substrate 2 by being electrically connected to the wiring pattern of the wiring layer 8 formed on the surface of the mounting substrate 2. The bump 3 may be made of gold in addition to the low melting point metal, or may be an electrode having a conductive layer formed on the surface of an insulating spherical body. Known low melting point metals include Pb-Sn and In-Sn solders. As the mounting substrate 2, a printed substrate, a ceramic substrate, a silicon semiconductor substrate, or the like, which is formed by impregnating a glass base material with an epoxy resin and laminating it, is used.

FIG. 14 shows another conventional example, and since the structure is the same, the wiring pattern of the wiring layer 8 is formed on the mounting substrate 2. The chip 1 includes a pad 7 made of Al or the like and a bump 3 connected to the pad 7 and having a height of about 100 μ, such as a solder bump. In this way, the plurality of chips 1 are mounted on the mounting board 2. The plurality of bumps 3 on the chip are mounted on the mounting substrate 2 by being electrically connected to the wiring pattern of the wiring layer 8 formed on the surface of the mounting substrate 2. Generally, the temperature of a semiconductor memory device rises due to the heat generated from the chip when it is used. The heat generated from the chip is transmitted to the mounting board through the bumps, and the mounting board also becomes high in temperature. At this time, the chip and the mounting board thermally expand. In the flip-chip connection as shown in FIGS. 12 to 14, if there is a difference in the thermal expansion coefficient between the chip 1 and the mounting substrate 2, the thermal stress generated thereby concentrates on the bumps 3. In FIG. 14, in order to relieve such stress, a resin 4 is filled between the chip 1 and the mounting substrate 2 and the space between them is resin-sealed.

[0005]

FIG. 15 shows a conventional bump arrangement formed on a chip. The bumps 3 are formed on pads (not shown) on the surface of the chip 1 and are connected to the pads or bumps of the mounting board. The pad is usually made of metal such as aluminum. Since aluminum has poor connectivity with solder used for bumps, the pads are generally connected to the bumps 3 of the chip 1 through a barrier metal (not shown) made of titanium, nickel or the like. In the figure, the bump array is chip 1
Are formed along the opposite sides of. The bumps may be arranged in the middle of the facing sides of the chip, but no matter where they are arranged in the chip, the bump rows are not evenly spaced as shown in FIG. 15 even if they are arranged at the same pitch. In some cases. The pads are electrically connected to the semiconductor integrated circuit formed inside the chip 1, and the bumps are electrically connected to an external circuit. The bumps shown in the plan view of the chip below including FIG. 15 are shown as squares like the pads.

In the conventional bump arrangement, the bump arrangement for the purpose of electrical connection is prioritized, and a short circuit defect due to bump collapse is likely to occur, resulting in poor assembly. Techniques for arranging dummy bumps that are not intended for electrical connection have been proposed so far, but most of them have been aimed at improving heat dissipation and connection reliability. As described above, in a semiconductor memory device in which a chip is mounted on a mounting substrate by flip-chip connection, there is a technique for increasing the number of bumps in order to improve heat dissipation from the chip and connection reliability at a corner portion. However, there is no technology that focuses on the assembly property such as short-circuiting of adjacent bumps or defective connection. It is also known to form a hard bump that is not related to the wiring on the chip in order to prevent the crushing of the solder bump, but this forming step is performed in a step different from the solder bump, so that the number of steps is increased, which is preferable. Absent. In recent chips having a flip-chip connection structure, particularly in a memory chip in which a semiconductor memory device is formed, the connection pitch becomes narrow and the distance between the pumps tends to become small due to the increase in the number of pins of signals. Further, the weight of the chip tends to increase as the size of the chip increases. In such a case, in the method in which the bumps formed on the chip and the mounting substrate are melted and flip-chip connected, the bumps may be crushed by the weight of the chip during bump reflow and a bump short circuit may occur.

Bump collapse occurs by a mechanism as shown in FIG. The figure is a cross-sectional view of a mounting board on which a chip is mounted, which schematically shows how bumps are crushed during bump reflow. In the flip-chip connection, first, the rosin-based flux 5 is applied to the mounting board 2. After that, the chip 1 is mounted at a predetermined position on the mounting substrate 2 and heated to a temperature at which the solder melts using a reflow furnace or the like to connect the chip 1 and the mounting substrate 2. When heated during reflow, the flux 5 evaporates, and the flux volume decreases. The surface tension increases due to the volume phenomenon of the flux 5, and a force for attracting the chip 1 and the mounting substrate 2 to each other is generated. When the bumps 3 are melted in this state, the bumps 3 are crushed by an attractive force and a bump short circuit occurs. In order to prevent bump crushing, it is necessary to reduce the flux coating amount, but if the flux coating amount is reduced too much, conversely a connection failure such as an open failure occurs. Although the amount of flux is set by these trade-offs, it is difficult to actually control this. Generally, it is common to set a large amount of flux to prevent open defects. The present invention provides a flip-chip mounted semiconductor memory device in which bump shorts do not occur by setting the bump density to a predetermined value which is equal to or higher than a specified value, and a method for manufacturing the same.

[0008]

According to the present invention, a solder bump density per unit area is obtained from the number of solder bumps and a chip area in a semiconductor memory device, and the bump density is adjusted by adding a dummy bump to a predetermined value equal to or more than a specified value. This is characterized in that flip-chip mounting is performed in which bump shorts do not occur. That is, the invention of claim 1 is a semiconductor memory device in which a mounting substrate having a plurality of connection electrodes electrically connected to wiring formed on the surface thereof and a semiconductor memory device having a plurality of connection electrodes formed therein. A solder bump connecting the connection electrode of the mounting substrate and a connection electrode of the semiconductor memory element, and a dummy bump provided between the mounting substrate and the semiconductor memory element that does not contribute to electrical connection, The total number of bumps including the solder bumps and the dummy bumps is adjusted so as to have a predetermined bump density at which bump collapse does not occur when the semiconductor memory element and the mounting substrate are flip-chip connected, and the bump density is The area of the semiconductor memory device is 1.9 pieces / mm ² or more.

According to a second aspect of the present invention, in a semiconductor memory device, a mounting substrate having a plurality of connection electrodes electrically connected to wiring formed on a surface thereof, and a semiconductor having a plurality of connection electrodes formed therein. A memory element, a solder bump connecting the connection electrode of the mounting substrate and a connection electrode of the semiconductor memory element, and a dummy bump provided between the mounting substrate and the semiconductor memory element that does not contribute to electrical connection. The number of bumps including the solder bumps and the dummy bumps is adjusted so that bump crushing does not occur when the semiconductor memory device and the mounting substrate are flip-chip connected to each other so as to have a predetermined bump density.
The surface of the mounting board on which the wiring is formed is covered with a solder resist, and an opening is formed in the solder resist so as to expose the connection electrodes of the mounting board. In the individual opening method formed in each of the connection electrodes, the bump density of the bumps composed of the solder bumps and the dummy bumps is
1.1 pieces / mm with respect to the area of the semiconductor memory element
It is characterized by being ² or more. According to a third aspect of the present invention, in a semiconductor memory device, a mounting substrate having a plurality of connection electrodes electrically connected to wiring formed on a surface thereof, and a semiconductor memory element having a plurality of connection electrodes formed therein are provided. A solder bump for connecting the connection electrode of the mounting substrate and a connection electrode of the semiconductor memory element, and a dummy bump provided between the mounting substrate and the semiconductor memory element that does not contribute to electrical connection, The number of bumps including the dummy bumps and the dummy bumps is adjusted so as to have a predetermined bump density at which bump collapse does not occur when the semiconductor memory device and the mounting substrate are flip-chip connected. The surface on which the wiring is formed is covered with a solder resist, and the solder resist is applied so that the connection electrodes of the mounting board are exposed. Is a continuous opening method in which a plurality of connection electrodes of the mounting substrate are exposed in one opening, and the bump density of the bumps composed of the solder bumps and the dummy bumps is The area of the semiconductor memory device is 1.9 / mm ² or more.

The invention of claim 4 is the first to third aspects of the invention.
In the semiconductor memory device according to any one of items 1 to 3, the dummy bumps are arranged in a peripheral portion of the surface of the semiconductor memory element, and the dummy bumps are arranged substantially symmetrically with respect to the center of the surface of the semiconductor memory element. And According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor memory device, the circuit of the semiconductor memory device is designed, and the number of bumps required for the semiconductor memory element and / or the mounting substrate is determined based on this design, Setting the bump density of the semiconductor memory device or the mounting substrate to a predetermined value that does not exceed the crush amount limit, and determining the number of bumps corresponding to this value, and the number of bumps corresponding to the predetermined value that does not exceed the crush amount limit. And a step of calculating the difference between the required number of bumps based on the design and setting this as the number of dummy bumps used in this semiconductor memory device, and the predetermined number of solder bumps and dummy bumps in the semiconductor memory device or the mounting substrate. Flip-chip the semiconductor memory device on the mounting board by applying flux to the mounting board and forming bumps on the mounting board Characterized in that it comprises a step of connection.

The solder bump used in the semiconductor memory device of the present invention is mounted on the chip side or on the mounting substrate side before mounting the chip on the mounting substrate. Alternatively, the chip and the mounting substrate are attached to each other, and when the chip is fixed to the mounting substrate, the solder bumps attached to both the chip and the mounting substrate are overlapped and bonded to each other. Further, the bump materials on the chip side and the mounting substrate side have the same composition. The bump density after melting the solder bumps and performing flip-chip connection is adjusted by adding dummy bumps that are not electrically connected to the integrated circuits in the chip so that the number of bumps is more than the number shown in Table 1 with respect to the chip area. It is decided at the design stage to arrange. With such an arrangement, bump crushing can be prevented with a flux amount that does not cause an open defect.

[0012]

[Table 1]

Since the degree of bump crushing and the frequency of occurrence of bump shorts depend on the pad shape on the mounting substrate side, FIG. 2 shows a pad structure formed on the surface of the mounting substrate. The pad structure on the mounting board depends on the shape of the solder resist 9 covering the wiring surface of the mounting board. Figure 2
In the individual opening method of (a), the solder resist 9 on the mounting substrate is opened only in the region of the pad 8 formed on the wiring 10. The continuous opening method of FIG.
The plurality of pads 8 formed in 0 are exposed from one opening of the solder resist 9, and a part of the mounting substrate 2 not occupied by the wiring 10 is also exposed in this opening. There is. There are two types of pad 8; one is to use a part of the wiring 10 as it is and the other is to separately form a pad part in a predetermined region of the wiring 10. The individual opening method is difficult to form and high in cost, and thus is suitable for a semiconductor memory device (semiconductor memory) such as SRAM, which has been advanced in speed. Since the continuous opening method is formed at low cost,
For example, it is suitable for a versatile and inexpensive memory such as DRAM. The material of the solder resist is matched depending on the substrate. If the mounting board is a ceramic such as alumina, an alumina (Al ₂ O ₃ ) film is used. If the printed circuit board in which glass fiber is impregnated with a synthetic resin such as epoxy is used as the mounting board, an epoxy resin film or A polyimide film or the like is used as the solder resist. Comparing the pad structures of the mounting substrates, the bumps are more likely to be crushed in the lateral direction and bump shorts are more likely to occur in the continuous opening pad. Therefore, it is necessary to increase the number of bumps as compared with the individual opening pad.

The inventor has made the present invention by paying attention to the number of bumps and the chip size, and finding that there is a range of bump densities in which bump collapse does not occur in a flux coating amount in which bump open defects do not occur. FIG. 3 is a characteristic diagram showing the bump density dependency of the bump crush amount when the chip is mounted on the mounting substrate. Bump collapse amount on the vertical axis (%)
And the abscissa shows the bump density (pieces / mm ² ). Curve A is a bump crush amount-bump density curve of the continuous opening method, and curve B is a bump crush amount-bump density curve of the individual opening method.
A curve C is a bump crush amount-bump density curve based on a calculation formula. From these results, it can be seen that the bump collapse amount decreases as the bump density increases. The allowable value of the bump crush amount varies depending on the bump pitch, but if the bump is crushed by 20% or more with respect to the height of the bump, bump short circuit frequently occurs in the entire chip. This crushed amount is 20
% To keep bumps short and prevent bump shorts, curve A,
As shown in B, the bump density is 1.9 pieces / mm ² or more in the continuous opening method and 1.1 pieces / mm ^{2 in} the individual opening method.
It should be at least mm ² .

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First, an embodiment of the first invention will be described with reference to FIGS. 1, 2 and 3. FIG. 1 is a plan view of a chip showing a bump arrangement. In the embodiment of the present invention, the mounting substrate is the individual opening pad type substrate shown in FIG. The mounting substrate 2 is a printed wiring board made of glass nonwoven fabric impregnated with a resin such as epoxy resin, and the solder resist 9 formed on the surface is, for example,
It is composed of epoxy resin. Solder resist 9
Covers the area other than the pads 8 on the wiring surface of the mounting substrate 2 on which the wiring 10 is formed (FIG. 2A). Bump 3
Is formed on a pad (not shown) which is a connection electrode on the surface of the chip 1 and is formed on the mounting substrate 2.
Alternatively, it is connected to the bump on the pad. The chips and pads of the mounting board are usually made of metal such as aluminum. Since aluminum has poor connectivity with solder used for bumps, the pads are generally connected to the bumps 3 of the chip 1 via a barrier metal (not shown) made of titanium, nickel or the like. In FIG. 1, the bump rows are formed along the opposite sides of the chip 1.

The bumps may be arranged in the middle of the facing sides of the chip, but wherever they are arranged in the chip, the bump rows may be arranged at the same pitch, or in FIG. In some cases, the intervals are not constant. The pads are electrically connected to the semiconductor integrated circuit formed inside the chip 1, and the bumps 3 are electrically connected to an external circuit. In the embodiment of the present invention,
Dummy bumps 31 not intended for electrical connection are arranged between the bumps 3 in the bump row. The layout of the dummy bumps is defined only by the number of bumps, and the dummy bumps 31
The number of dummy bumps is determined so that the bump density of the bump group composed of 3 and bumps 3 is 1.1 / mm ² or more. The dummy bumps 31 are not provided for the purpose of electrically connecting the chip 1 to the mounting substrate, and therefore need not be connected to the pads. However, it is also possible to form a pad that is not electrically connected to the semiconductor integrated circuit inside the chip and connect the bump thereto.
The dummy bumps are preferably composed of a solder material having the same composition as the bumps of the chip.

The bumps of the chip are bonded to the pads of the wiring of the mounting substrate or the bumps formed on the pads to mount the chip. For flip-chip connection when the chip is mounted on the mounting substrate, first, the rosin-based flux 5 is applied to the mounting substrate 2. After that, the chip is mounted at a predetermined position on the mounting board and heated to a temperature at which the solder melts using a reflow oven or the like to connect the chip and the mounting board. The flux evaporates due to the heating during reflow, and the flux volume decreases. The surface tension increases due to the volume phenomenon of the flux, and a force for attracting the chip and the mounting substrate to each other is generated. If the bumps are melted in this state, the bumps may be crushed due to the attractive force and a bump short circuit may occur. In order to prevent bump crushing, it is necessary to reduce the amount of flux applied, but if the amount of flux applied is reduced too much,
On the contrary, a connection failure such as an open failure occurs. The amount of flux is set by these trade-offs,
It is difficult to actually control this. Generally, it is common to set a large amount of flux to prevent open defects. When a dummy bump is added to the solder bump formed on the main surface of the chip and the density of the bump including the dummy bump is set to 1.1 / mm ² or more, the bump collapse amount is 20% as shown by the curve B in FIG. It will be below and will be below the crush amount limit. Bump collapse caused by melting of the bump due to reflow is avoided, and the occurrence of bump shorts is reduced.
As a result, it is possible to provide a semiconductor memory in which bump crushing can be suppressed and bump short circuits do not occur regardless of the amount of flux applied.

Next, an embodiment of the second invention will be described with reference to FIG. FIG. 4 is a plan view of the chip showing the bump arrangement. In the embodiment of the present invention, as the mounting substrate, the continuous opening pad type substrate shown in FIG. 2 is used. The mounting substrate 2 is formed of a printed wiring board obtained by impregnating a glass nonwoven fabric with a resin such as epoxy resin, and the solder resist 9 formed on the surface is formed of, for example, epoxy resin. The solder resist 9 covers most of the wiring surface of the mounting substrate 2 on which the wiring 10 is formed, but partially covers the plurality of pads 8 formed on the plurality of wirings 10 so as to be continuously exposed. It has a part which is not (FIG.2 (b)). The bumps 3 are formed on pads (not shown) that are connection electrodes on the surface of the chip 1, and are connected to the pads 8 formed on the mounting substrate 2 or the bumps on the pads. The chips and pads of the mounting board are usually made of metal such as aluminum. Since aluminum has poor connectivity with solder used for bumps, the pads are generally connected to the bumps 3 of the chip 1 via a barrier metal (not shown) made of titanium, nickel or the like. In FIG. 4, the bump array is formed along each side of the chip 1. The bump rows may be arranged at the same pitch, or the intervals may not be constant as shown in FIG.

Dummy bumps 3 not intended for electrical connection
1 is arranged between the solder bumps 3 in the bump row.
Regarding the layout of the dummy bumps, the number of dummy bumps is defined only by the number of bumps, and the number of dummy bumps is determined so that the bump density of the bump group including the dummy bumps 31 and the bumps 3 is 1.9 / mm ² or more. The dummy bump does not need to be connected to a pad formed on the chip, but a pad that is not electrically connected to the semiconductor integrated circuit inside the chip may be formed and connected to the pad. The dummy bumps are preferably composed of a solder material having the same composition as the bumps of the chip. The bumps of the chip are bonded to the pads of the wiring of the mounting substrate or the bumps formed on the pads to mount the chip. The flip-chip connection when the chip is mounted on the mounting board is the same as that of the first embodiment of the invention. When a dummy bump is added to the solder bump formed on the main surface of the chip and the density of the bump including the dummy bump is set to 1.9 / mm ² or more, the bump crushing amount is 20% as shown by the curve A in FIG.
It will be below and will be below the crush amount limit. Bump collapse caused by melting of the bump due to reflow is avoided, and the occurrence of bump shorts is reduced. As a result, it is possible to provide a semiconductor memory in which bump crushing can be suppressed and bump short circuits do not occur regardless of the amount of flux applied.

Next, an embodiment of the third invention will be described with reference to FIG. FIG. 5 is a plan view of the chip showing the bump arrangement. In the embodiment of the present invention, the mounting substrate is the continuous opening pad type substrate shown in FIG. The mounting substrate 2 is formed of a printed wiring board obtained by impregnating a glass nonwoven fabric with a resin such as epoxy resin, and the solder resist 9 formed on the surface is formed of, for example, polyimide. The solder bumps 3 are formed on pads (not shown) which are connection electrodes on the surface of the chip 1.
It is connected to the pads 8 and the like formed on the mounting substrate 2. The chip and the pad of the mounting substrate are made of aluminum or the like. Since aluminum has poor connectivity with solder used for bumps, the pads are generally connected to the solder bumps 3 of the chip 1 through a barrier metal (not shown) made of titanium, nitride, nickel or the like. There is. In FIG. 5, the bump rows are spaced apart from each side of the chip 1 and arranged in two rows at equal intervals in the central portion of the chip. This arrangement applies to LOC type memory chips. The dummy bumps 31 not intended for electrical connection have the solder bumps 3 formed in the central portion of the chip 1, but are arranged along the sides in the peripheral portion.

In the embodiment of the present invention, the solder bumps in the central portion are arranged on a pair of sides parallel to the chip row. Regarding the layout of the dummy bumps, the number of dummy bumps is defined only by the number of bumps, and the number of dummy bumps is determined so that the bump density of the bump group including the dummy bumps 31 and the bumps 3 is 1.9 / mm ² or more. The dummy bump is
It is not necessary to connect to the pad formed on the chip, but it is also possible to form a pad that is not electrically connected to the semiconductor integrated circuit inside the chip and connect to the pad. The dummy bumps are preferably composed of a solder material having the same composition as the bumps of the chip. The dummy bumps are preferably arranged symmetrically with respect to the center of the chip as shown in FIG. With such an arrangement structure, the chip and the mounting substrate are evenly joined by the solder bump and the dummy bump. The solder bumps of the chip are mounted by bonding the pads of the wiring of the mounting substrate or the bumps formed on the pads to the chip.
The flip-chip connection when the chip is mounted on the mounting substrate is performed by the same method as that of the first embodiment of the invention.

When dummy bumps are added to the solder bumps formed on the main surface of the chip and the density of the bumps including the dummy bumps is set to 1.9 / mm ² or more, the bump crushing amount becomes as shown by the curve A in FIG. , 20% or less, which is below the crush amount limit. Bump collapse caused by melting of the bump due to reflow is avoided, and the occurrence of bump shorts is reduced. As a result, it is possible to provide a semiconductor memory in which bump crushing can be suppressed and bump short circuits do not occur regardless of the amount of flux applied. Next, the relationship between the number of bumps of the semiconductor memory (DRAM) of the present invention and the bump density for a chip will be described with reference to FIG. The vertical axis shows the number of bumps on the chip (piece), and the horizontal axis shows the bump density on the chip (piece / mm ² ). As the memory capacity and the number of bits of the semiconductor memory increase, the chip size increases and the number of pads increases. For example, in a DRAM having a chip size of 18.0 × 8.0 mm (straight line D), when the number of pads is increased from 66 to 138 per chip, the bump density is 0.45 / mm ² to 0.96. Increase to pieces / mm ² .

The chip size is 22.0 × 13.0.
In the DRAM (straight line E) of mm, when the number of pads is increased from 68 to 236 per chip, the bump density becomes 0.
Increased from 24 pieces / mm ² to 0.83 pieces / mm ² . In all cases, the bump density of 1.1 pcs / mm ² in the case of the individual opening method and the bump density 1.9 pcs / mm ² in the case of the continuous opening method, which are the limit values of the collapse amount, are not exceeded. Therefore, if dummy bumps are additionally formed according to the manufacturing method of the present invention and the bump density of the chip is set to 1.1 pieces / mm ² or more or 1.9 pieces / mm ² or more, flux evaporation during bump reflow is caused. Bump collapse can be prevented. Next, a chip bump connection structure and a chip mounting method common to the present invention will be described. FIG. 7 is a cross-sectional view of a chip bonded to a mounting board. The bumps are formed on the chip in advance (FIG. 7 (a)) and the bumps of the mounting substrate are joined at the time of mounting, so that the bumps are not provided on the chip before mounting (FIG. 7 (b)). ) There is. Chip 1 such as silicon
The main surface of is covered with an insulating film 11 such as a silicon oxide film. Pad 7 made of aluminum which is a connection electrode
Are formed in between.

The aluminum pad 7 is 90 to 1 on one side.
It is a quadrangle of 50 μm, preferably 100 to 140 μm. A barrier metal layer 12 is formed on this. In general, aluminum and solder have poor bondability and require the inclusion of a barrier metal. The barrier metal layer 12 is formed somewhat wider (about 10%) than the pad 7. Barrier metal layer 12
Consists of a Ti / Ni / Pd film, and the pad-Ti / Ni
/ Pd-bump structure. In the chip 1 of FIG. 8A, ball-shaped solder bumps 3 are bonded onto the barrier metal layer 12. The solder bumps are ball-shaped, but are shown as squares for convenience in a plan view. FIG. 8 is a cross-sectional view of the mounting board before the chip is mounted. Figure 8
Bumps are not previously formed on the mounting board of FIG. 8A, and bumps are preliminarily formed on the mounting board of FIG. 8B. The display of the solder resist formed on the surface of the mounting board is omitted. The mounting board 2 is formed of a printed wiring board in which a glass non-woven fabric is impregnated with a resin such as an epoxy resin, and is covered with a solder resist such as polyimide formed on the surface thereof. Pads 13 made of tungsten (W), which are connection electrodes, are formed between the solder resists of the mounting substrate 2.

The pad 13 uses a part of a wiring (not shown) formed on the surface of the mounting substrate 2 or is formed on this wiring. 1 tungsten pad 13
It is a quadrangle with sides of 90 to 150 μm, preferably 100 to 140 μm. A barrier metal layer 14 is formed on top of this to improve the bondability with the solder bumps. The barrier metal layer 14 is made of an Au / Ni / Ti film, and has a pad-A.
It has a structure of u / Ni / Ti-bump (W). In the chip 1 of FIG. 8B, ball-shaped solder bumps 3 are bonded onto the barrier metal layer 14. FIG. 9 is a cross-sectional view of the mounting board before the chips are mounted. The mounting substrate of FIG. 9 has the same configuration as that of FIG. 8 except for the bump structure. Pads 15 made of copper (Cu) are formed between the solder resists on the surface of the mounting substrate 2. The pad 15 uses a part of wiring (not shown) formed on the surface of the mounting substrate 2 or is formed on this wiring. The copper pad 15 has a side of 90 to 150 μm, preferably 100 to 150 μm.
It is a 140 μm quadrilateral. A barrier metal layer 16 is formed on top of this to improve the bondability with the solder bumps. The barrier metal layer 16 is made of an Au / Ni film and has a pad-Au / Ni-bump (Cu) structure. In the chip 1 of FIG. 8B, this barrier metal layer 1
The ball-shaped solder bumps 3 are bonded onto the surface 6.

FIG. 10 is a sectional view for explaining a method of joining the chip shown in FIGS. 7 to 9 to a mounting board. Figure 1
The semiconductor memory of 0 (a) has a structure shown in FIG. 8 (a) or FIG. 9 (a).
The chip 1 of FIG. 7A is mounted on the mounting substrate 2 of FIG.
The bumps 3 on the chip side are bonded to the pads 13 on the mounting substrate 2. At the same time, the dummy bumps formed on the chip 1 are also bonded to the pads 13 on the mounting substrate side. In the semiconductor memory of FIG. 10B, the chip 1 of FIG. 7B is mounted on the mounting substrate 2 of FIG. 8B or 9B. Bump 3 on the mounting board side
Is bonded to the pad 7 on the chip side. At the same time, the dummy bumps formed on the mounting substrate 2 are also bonded to the pads 7 on the chip side. In the semiconductor memory of FIG. 10C, the chip 1 of FIG. 7A is mounted on the mounting substrate 2 of FIG. 8B or 9B. The bumps 3 on the mounting substrate side are bonded to the bumps 3 on the chip side. At the same time, the dummy bumps formed on the chip 1 or the mounting substrate 2 are also bonded to the bumps 3 on the mounting substrate side or the chip side.

Next, with reference to FIG. 11, a description will be given of a method of manufacturing a semiconductor memory according to the present invention, in which the number and arrangement of dummy bumps are determined and flip-chip connection is performed. After determining the number and arrangement of the dummy bumps, solder bumps and dummy bumps are formed on the chip and the mounting board, and the chip is bonded to the mounting board. FIG. 11 is a flow chart for explaining this manufacturing process. First, design a semiconductor memory circuit such as DRAM,
Based on this design, the number of pads (a) required on the chip or the mounting board or both and the position on the chip or the mounting board are determined. 1.1 bumps / mm that does not exceed the bump density limit
² or more or 1.9 / mm ² or more is set to a predetermined value, obtains the number of bumps corresponding to the value (b) the characteristic line D in FIG. 6, the E. The difference (b-a) in the number of bumps obtained in and is calculated and used as the number of dummy bumps used in this semiconductor memory. A predetermined number of solder bumps and dummy bumps are formed at predetermined positions on the chip or the mounting substrate. Flux is applied to the mounting board and the chip is flip-chip connected to the mounting board by bump reflow.

If the flip chip connection is performed by the above manufacturing process, the chip is surely mounted on the mounting substrate regardless of the flux coating amount. The bump arrangement is not particularly limited with respect to the arrangement such that it is arranged only on two opposite sides or arranged on four sides so long as the above-mentioned bump density condition is satisfied. However, when the bumps are added in order to increase the bump density, it is desirable to arrange the bumps so that the pitches are as uniform as possible (pitch of 250 μm or less is preferable). The solder composition is the same on both the chip side and the mounting substrate side, and is targeted for flip-chip connection in which both bumps are melted and bump-connected.
Therefore, the solder composition is not limited, and Pd-Sn system, Sn
Any composition such as -Ag type or Sn-Zn type may be used. It is preferable to use solder having a melting point of 230 ° C. or lower. There are various types of flux such as rosin-based, organic acid-based, and water-based flux, which may be appropriately selected in consideration of the mounting board material, solder composition, and the like.

[0029]

According to the present invention, with the above-mentioned constitution, it is possible to prevent connection failure such as open or short circuit without particularly controlling the flux application amount, thereby significantly improving the assembly yield. As a result, the package cost is reduced and the connection test is simplified.

[Brief description of drawings]

FIG. 1 is a plan view of a chip according to an embodiment of the first invention.

FIG. 2 is a plan view of a mounting board used in the present invention.

FIG. 3 is a characteristic diagram showing the bump density dependency of the bump crush amount of the present invention.

FIG. 4 is a plan view of a chip according to an embodiment of the second invention.

FIG. 5 is a plan view of a chip according to an embodiment of the third invention.

FIG. 6 is a characteristic diagram showing the relationship between the number of bumps on the chip of the present invention and the bump density.

FIG. 7 is a cross-sectional view of the chip before mounting of the present invention.

FIG. 8 is a cross-sectional view of a mounting board before mounting of the present invention.

FIG. 9 is a cross-sectional view of a mounting board before mounting of the present invention.

FIG. 10 is a cross-sectional view of a chip and a mounting substrate during mounting of the present invention.

FIG. 11 is a flowchart of the manufacturing method of the present invention.

FIG. 12 is a sectional view of a conventional semiconductor memory device.

FIG. 13 is a plan view of a conventional semiconductor memory device.

FIG. 14 is a sectional view of a conventional semiconductor memory device.

FIG. 15 is a plan view of a conventional chip.

FIG. 16 is a cross-sectional view illustrating bump collapse in flip chip connection.

[Explanation of symbols]

1 ... Chip, 2 ... Mounting board, 3 ...
Solder bump, 4 ... Resin encapsulant, 5 ... Flux, 7 ... Chip-side pad, 8, 13, 15 ...
.. Pads on the mounting board side, 9 ... Solder resist, 10 ... Wiring on the mounting board, 11 ... Insulating film, 12, 14, 16 ... Barrier metal, 31.
..Dummy bumps.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhide Doi 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center (72) Inventor Takashi Okada Toshiba, Komukai-ku, Kawasaki-shi, Kanagawa No. 1 in the Town, Toshiba Research & Development Center Co., Ltd. (72) Inventor Yoichi Hikita One Komachi, Komukai-shi, Kawasaki City, Kanagawa Prefecture No. 1 Toshiba Research & Development Center, Co., Ltd. Komukai Toshiba Town No. 1 In Toshiba Research and Development Center (72) Inventor Hiroshi Tazawa Komukai Toshiba No. 1 in Kawasaki City, Kanagawa Prefecture Komukai Toshiba Research and Development Center (72) Inventor Tomoaki Takubo Kawasaki City, Kanagawa Prefecture Komukai-Toshiba-cho, Saiwai-ku, Toshiba Research & Development Center (72) Inventor Koji Shibasaki Kawasaki-ku, Kawasaki-shi, Kanagawa Maehonmachi 25-1 TOSHIBA MICRO ELECTRONICS CORP. In-house (56) Reference JP 7-335694 (JP, A) JP 7-263449 (JP, A) JP 58-53837 (JP, A) Special Kaihei 3-211838 (JP, A) JP-A-4-373131 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/60 H01L 27/10

Claims (5)

(57) [Claims] 1. A mounting board having a plurality of connection electrodes electrically connected to wiring formed on a surface thereof, a semiconductor memory device having a plurality of connection electrodes formed thereon, and a connection electrode of the mounting board. And solder bumps for connecting the connection electrodes of the semiconductor memory element, and dummy bumps provided between the mounting substrate and the semiconductor memory element that do not contribute to electrical connection, and the solder bumps and the dummy bumps are combined. number bump is adjusted such that the said semiconductor memory element and said mounting substrate in a predetermined bump density without occurrence of collapse bumps in flip-chip connection, the bump dense
The degree is 1.9 with respect to the area of the semiconductor memory device.
/ Mm ² or more, a semiconductor memory device characterized by being. 2. An electrical connection to a wiring formed on the surface
A mounting substrate on which a plurality of connection electrodes are formed, a semiconductor memory element on which a plurality of connection electrodes are formed, and a connection electrode between the mounting substrate and the semiconductor memory element
It is provided between a solder bump connecting the electrode and the mounting substrate and the semiconductor memory element.
And a dummy bump that does not contribute to electrical connection, and is a bump that combines the solder bump and the dummy bump.
The number of chips is set between the semiconductor memory device and the mounting board.
Predetermined that bump crushing does not occur when connecting chips
The surface of the mounting board on which the wiring is formed is covered with a solder resist, and an opening is formed in the solder resist so that the connection electrodes of the mounting board are exposed. This is an individual opening method in which the openings are formed in each of the connection electrodes of the mounting substrate, and the bump density of the bumps composed of the solder bumps and the dummy bumps is, with respect to the area of the semiconductor memory element, 1. A semiconductor memory device characterized in that the number is 1.1 pieces / mm ² or more. 3. An electrical connection to a wiring formed on the surface
A mounting substrate on which a plurality of connection electrodes are formed, a semiconductor memory element on which a plurality of connection electrodes are formed, and a connection electrode between the mounting substrate and the semiconductor memory element
It is provided between a solder bump connecting the electrode and the mounting substrate and the semiconductor memory element.
And a dummy bump that does not contribute to electrical connection, and is a bump that combines the solder bump and the dummy bump.
The number of chips is set between the semiconductor memory device and the mounting board.
Predetermined that bump crushing does not occur when connecting chips
The surface of the mounting board on which the wiring is formed is covered with a solder resist, and an opening is formed in the solder resist so that the connection electrodes of the mounting board are exposed. And open this
The opening is a continuous opening method in which a plurality of connection electrodes of the mounting substrate are exposed in one opening, and a bump density of bumps composed of the solder bumps and the dummy bumps is, with respect to an area of the semiconductor memory device, A semiconductor memory device characterized by being 1.9 pieces / mm ² or more. 4. The plurality of dummy bumps are arranged in a peripheral portion of the surface of the semiconductor memory device, and the dummy bumps are arranged symmetrically with respect to the center of the surface of the semiconductor memory device. 1 to claim 3
The semiconductor memory device according to any one of 1. 5. A step of designing a circuit of a semiconductor memory device and determining the number of bumps required for a semiconductor memory device or a mounting substrate or both based on the design, and a bump density of the semiconductor memory device or the mounting substrate. Is set to a predetermined value that does not exceed the crush amount limit, and the number of bumps that corresponds to this value is determined, and the number of bumps that corresponds to the predetermined value that does not exceed the crush amount limit and the necessary bumps based on the design A step of calculating a difference between the number and the number of dummy bumps used in this semiconductor memory device, and a step of forming the predetermined number of solder bumps and dummy bumps at predetermined positions of a semiconductor memory device or a mounting substrate, A step of applying flux to the mounting board and flip-chip connecting the semiconductor memory element to the mounting board by bump reflow. The method of manufacturing a semiconductor memory device which.