JP4934935B2 - Solid-state imaging device - Google Patents

Solid-state imaging device Download PDF

Info

Publication number
JP4934935B2
JP4934935B2 JP2001285942A JP2001285942A JP4934935B2 JP 4934935 B2 JP4934935 B2 JP 4934935B2 JP 2001285942 A JP2001285942 A JP 2001285942A JP 2001285942 A JP2001285942 A JP 2001285942A JP 4934935 B2 JP4934935 B2 JP 4934935B2
Authority
JP
Japan
Prior art keywords
dummy
solid
semiconductor substrate
imaging device
state imaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001285942A
Other languages
Japanese (ja)
Other versions
JP2003100999A (en
Inventor
啓二 笹野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2001285942A priority Critical patent/JP4934935B2/en
Publication of JP2003100999A publication Critical patent/JP2003100999A/en
Application granted granted Critical
Publication of JP4934935B2 publication Critical patent/JP4934935B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

【０００１】
【発明の属する技術分野】
本発明は固体撮像装置に関し、透明基板に固体撮像素子を取り付けて構成した固体撮像装置に関するものである。
【０００２】
【従来の技術】
図４の（Ａ）は従来の固体撮像装置を示す平面図、（Ｂ）は固体撮像素子固定用の接着剤を塗布する前の固体撮像装置を示す平面図である。また、図５は従来の固体撮像素子の側面図であり、接着剤を塗布する前の状態を示している。
図４、図５に示したように、従来の固体撮像装置１０２は、平面視矩形の半導体基板１０４から成る固体撮像素子１０６を透明基板１０８に固定して構成されている。半導体基板１０４は、その表面中央部に矩形の撮像領域１１０が形成され、かつ撮像領域１１０を挟んむ２つの辺部にそれぞれ複数の電極パッド１１２が配列されている。透明基板１０８は、その表面に複数の配線パターン１１４が形成され、半導体基板１０４および透明基板１０８は板面を相互に対向させるとともに半導体基板１０４の電極パッド１１２が透明基板１０８の配線パターン１１４に対向する状態で配置され、各電極パッド１１２はバンプ１１６を介して対応する配線パターン１１４に電気的および機械的に接続されている。そして、半導体基板１０４の裏面における周辺部と同裏面周辺部に隣接する透明基板１０８上の箇所とに接着剤１１８が塗布され、半導体基板１０４が透明基板１０８に固定されるとともに、半導体基板表面と透明基板１０８との間の隙間空間１０９の気密性が確保されている。
【０００３】
【発明が解決しようとする課題】
ところで、固体撮像素子１０６に形成される電極パッド１１２の数は通常、２０以下と少ないため、各電極パッド１１２をバンプ１１６を介して透明基板１０８上の配線パターン１１４に接合しても、得られる接合強度は不充分であり、半導体基板１０４が接着剤１１８により上述のように透明基板１０８に固定されていても、強い熱的衝撃や機械的衝撃が加わった場合に接続不良が生じる場合があった。
【０００４】
また、硬化前の接着剤１１８を半導体基板１０４および透明基板１０８に塗布した際に、バンプ１１６などの間から接着剤１１８が半導体基板１０４と透明基板１０８との間の隙間に流れ込み、撮像領域１１０にかかってしまう場合があった。特に半導体基板１０４の、バンプ１１６が配列されている辺部に直交する辺部１０４Ａでは、遮るものがないため接着剤１１８が流入し易かった。このように接着剤１１８が撮像領域１１０にまで流入すると撮像領域１１０への入射光が接着剤１１８により阻止されることから固体撮像装置１０２は不良品となってしまい、製造歩留まりの低下を招く結果となっていた。
【０００５】
本発明はこのような問題を解決するためになされたもので、その目的は、固体撮像素子を透明基板に強固に固定して熱的衝撃や機械的衝撃に対する耐性を高め、かつ接着剤が撮像領域にまで流入することによる不具合の発生を防止した固体撮像装置を提供することにある。
【０００６】
【課題を解決するための手段】
本発明は上記目的を達成するため、固体撮像素子を透明基板に固定して構成され、前記固体撮像素子が半導体基板から成り、前記半導体基板は、その表面中央部に撮像領域が形成され、かつ前記撮像領域の周辺に複数の電極パッドが配列されており、前記透明基板は、その表面に複数の配線パターンが形成され、前記半導体基板および前記透明基板は板面を相互に対向させるとともに前記半導体基板の前記電極パッドが前記透明基板の前記配線パターンに対向する状態で配置され、各電極パッドはバンプを介して対応する前記配線パターンに電気的および機械的に接続され、前記半導体基板の裏面における周辺部と同裏面周辺部に隣接する前記透明基板上の箇所とに接着剤を塗布して前記半導体基板が前記透明基板に固定されている固体撮像装置であって、前記半導体基板は、その表面の各電極パッドの間に配列された複数のダミー電極パッドと、各ダミー電極パッド上に配置されたダミーバンプとを備え、前記透明基板は、前記ダミー電極パッドに対向する箇所にダミー配線パターンを備え、前記ダミー電極パッドと前記ダミー配線パターンとは前記ダミーバンプを介して相互に電気的および機械的に接続されていることを特徴とする。
【０００７】
本発明では、本来の電極パッドとともにダミー電極パッドが半導体基板に配置され、ダミー電極パッドはダミーバンプを介して半導体基板上の対応するダミー配線に接続されている。したがって、半導体基板はこれらのダミー電極パッド、ダミーバンプ、ダミー配線によっても透明基板に機械的に接続されることになり、従来より強固に透明基板に固定される。その結果、固体撮像装置の熱的衝撃や機械的衝撃に対する耐性が向上する。
また、本来のバンプなどとともにダミーバンプなどが配列されていることから、硬化前の接着剤を半導体基板の周囲に塗布した際に、接着剤は本来のバンプなどとともにダミーバンプなどによっても半導体基板下へ流入することが阻止される。よって、接着剤が撮像領域にまで流入することによる不具合の発生を防止することができる。
【０００８】
【発明の実施の形態】
次に本発明の実施の形態例について図面を参照して説明する。
図１は本発明による固体撮像装置の一例を示す平面図、図２は実施の形態例の固体撮像装置を示す側面図であり、いずれも固体撮像素子を固定するための接着剤を塗布する前の状態を示している。なお、図中、図４、図５と同一の要素には同一の符号が付されている。
図１、図２に示した実施の形態例の固体撮像装置２は、平面視矩形の半導体基板１０４から成る固体撮像素子４を透明基板１０８に固定して構成されている。半導体基板１０４は、その表面中央部に矩形の撮像領域１１０が形成され、かつ撮像領域１１０を挟んむ２つの辺部にそれぞれ複数の電極パッド１１２が配列され、電極パッド１１２上にはバンプ１１６がそれぞれ配置されている。さらに、本実施の形態例では、電極パッド１１２の間の箇所など、電極パッド１１２に隣接してにダミー電極パッド６が配列され、各ダミー電極パッド６上にダミーバンプ８が配置されている。ダミー電極パッド６は電気的な機能を持たず、ダミー電極パッド６を通じて信号が入力あるいは出力されたり、電源供給が行われることはない。
電極パッド１１２およびダミー電極パッド６は一例としてアルミニウムにより形成され、バンプ１１６およびダミーバンプ８は、一例として金によるボールバンプとして形成されている。
【０００９】
透明基板１０８は、一例としてガラス板から成り、その表面に複数の配線パターン１１４とともに、ダミー電極パッド６に対向する箇所にダミー配線パターン１０が形成されている。ダミー配線パターン１０は電気的な機能を持たず、ダミー電極パッド６を通じて固体撮像素子４に信号が入力あるいは出力されたり、電源供給が行われることはない。
配線パターン１１４の一方の端部はアウターリード部１２として透明基板１０８の端部に配列され、もう一方の端部はインナーリード部１４として半導体基板１０４の電極パッド１１２に対向する箇所に配列されている。一方、ダミー配線パターン１０は、ダミー電極パッド６（したがってダミーバンプ８）に対応する箇所にのみ形成されている。配線パターン１１４およびダミー配線パターン１０は、本実施の形態例では、一例としてアルミニウムにより形成されている。なお、アルミニウム以外にもたとえば金によりこれらの配線パターン１１４を形成することも可能である。アウターリード部１２は、たとえばフレキシブル回路基板などを接続する際に、フレキシブル回路基板上の各配線を接続するための電極となる。
【００１０】
半導体基板１０４および透明基板１０８は、板面を相互に対向させるとともに半導体基板１０４の電極パッド１１２およびダミー電極パッド６が透明基板１０８の配線パターン１１４およびダミー配線パターン１０に対向する状態で配置され、各電極パッド１１２およびダミー電極パッド６はバンプ１１６およびダミーバンプ８を介して対応する配線パターン１１４およびダミー配線パターン１０に電気的および機械的に接続されている。
【００１１】
そして、半導体基板１０４の裏面における周辺部と同裏面周辺部に隣接する透明基板１０８上の箇所とに、半導体基板１０４の全周にわたり、たとえば合成樹脂製の接着剤（図示せず）が塗布され、半導体基板１０４が透明基板１０８に固定されるとともに、半導体基板表面と透明基板１０８との間の隙間空間の気密性が確保されている。なお、接着剤を塗布した後の固体撮像装置２は、図４の（Ａ）に示した従来の固体撮像装置と同様の形態となる。
【００１２】
バンプ１１６およびダミーバンプ８を介した半導体基板１０４の透明基板１０８への接合は、たとえば超音波圧着により行うことができる。その際、半導体基板１０４および透明基板１０８のいずれか一方または両方を加熱して、より強固な接合を図ることも有効である。
また、バンプ１１６およびダミーバンプ８を電極パッド１１２およびダミー電極パッド６の上にそれぞれ形成した際、バンプの高さを均一にするレベリング加工を行って、バンプ１１６およびダミーバンプ８を介した半導体基板１０４と透明基板１０８との接合をより確実なものとするよう図ることも有効である。
【００１３】
上記接着剤としては紫外線硬化型あるいは熱硬化型のものを用いることができ、硬化前の接着剤を半導体基板１０４の周囲に塗布した後、紫外線を照射するか、または熱を加えて接着剤を硬化させ、半導体基板１０４を透明基板１０８に固定することができる。
【００１４】
このように、本実施の形態例では、半導体基板１０４には、本来の電極パッド１１２とともにダミー電極パッド６が配置され、ダミー電極パッド６はダミーバンプ８を介して半導体基板１０４上の対応するダミー配線パターン１０に接続されている。したがって、半導体基板１０４はこれらのダミー電極パッド６、ダミーバンプ８、ダミー配線パターン１０によっても透明基板１０８に機械的に接続されることになり、従来より強固に透明基板１０８に固定される。その結果、固体撮像装置２の熱的衝撃や機械的衝撃に対する耐性が向上する。
【００１５】
また、本来のバンプ１１６などとともにダミーバンプ８などが配置されるため、硬化前の接着剤を半導体基板１０４の周囲に塗布した際に、接着剤はダミーバンプ８や、ダミー電極パッド６、ダミー配線パターン１０によっても半導体基板１０４下へ流入することが阻止される。よって、接着剤が撮像領域１１０にまで流入することによる不具合の発生を防止することができる。
【００１６】
次に、本発明の第２の実施の形態例について説明する。
図３は、本発明の第２の実施の形態例を示す平面図であり、接着剤を塗布する前の状態を示している。図中、図１などと同一の要素には同一の符号が付されている。
この第２の実施の形態例の固体撮像装置１６が、上記実施の形態例の固体撮像装置２と異なるのは、半導体基板表面の上記電極パッド１１２、バンプ１１６、ダミー電極パッド６、ダミーバンプ８が配列された辺部に直交する両辺部１１４Ａにも、複数のダミー電極パッド６およびダミーバンプ８がそれぞれ配列されている点である。各ダミー電極パッド６（したがってダミーバンプ８）に対向する透明基板１０８上の箇所にはダミー配線パターン１０が形成されて、対応するダミー電極パッド６とダミー配線パターン１０とがダミーバンプ８を介して接続されている。
【００１７】
したがって、第２の実施の形態例では、半導体基板１０４は辺部１０４Ａに配列されたこれらのダミー電極パッド６、ダミーバンプ８、ダミー配線パターン１０によっても透明基板１０８に機械的に接続されることになり、固体撮像装置２の場合より強固に透明基板１０８に固定される。その結果、固体撮像装置の熱的衝撃や機械的衝撃に対する耐性がさらに向上する。
また、辺部１１４Ａにもダミーバンプ８などが配置されるため、硬化前の接着剤を半導体基板１０４の周囲に塗布した際に、接着剤は辺部１１４Ａの箇所から半導体基板１０４下へ流入することが阻止される。よって、接着剤が撮像領域１１０にまで流入することによる不具合の発生をより確実に防止することができる。
【００１８】
【発明の効果】
以上説明したように本発明では、本来の電極パッドとともにダミー電極パッドが半導体基板に配置され、ダミー電極パッドはダミーバンプを介して半導体基板上の対応するダミー配線に接続されている。したがって、半導体基板はこれらのダミー電極パッド、ダミーバンプ、ダミー配線によっても透明基板に機械的に接続されることになり、従来より強固に透明基板に固定される。その結果、固体撮像装置の熱的衝撃や機械的衝撃に対する耐性が向上する。
また、本来のバンプなどとともにダミーバンプなどが配列されていることから、硬化前の接着剤を半導体基板の周囲に塗布した際に、接着剤は本来のバンプなどとともにダミーバンプなどによっても半導体基板下へ流入することが阻止される。よって、接着剤が撮像領域にまで流入することによる不具合の発生を防止することができる。
【図面の簡単な説明】
【図１】本発明による固体撮像装置の一例を示す平面図である。
【図２】本発明による固体撮像装置の一例を示す側面図である。
【図３】本発明の第２の実施の形態例を示す平面図である。
【図４】（Ａ）および（Ｂ）は従来の固体撮像装置を示す平面図である。
【図５】従来の固体撮像装置を示す側面図である。
【符号の説明】
２、１０２……固体撮像装置、４、１０６……固体撮像素子、６……ダミー電極パッド、８……ダミーバンプ、１０……ダミー配線パターン、１２……アウターリード部、１４……インナーリード部、１０４……半導体基板、１０８……透明基板、１１０……撮像領域、１１２……電極パッド、１１４……配線パターン、１１６……バンプ、１１８……接着剤。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and relates to a solid-state imaging device configured by attaching a solid-state imaging element to a transparent substrate.
[0002]
[Prior art]
4A is a plan view showing a conventional solid-state imaging device, and FIG. 4B is a plan view showing the solid-state imaging device before applying an adhesive for fixing a solid-state imaging device. FIG. 5 is a side view of a conventional solid-state imaging device, showing a state before applying an adhesive.
As shown in FIGS. 4 and 5, the conventional solid-state imaging device 102 is configured by fixing a solid-state imaging device 106 composed of a semiconductor substrate 104 having a rectangular shape in plan view to a transparent substrate 108. The semiconductor substrate 104 has a rectangular imaging area 110 formed at the center of the surface thereof, and a plurality of electrode pads 112 are arranged on each of two sides sandwiching the imaging area 110. The transparent substrate 108 has a plurality of wiring patterns 114 formed on the surface thereof, and the semiconductor substrate 104 and the transparent substrate 108 have their plate surfaces facing each other, and the electrode pads 112 of the semiconductor substrate 104 are opposed to the wiring patterns 114 of the transparent substrate 108. Each electrode pad 112 is electrically and mechanically connected to a corresponding wiring pattern 114 via a bump 116. Then, an adhesive 118 is applied to a peripheral portion on the back surface of the semiconductor substrate 104 and a location on the transparent substrate 108 adjacent to the back surface peripheral portion, so that the semiconductor substrate 104 is fixed to the transparent substrate 108 and the semiconductor substrate surface The airtightness of the gap space 109 with the transparent substrate 108 is ensured.
[0003]
[Problems to be solved by the invention]
By the way, since the number of electrode pads 112 formed on the solid-state imaging device 106 is usually as small as 20 or less, it can be obtained even if each electrode pad 112 is bonded to the wiring pattern 114 on the transparent substrate 108 via the bump 116. The bonding strength is insufficient, and even if the semiconductor substrate 104 is fixed to the transparent substrate 108 with the adhesive 118 as described above, connection failure may occur when a strong thermal shock or mechanical shock is applied. It was.
[0004]
In addition, when the adhesive 118 before curing is applied to the semiconductor substrate 104 and the transparent substrate 108, the adhesive 118 flows into the gap between the semiconductor substrate 104 and the transparent substrate 108 from between the bumps 116 and the like, and the imaging region 110. There was a case that it was over. In particular, in the side portion 104A orthogonal to the side portion where the bumps 116 are arranged on the semiconductor substrate 104, there is nothing to block, and thus the adhesive 118 easily flows. As described above, when the adhesive 118 flows into the imaging region 110, the incident light to the imaging region 110 is blocked by the adhesive 118, so that the solid-state imaging device 102 becomes a defective product, resulting in a decrease in manufacturing yield. It was.
[0005]
The present invention has been made to solve such problems. The object of the present invention is to firmly fix a solid-state imaging device to a transparent substrate to increase resistance to thermal shock and mechanical shock, and an adhesive image is taken. An object of the present invention is to provide a solid-state imaging device that prevents the occurrence of problems due to inflow into a region.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured by fixing a solid-state imaging device to a transparent substrate, the solid-state imaging device is composed of a semiconductor substrate, and the semiconductor substrate has an imaging region formed at the center of the surface thereof, and A plurality of electrode pads are arranged in the periphery of the imaging region, and the transparent substrate has a plurality of wiring patterns formed on the surface thereof, and the semiconductor substrate and the transparent substrate have the plate surfaces facing each other and the semiconductor The electrode pads of the substrate are arranged in a state of facing the wiring pattern of the transparent substrate, and each electrode pad is electrically and mechanically connected to the corresponding wiring pattern via a bump, on the back surface of the semiconductor substrate Solid-state imaging in which the semiconductor substrate is fixed to the transparent substrate by applying an adhesive to a peripheral portion and a portion on the transparent substrate adjacent to the peripheral portion A location, the semiconductor substrate includes a plurality of dummy electrode pads arranged between the electrode pads of the surface, and a dummy bump disposed on each dummy electrode pads, the transparent substrate, the dummy A dummy wiring pattern is provided at a position facing the electrode pad, and the dummy electrode pad and the dummy wiring pattern are electrically and mechanically connected to each other through the dummy bump.
[0007]
In the present invention, dummy electrode pads are arranged on a semiconductor substrate together with original electrode pads, and the dummy electrode pads are connected to corresponding dummy wirings on the semiconductor substrate via dummy bumps. Therefore, the semiconductor substrate is mechanically connected to the transparent substrate also by these dummy electrode pads, dummy bumps, and dummy wirings, and is more firmly fixed to the transparent substrate than before. As a result, the resistance of the solid-state imaging device to thermal shock and mechanical shock is improved.
In addition, since the dummy bumps are arranged along with the original bumps, when the adhesive before curing is applied around the semiconductor substrate, the adhesive also flows under the semiconductor substrate by the dummy bumps together with the original bumps. To be prevented. Therefore, it is possible to prevent the occurrence of problems due to the adhesive flowing into the imaging region.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a plan view showing an example of a solid-state imaging device according to the present invention, and FIG. 2 is a side view showing the solid-state imaging device of an embodiment, both before applying an adhesive for fixing the solid-state imaging device. Shows the state. In addition, in the figure, the same code | symbol is attached | subjected to the element same as FIG. 4, FIG.
The solid-state imaging device 2 according to the embodiment shown in FIGS. 1 and 2 is configured by fixing a solid-state imaging device 4 including a semiconductor substrate 104 having a rectangular shape in plan view to a transparent substrate 108. The semiconductor substrate 104 has a rectangular imaging region 110 formed at the center of the surface thereof, and a plurality of electrode pads 112 are arranged on two sides sandwiching the imaging region 110, and bumps 116 are formed on the electrode pads 112. Each is arranged. Further, in the present embodiment, dummy electrode pads 6 are arranged adjacent to the electrode pads 112 such as portions between the electrode pads 112, and dummy bumps 8 are arranged on the dummy electrode pads 6. The dummy electrode pad 6 does not have an electrical function, and no signal is input or output through the dummy electrode pad 6 or power supply is not performed.
The electrode pad 112 and the dummy electrode pad 6 are formed of aluminum as an example, and the bump 116 and the dummy bump 8 are formed of ball bumps of gold as an example.
[0009]
The transparent substrate 108 is made of, for example, a glass plate, and a dummy wiring pattern 10 is formed on the surface of the transparent substrate 108 at a location facing the dummy electrode pad 6 together with a plurality of wiring patterns 114. The dummy wiring pattern 10 does not have an electrical function, and no signal is input to or output from the solid-state imaging device 4 through the dummy electrode pad 6, and power is not supplied.
One end portion of the wiring pattern 114 is arranged as an outer lead portion 12 on the end portion of the transparent substrate 108, and the other end portion is arranged as an inner lead portion 14 at a position facing the electrode pad 112 of the semiconductor substrate 104. Yes. On the other hand, the dummy wiring pattern 10 is formed only at a location corresponding to the dummy electrode pad 6 (and hence the dummy bump 8). In the present embodiment, the wiring pattern 114 and the dummy wiring pattern 10 are formed of aluminum as an example. In addition to aluminum, these wiring patterns 114 can be formed of gold, for example. The outer lead portion 12 serves as an electrode for connecting each wiring on the flexible circuit board when, for example, a flexible circuit board is connected.
[0010]
The semiconductor substrate 104 and the transparent substrate 108 are disposed in such a manner that the plate surfaces face each other and the electrode pads 112 and the dummy electrode pads 6 of the semiconductor substrate 104 face the wiring patterns 114 and the dummy wiring patterns 10 of the transparent substrate 108. Each electrode pad 112 and dummy electrode pad 6 are electrically and mechanically connected to the corresponding wiring pattern 114 and dummy wiring pattern 10 via bumps 116 and dummy bumps 8.
[0011]
Then, for example, a synthetic resin adhesive (not shown) is applied to the peripheral portion of the back surface of the semiconductor substrate 104 and the portion on the transparent substrate 108 adjacent to the peripheral portion of the back surface over the entire periphery of the semiconductor substrate 104. The semiconductor substrate 104 is fixed to the transparent substrate 108, and the airtightness of the gap space between the semiconductor substrate surface and the transparent substrate 108 is ensured. The solid-state imaging device 2 after applying the adhesive has the same form as the conventional solid-state imaging device shown in FIG.
[0012]
The bonding of the semiconductor substrate 104 to the transparent substrate 108 via the bumps 116 and the dummy bumps 8 can be performed by, for example, ultrasonic pressure bonding. At that time, it is also effective to heat one or both of the semiconductor substrate 104 and the transparent substrate 108 to achieve stronger bonding.
Further, when the bump 116 and the dummy bump 8 are formed on the electrode pad 112 and the dummy electrode pad 6, respectively, leveling processing is performed to make the height of the bump uniform, and the semiconductor substrate 104 with the bump 116 and the dummy bump 8 interposed therebetween. It is also effective to make the bonding with the transparent substrate 108 more reliable.
[0013]
As the adhesive, an ultraviolet curing type or a thermosetting type can be used. After the adhesive before curing is applied around the semiconductor substrate 104, the adhesive is irradiated with ultraviolet rays or heat is applied. The semiconductor substrate 104 can be fixed to the transparent substrate 108 by being cured.
[0014]
As described above, in this embodiment, the dummy electrode pad 6 is arranged together with the original electrode pad 112 on the semiconductor substrate 104, and the dummy electrode pad 6 corresponds to the corresponding dummy wiring on the semiconductor substrate 104 via the dummy bump 8. Connected to the pattern 10. Therefore, the semiconductor substrate 104 is mechanically connected to the transparent substrate 108 also by the dummy electrode pads 6, the dummy bumps 8, and the dummy wiring pattern 10, and is more firmly fixed to the transparent substrate 108 than in the past. As a result, the resistance of the solid-state imaging device 2 to thermal shock and mechanical shock is improved.
[0015]
Since the dummy bumps 8 and the like are arranged together with the original bumps 116 and the like, when the adhesive before curing is applied around the semiconductor substrate 104, the adhesive is the dummy bumps 8, the dummy electrode pads 6, and the dummy wiring patterns 10. Also prevents the semiconductor substrate 104 from flowing under. Therefore, it is possible to prevent the occurrence of problems due to the adhesive flowing into the imaging region 110.
[0016]
Next, a second embodiment of the present invention will be described.
FIG. 3 is a plan view showing a second embodiment of the present invention, and shows a state before an adhesive is applied. In the figure, the same elements as those in FIG.
The solid-state imaging device 16 of the second embodiment is different from the solid-state imaging device 2 of the above-described embodiment in that the electrode pad 112, the bump 116, the dummy electrode pad 6, and the dummy bump 8 on the surface of the semiconductor substrate. A plurality of dummy electrode pads 6 and dummy bumps 8 are also arranged on both sides 114A orthogonal to the arranged sides. A dummy wiring pattern 10 is formed at a position on the transparent substrate 108 facing each dummy electrode pad 6 (and hence the dummy bump 8), and the corresponding dummy electrode pad 6 and dummy wiring pattern 10 are connected via the dummy bump 8. ing.
[0017]
Therefore, in the second embodiment, the semiconductor substrate 104 is mechanically connected to the transparent substrate 108 by the dummy electrode pads 6, the dummy bumps 8, and the dummy wiring patterns 10 arranged in the side portion 104A. Thus, it is fixed to the transparent substrate 108 more firmly than in the case of the solid-state imaging device 2. As a result, the resistance of the solid-state imaging device to thermal shock and mechanical shock is further improved.
In addition, since the dummy bumps 8 and the like are also arranged on the side portion 114A, when the adhesive before curing is applied around the semiconductor substrate 104, the adhesive flows from the location of the side portion 114A to the bottom of the semiconductor substrate 104. Is blocked. Therefore, it is possible to more reliably prevent the occurrence of problems due to the adhesive flowing into the imaging region 110.
[0018]
【Effect of the invention】
As described above, in the present invention, the dummy electrode pad is disposed on the semiconductor substrate together with the original electrode pad, and the dummy electrode pad is connected to the corresponding dummy wiring on the semiconductor substrate via the dummy bump. Therefore, the semiconductor substrate is mechanically connected to the transparent substrate also by these dummy electrode pads, dummy bumps, and dummy wirings, and is more firmly fixed to the transparent substrate than before. As a result, the resistance of the solid-state imaging device to thermal shock and mechanical shock is improved.
In addition, since the dummy bumps are arranged along with the original bumps, when the adhesive before curing is applied around the semiconductor substrate, the adhesive also flows under the semiconductor substrate by the dummy bumps together with the original bumps. To be prevented. Therefore, it is possible to prevent the occurrence of problems due to the adhesive flowing into the imaging region.
[Brief description of the drawings]
FIG. 1 is a plan view showing an example of a solid-state imaging device according to the present invention.
FIG. 2 is a side view showing an example of a solid-state imaging device according to the present invention.
FIG. 3 is a plan view showing a second embodiment of the present invention.
4A and 4B are plan views showing a conventional solid-state imaging device. FIG.
FIG. 5 is a side view showing a conventional solid-state imaging device.
[Explanation of symbols]
2, 102... Solid-state imaging device 4, 106... Solid-state imaging device, 6... Dummy electrode pad, 8. , 104... Semiconductor substrate, 108... Transparent substrate, 110... Imaging area, 112... Electrode pad, 114.

Claims (9)

固体撮像素子を透明基板に固定して構成され、前記固体撮像素子は半導体基板から成り、前記半導体基板は、その表面中央部に撮像領域が形成され、かつ前記撮像領域の周辺に複数の電極パッドが配列されており、前記透明基板は、その表面に複数の配線パターンが形成され、前記半導体基板および前記透明基板は板面を相互に対向させるとともに前記半導体基板の前記電極パッドが前記透明基板の前記配線パターンに対向する状態で配置され、各電極パッドはバンプを介して対応する前記配線パターンに電気的および機械的に接続され、前記半導体基板の裏面における周辺部と同裏面周辺部に隣接する前記透明基板上の箇所とに接着剤を塗布して前記半導体基板が前記透明基板に固定されている固体撮像装置であって、
前記半導体基板は、その表面の各電極パッドの間に配列された複数のダミー電極パッドと、各ダミー電極パッド上に配置されたダミーバンプとを備え、
前記透明基板は、前記ダミー電極パッドに対向する箇所にダミー配線パターンを備え、
前記ダミー電極パッドと前記ダミー配線パターンとは前記ダミーバンプを介して相互に電気的および機械的に接続されている固体撮像装置。A solid-state image sensor is fixed to a transparent substrate, and the solid-state image sensor is composed of a semiconductor substrate. The semiconductor substrate has an image area formed at the center of the surface thereof, and a plurality of electrode pads around the image area. The transparent substrate has a plurality of wiring patterns formed on a surface thereof, and the semiconductor substrate and the transparent substrate have plate surfaces facing each other, and the electrode pads of the semiconductor substrate are disposed on the transparent substrate. Arranged in a state facing the wiring pattern, each electrode pad is electrically and mechanically connected to the corresponding wiring pattern through a bump, and is adjacent to the peripheral portion on the back surface of the semiconductor substrate and the peripheral portion on the back surface. A solid-state imaging device in which an adhesive is applied to a location on the transparent substrate and the semiconductor substrate is fixed to the transparent substrate,
The semiconductor substrate includes a plurality of dummy electrode pads arranged between the electrode pads on the surface , and dummy bumps disposed on the dummy electrode pads,
The transparent substrate includes a dummy wiring pattern at a location facing the dummy electrode pad,
The dummy electrode pad and the dummy wiring pattern electrically and mechanically connected to have that solid-state image pickup device to each other through the dummy bumps and. 前記電極パッドおよび前記ダミー電極パッドは、前記半導体基板の表面において前記撮像領域を挟む２つの辺部に配列されている請求項１記載の固体撮像装置。The electrode pad and the dummy electrode pads, the solid-state imaging device of the 請 Motomeko 1 wherein that are arranged in two side portions sandwiching the imaging region in the semiconductor substrate surface. 前記ダミー電極パッドは、前記半導体基板の表面において前記辺部に直交する他の辺部にも配列されている請求項２記載の固体撮像装置。The dummy electrode pads, the solid-state imaging device of the side portions also arranged in the other side portion which is perpendicular to that have that請 Motomeko 2 wherein the surface of said semiconductor substrate. 前記配線パターンの一方の端部はアウターリード部として前記透明基板の端部に配列され、もう一方の端部はインナーリード部として前記半導体基板の前記電極パッドに対向する箇所に配列されている請求項１記載の固体撮像装置。One end of the wiring pattern is arranged on an end portion of the transparent substrate as an outer lead portion, that has the other end portion is arranged at a position facing the electrode pad of the semiconductor substrate as an inner lead portion 請 The solid-state imaging device according to claim 1. 前記電極パッドおよび前記ダミー電極パッドはアルミニウムにより形成されている請求項１記載の固体撮像装置。The solid-state imaging device 請 Motomeko 1, wherein said electrode pad and said dummy electrode pads that are formed of aluminum. 前記バンプおよび前記ダミーバンプは金により形成されている請求項１記載の固体撮像装置。The solid-state imaging device 請 Motomeko 1 wherein said bump and said dummy bump is that is formed by gold. 前記配線パターンおよび前記ダミー配線パターンはアルミニウムまたは金により形成されている請求項１記載の固体撮像装置。The wiring pattern and the dummy wiring pattern is a solid-state imaging device 請 Motomeko 1 wherein that is formed of aluminum or gold. 前記接着剤は前記半導体基板の全周にわたり塗布されている請求項１記載の固体撮像装置。The adhesive solid-state imaging device 請 Motomeko 1 wherein that is applied over the entire circumference of the semiconductor substrate. 前記透明基板は透明なガラス板により形成されている請求項１記載の固体撮像装置。The transparent substrate is a solid-state imaging device 請 Motomeko 1 wherein that is formed by a transparent glass plate.
JP2001285942A 2001-09-19 2001-09-19 Solid-state imaging device Expired - Fee Related JP4934935B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001285942A JP4934935B2 (en) 2001-09-19 2001-09-19 Solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001285942A JP4934935B2 (en) 2001-09-19 2001-09-19 Solid-state imaging device

Publications (2)

Publication Number Publication Date
JP2003100999A JP2003100999A (en) 2003-04-04
JP4934935B2 true JP4934935B2 (en) 2012-05-23

Family

ID=19109006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001285942A Expired - Fee Related JP4934935B2 (en) 2001-09-19 2001-09-19 Solid-state imaging device

Country Status (1)

Country Link
JP (1) JP4934935B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005252140A (en) * 2004-03-08 2005-09-15 Olympus Corp Package for solid photographing device
JP4677260B2 (en) * 2005-03-23 2011-04-27 富士フイルム株式会社 Manufacturing method of solid-state imaging device
JP4699089B2 (en) * 2005-05-27 2011-06-08 オプトレックス株式会社 Chip-on-film semiconductor device
KR100730077B1 (en) 2005-11-25 2007-06-19 삼성전기주식회사 Image sensor module and camera module package therewith
JP5076315B2 (en) * 2005-12-26 2012-11-21 富士ゼロックス株式会社 Wiring board and flip chip mounting structure
JP6001917B2 (en) * 2012-05-16 2016-10-05 シャープ株式会社 Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2810666B2 (en) * 1988-01-21 1998-10-15 沖電気工業株式会社 Flip chip type semiconductor device and manufacturing method thereof
JP3110886B2 (en) * 1992-08-19 2000-11-20 オリンパス光学工業株式会社 Solid-state imaging device
JP3207319B2 (en) * 1993-05-28 2001-09-10 株式会社東芝 Photoelectric conversion device and method of manufacturing the same
JP3367826B2 (en) * 1996-06-14 2003-01-20 東芝マイクロエレクトロニクス株式会社 Semiconductor memory device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2003100999A (en) 2003-04-04

Similar Documents

Publication Publication Date Title
JP4304163B2 (en) Imaging module and manufacturing method thereof
KR100791730B1 (en) Semiconductor device and production method thereof
KR100546411B1 (en) Flip chip package, image sensor module including the package and method of manufacturing the same
JP6214337B2 (en) Electronic parts, electronic devices, and methods for manufacturing electronic parts.
JP2011086670A (en) Manufacturing method of solid-state image pickup device
JP3376356B2 (en) Thin photosensitive semiconductor device
JPH09260436A (en) Semiconductor device
JP2002246418A (en) Method for mounting semiconductor element and optical information processing unit
JP4934935B2 (en) Solid-state imaging device
JPH10289932A (en) Carrier film and integrated circuit device using thereof
JP3490303B2 (en) Semiconductor device package
JP4556671B2 (en) Semiconductor package and flexible circuit board
KR100485629B1 (en) Method for assembling camera module
JP2008078164A (en) Semiconductor device, and manufacturing method thereof
JP4292383B2 (en) Optical device manufacturing method
US20070164404A1 (en) Semiconductor package
JP4483016B2 (en) Solid-state imaging device and manufacturing method thereof
JPH0786544A (en) Ccd device
US20090310321A1 (en) Printed circuit board and electronic apparatus
JP2756791B2 (en) Resin-sealed semiconductor device
JP2003060114A (en) Semiconductor device and solid-state image pickup device
KR20030085449A (en) An improved flip chip package
JP2006060178A (en) Sensor package
JP4362931B2 (en) Solid-state imaging device
JPH1126634A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080908

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20090817

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091013

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110802

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110811

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110922

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120124

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120206

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150302

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150302

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees