JP2003100999A - Solid state image sensor - Google Patents
Solid state image sensorInfo
- Publication number
- JP2003100999A JP2003100999A JP2001285942A JP2001285942A JP2003100999A JP 2003100999 A JP2003100999 A JP 2003100999A JP 2001285942 A JP2001285942 A JP 2001285942A JP 2001285942 A JP2001285942 A JP 2001285942A JP 2003100999 A JP2003100999 A JP 2003100999A
- Authority
- JP
- Japan
- Prior art keywords
- dummy
- solid
- semiconductor substrate
- transparent substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は固体撮像装置に関
し、透明基板に固体撮像素子を取り付けて構成した固体
撮像装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device having a solid-state image pickup device mounted on a transparent substrate.
【０００２】[0002]
【従来の技術】図４の（Ａ）は従来の固体撮像装置を示
す平面図、（Ｂ）は固体撮像素子固定用の接着剤を塗布
する前の固体撮像装置を示す平面図である。また、図５
は従来の固体撮像素子の側面図であり、接着剤を塗布す
る前の状態を示している。図４、図５に示したように、
従来の固体撮像装置１０２は、平面視矩形の半導体基板
１０４から成る固体撮像素子１０６を透明基板１０８に
固定して構成されている。半導体基板１０４は、その表
面中央部に矩形の撮像領域１１０が形成され、かつ撮像
領域１１０を挟んむ２つの辺部にそれぞれ複数の電極パ
ッド１１２が配列されている。透明基板１０８は、その
表面に複数の配線パターン１１４が形成され、半導体基
板１０４および透明基板１０８は板面を相互に対向させ
るとともに半導体基板１０４の電極パッド１１２が透明
基板１０８の配線パターン１１４に対向する状態で配置
され、各電極パッド１１２はバンプ１１６を介して対応
する配線パターン１１４に電気的および機械的に接続さ
れている。そして、半導体基板１０４の裏面における周
辺部と同裏面周辺部に隣接する透明基板１０８上の箇所
とに接着剤１１８が塗布され、半導体基板１０４が透明
基板１０８に固定されるとともに、半導体基板表面と透
明基板１０８との間の隙間空間１０９の気密性が確保さ
れている。2. Description of the Related Art FIG. 4A is a plan view showing a conventional solid-state image pickup device, and FIG. 4B is a plan view showing the solid-state image pickup device before applying an adhesive for fixing a solid-state image pickup device. Also, FIG.
FIG. 4A is a side view of a conventional solid-state imaging device, showing a state before applying an adhesive. As shown in FIGS. 4 and 5,
The conventional solid-state image pickup device 102 is configured by fixing a solid-state image pickup element 106 made of a semiconductor substrate 104 having a rectangular shape in plan view to a transparent substrate 108. In the semiconductor substrate 104, a rectangular image pickup region 110 is formed in the center of the surface thereof, and a plurality of electrode pads 112 are arranged on each of two sides sandwiching the image pickup region 110. A plurality of wiring patterns 114 are formed on the surface of the transparent substrate 108. The semiconductor substrate 104 and the transparent substrate 108 have their plate surfaces face each other, and the electrode pads 112 of the semiconductor substrate 104 face the wiring pattern 114 of the transparent substrate 108. The electrode pads 112 are electrically and mechanically connected to the corresponding wiring patterns 114 via the bumps 116. Then, the adhesive 118 is applied to the peripheral portion of the back surface of the semiconductor substrate 104 and the portion on the transparent substrate 108 adjacent to the peripheral portion of the back surface, so that the semiconductor substrate 104 is fixed to the transparent substrate 108 and the surface of the semiconductor substrate The airtightness of the gap space 109 with the transparent substrate 108 is ensured.
【０００３】[0003]
【発明が解決しようとする課題】ところで、固体撮像素
子１０６に形成される電極パッド１１２の数は通常、２
０以下と少ないため、各電極パッド１１２をバンプ１１
６を介して透明基板１０８上の配線パターン１１４に接
合しても、得られる接合強度は不充分であり、半導体基
板１０４が接着剤１１８により上述のように透明基板１
０８に固定されていても、強い熱的衝撃や機械的衝撃が
加わった場合に接続不良が生じる場合があった。By the way, the number of electrode pads 112 formed on the solid-state image pickup device 106 is usually two.
Since it is as small as 0 or less, each electrode pad 112 is bump 11
Even if it is bonded to the wiring pattern 114 on the transparent substrate 108 via 6, the obtained bonding strength is insufficient, and the semiconductor substrate 104 is bonded by the adhesive 118 to the transparent substrate 1 as described above.
Even if it was fixed at 08, connection failure could occur when a strong thermal shock or mechanical shock was applied.
【０００４】また、硬化前の接着剤１１８を半導体基板
１０４および透明基板１０８に塗布した際に、バンプ１
１６などの間から接着剤１１８が半導体基板１０４と透
明基板１０８との間の隙間に流れ込み、撮像領域１１０
にかかってしまう場合があった。特に半導体基板１０４
の、バンプ１１６が配列されている辺部に直交する辺部
１０４Ａでは、遮るものがないため接着剤１１８が流入
し易かった。このように接着剤１１８が撮像領域１１０
にまで流入すると撮像領域１１０への入射光が接着剤１
１８により阻止されることから固体撮像装置１０２は不
良品となってしまい、製造歩留まりの低下を招く結果と
なっていた。When the adhesive 118 before curing is applied to the semiconductor substrate 104 and the transparent substrate 108, the bump 1
The adhesive 118 flows into the gap between the semiconductor substrate 104 and the transparent substrate 108 from between 16 and the like, and the imaging region 110
There was a case where Especially the semiconductor substrate 104
In the side portion 104A orthogonal to the side portion where the bumps 116 are arranged, since there is nothing to block, the adhesive 118 easily flows in. In this way, the adhesive 118 is applied to the imaging area 110.
Incident on the adhesive 1
Since the solid-state imaging device 102 is blocked by 18, the solid-state imaging device 102 becomes a defective product, resulting in a decrease in manufacturing yield.
【０００５】本発明はこのような問題を解決するために
なされたもので、その目的は、固体撮像素子を透明基板
に強固に固定して熱的衝撃や機械的衝撃に対する耐性を
高め、かつ接着剤が撮像領域にまで流入することによる
不具合の発生を防止した固体撮像装置を提供することに
ある。The present invention has been made to solve such a problem, and an object thereof is to firmly fix a solid-state image pickup device to a transparent substrate to improve resistance to thermal shock and mechanical shock and to bond the solid-state image pickup device. It is an object of the present invention to provide a solid-state imaging device that prevents the occurrence of defects due to the agent flowing into the imaging region.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するため、固体撮像素子を透明基板に固定して構成さ
れ、前記固体撮像素子が半導体基板から成り、前記半導
体基板は、その表面中央部に撮像領域が形成され、かつ
前記撮像領域の周辺に複数の電極パッドが配列されてお
り、前記透明基板は、その表面に複数の配線パターンが
形成され、前記半導体基板および前記透明基板は板面を
相互に対向させるとともに前記半導体基板の前記電極パ
ッドが前記透明基板の前記配線パターンに対向する状態
で配置され、各電極パッドはバンプを介して対応する前
記配線パターンに電気的および機械的に接続され、前記
半導体基板の裏面における周辺部と同裏面周辺部に隣接
する前記透明基板上の箇所とに接着剤を塗布して前記半
導体基板が前記透明基板に固定されている固体撮像装置
であって、前記半導体基板は、その表面に配列された複
数のダミー電極パッドと、各ダミー電極パッド上に配置
されたダミーバンプとを備え、前記透明基板は、前記ダ
ミー電極パッドに対向する箇所にダミー配線パターンを
備え、前記ダミー電極パッドと前記ダミー配線パターン
とは前記ダミーバンプを介して相互に電気的および機械
的に接続されていることを特徴とする。In order to achieve the above object, the present invention comprises a solid-state image sensor fixed to a transparent substrate, the solid-state image sensor comprises a semiconductor substrate, and the semiconductor substrate has a surface center. A plurality of electrode pads are arranged around the image pickup area, a plurality of wiring patterns are formed on the surface of the transparent substrate, and the semiconductor substrate and the transparent substrate are plates. The electrode pads of the semiconductor substrate are arranged so as to face each other and face the wiring pattern of the transparent substrate, and each electrode pad is electrically and mechanically connected to the corresponding wiring pattern via a bump. The semiconductor substrate is transparent by applying an adhesive to a peripheral portion of the back surface of the semiconductor substrate and a portion on the transparent substrate adjacent to the peripheral portion of the back surface of the semiconductor substrate. A solid-state imaging device fixed to a plate, wherein the semiconductor substrate includes a plurality of dummy electrode pads arranged on the surface thereof and dummy bumps arranged on each dummy electrode pad, and the transparent substrate is A dummy wiring pattern is provided at a position facing the dummy electrode pad, and the dummy electrode pad and the dummy wiring pattern are electrically and mechanically connected to each other via the dummy bump.
【０００７】本発明では、本来の電極パッドとともにダ
ミー電極パッドが半導体基板に配置され、ダミー電極パ
ッドはダミーバンプを介して半導体基板上の対応するダ
ミー配線に接続されている。したがって、半導体基板は
これらのダミー電極パッド、ダミーバンプ、ダミー配線
によっても透明基板に機械的に接続されることになり、
従来より強固に透明基板に固定される。その結果、固体
撮像装置の熱的衝撃や機械的衝撃に対する耐性が向上す
る。また、本来のバンプなどとともにダミーバンプなど
が配列されていることから、硬化前の接着剤を半導体基
板の周囲に塗布した際に、接着剤は本来のバンプなどと
ともにダミーバンプなどによっても半導体基板下へ流入
することが阻止される。よって、接着剤が撮像領域にま
で流入することによる不具合の発生を防止することがで
きる。In the present invention, the dummy electrode pads are arranged on the semiconductor substrate together with the original electrode pads, and the dummy electrode pads are connected to the corresponding dummy wirings on the semiconductor substrate through the dummy bumps. Therefore, the semiconductor substrate is mechanically connected to the transparent substrate by these dummy electrode pads, dummy bumps, and dummy wirings.
It is more firmly fixed to the transparent substrate than before. As a result, the resistance of the solid-state imaging device to thermal shock and mechanical shock is improved. In addition, since the dummy bumps are arranged along with the original bumps, when the adhesive before curing is applied around the semiconductor substrate, the adhesive also flows under the semiconductor substrate due to the dummy bumps along with the original bumps. Is prevented. Therefore, it is possible to prevent the occurrence of defects caused by the adhesive flowing into the imaging region.
【０００８】[0008]
【発明の実施の形態】次に本発明の実施の形態例につい
て図面を参照して説明する。図１は本発明による固体撮
像装置の一例を示す平面図、図２は実施の形態例の固体
撮像装置を示す側面図であり、いずれも固体撮像素子を
固定するための接着剤を塗布する前の状態を示してい
る。なお、図中、図４、図５と同一の要素には同一の符
号が付されている。図１、図２に示した実施の形態例の
固体撮像装置２は、平面視矩形の半導体基板１０４から
成る固体撮像素子４を透明基板１０８に固定して構成さ
れている。半導体基板１０４は、その表面中央部に矩形
の撮像領域１１０が形成され、かつ撮像領域１１０を挟
んむ２つの辺部にそれぞれ複数の電極パッド１１２が配
列され、電極パッド１１２上にはバンプ１１６がそれぞ
れ配置されている。さらに、本実施の形態例では、電極
パッド１１２の間の箇所など、電極パッド１１２に隣接
してにダミー電極パッド６が配列され、各ダミー電極パ
ッド６上にダミーバンプ８が配置されている。ダミー電
極パッド６は電気的な機能を持たず、ダミー電極パッド
６を通じて信号が入力あるいは出力されたり、電源供給
が行われることはない。電極パッド１１２およびダミー
電極パッド６は一例としてアルミニウムにより形成さ
れ、バンプ１１６およびダミーバンプ８は、一例として
金によるボールバンプとして形成されている。BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. 1 is a plan view showing an example of a solid-state image pickup device according to the present invention, and FIG. 2 is a side view showing a solid-state image pickup device according to an embodiment, both of which are before applying an adhesive for fixing a solid-state image pickup device. Shows the state of. In the figure, the same elements as those in FIGS. 4 and 5 are designated by the same reference numerals. The solid-state image pickup device 2 of the embodiment shown in FIGS. 1 and 2 is configured by fixing a solid-state image pickup element 4 formed of a semiconductor substrate 104 having a rectangular shape in plan view to a transparent substrate 108. The semiconductor substrate 104 has a rectangular imaging region 110 formed in the center of its surface, and a plurality of electrode pads 112 are arranged on each of two sides sandwiching the imaging region 110. Bumps 116 are formed on the electrode pads 112. Each is arranged. Further, in the present embodiment, the dummy electrode pads 6 are arranged adjacent to the electrode pads 112, such as the positions between the electrode pads 112, and the dummy bumps 8 are arranged on each dummy electrode pad 6. The dummy electrode pad 6 has no electrical function, and no signal is input or output or power is not supplied through the dummy electrode pad 6. The electrode pad 112 and the dummy electrode pad 6 are formed of aluminum as an example, and the bumps 116 and the dummy bumps 8 are formed as ball bumps of gold as an example.
【０００９】透明基板１０８は、一例としてガラス板か
ら成り、その表面に複数の配線パターン１１４ととも
に、ダミー電極パッド６に対向する箇所にダミー配線パ
ターン１０が形成されている。ダミー配線パターン１０
は電気的な機能を持たず、ダミー電極パッド６を通じて
固体撮像素子４に信号が入力あるいは出力されたり、電
源供給が行われることはない。配線パターン１１４の一
方の端部はアウターリード部１２として透明基板１０８
の端部に配列され、もう一方の端部はインナーリード部
１４として半導体基板１０４の電極パッド１１２に対向
する箇所に配列されている。一方、ダミー配線パターン
１０は、ダミー電極パッド６（したがってダミーバンプ
８）に対応する箇所にのみ形成されている。配線パター
ン１１４およびダミー配線パターン１０は、本実施の形
態例では、一例としてアルミニウムにより形成されてい
る。なお、アルミニウム以外にもたとえば金によりこれ
らの配線パターン１１４を形成することも可能である。
アウターリード部１２は、たとえばフレキシブル回路基
板などを接続する際に、フレキシブル回路基板上の各配
線を接続するための電極となる。The transparent substrate 108 is made of, for example, a glass plate, and a plurality of wiring patterns 114 are formed on the surface of the transparent substrate 108, and a dummy wiring pattern 10 is formed at a position facing the dummy electrode pad 6. Dummy wiring pattern 10
Does not have an electrical function, and a signal is not input to or output from the solid-state imaging device 4 through the dummy electrode pad 6 or power is not supplied. One end of the wiring pattern 114 serves as the outer lead portion 12 and the transparent substrate 108.
And the other end is arranged as an inner lead portion 14 at a position facing the electrode pad 112 of the semiconductor substrate 104. On the other hand, the dummy wiring pattern 10 is formed only at the location corresponding to the dummy electrode pad 6 (and therefore the dummy bump 8). The wiring pattern 114 and the dummy wiring pattern 10 are made of aluminum as an example in the present embodiment. In addition to aluminum, these wiring patterns 114 may be formed of gold, for example.
The outer lead portion 12 serves as an electrode for connecting each wiring on the flexible circuit board when connecting, for example, a flexible circuit board.
【００１０】半導体基板１０４および透明基板１０８
は、板面を相互に対向させるとともに半導体基板１０４
の電極パッド１１２およびダミー電極パッド６が透明基
板１０８の配線パターン１１４およびダミー配線パター
ン１０に対向する状態で配置され、各電極パッド１１２
およびダミー電極パッド６はバンプ１１６およびダミー
バンプ８を介して対応する配線パターン１１４およびダ
ミー配線パターン１０に電気的および機械的に接続され
ている。The semiconductor substrate 104 and the transparent substrate 108
Is a semiconductor substrate 104.
Of the electrode pad 112 and the dummy electrode pad 6 of the transparent substrate 108 are arranged so as to face the wiring pattern 114 and the dummy wiring pattern 10.
The dummy electrode pad 6 is electrically and mechanically connected to the corresponding wiring pattern 114 and the dummy wiring pattern 10 via the bump 116 and the dummy bump 8.
【００１１】そして、半導体基板１０４の裏面における
周辺部と同裏面周辺部に隣接する透明基板１０８上の箇
所とに、半導体基板１０４の全周にわたり、たとえば合
成樹脂製の接着剤（図示せず）が塗布され、半導体基板
１０４が透明基板１０８に固定されるとともに、半導体
基板表面と透明基板１０８との間の隙間空間の気密性が
確保されている。なお、接着剤を塗布した後の固体撮像
装置２は、図４の（Ａ）に示した従来の固体撮像装置と
同様の形態となる。An adhesive agent (not shown) made of, for example, a synthetic resin is formed on the peripheral portion of the back surface of the semiconductor substrate 104 and a portion on the transparent substrate 108 adjacent to the peripheral portion of the back surface over the entire circumference of the semiconductor substrate 104. Is applied to fix the semiconductor substrate 104 to the transparent substrate 108, and at the same time, the airtightness of the gap space between the semiconductor substrate surface and the transparent substrate 108 is secured. The solid-state imaging device 2 after applying the adhesive has a form similar to that of the conventional solid-state imaging device shown in FIG.
【００１２】バンプ１１６およびダミーバンプ８を介し
た半導体基板１０４の透明基板１０８への接合は、たと
えば超音波圧着により行うことができる。その際、半導
体基板１０４および透明基板１０８のいずれか一方また
は両方を加熱して、より強固な接合を図ることも有効で
ある。また、バンプ１１６およびダミーバンプ８を電極
パッド１１２およびダミー電極パッド６の上にそれぞれ
形成した際、バンプの高さを均一にするレベリング加工
を行って、バンプ１１６およびダミーバンプ８を介した
半導体基板１０４と透明基板１０８との接合をより確実
なものとするよう図ることも有効である。The bonding of the semiconductor substrate 104 to the transparent substrate 108 via the bumps 116 and the dummy bumps 8 can be performed by ultrasonic pressure bonding, for example. At that time, it is also effective to heat one or both of the semiconductor substrate 104 and the transparent substrate 108 to achieve stronger bonding. When the bumps 116 and the dummy bumps 8 are formed on the electrode pads 112 and the dummy electrode pads 6, respectively, leveling processing is performed to make the heights of the bumps uniform, and the semiconductor substrate 104 via the bumps 116 and the dummy bumps 8 is formed. It is also effective to make the bonding with the transparent substrate 108 more reliable.
【００１３】上記接着剤としては紫外線硬化型あるいは
熱硬化型のものを用いることができ、硬化前の接着剤を
半導体基板１０４の周囲に塗布した後、紫外線を照射す
るか、または熱を加えて接着剤を硬化させ、半導体基板
１０４を透明基板１０８に固定することができる。As the above-mentioned adhesive, an ultraviolet curing type or a thermosetting type can be used. After the adhesive before curing is applied to the periphery of the semiconductor substrate 104, it is irradiated with ultraviolet rays or heat is applied. The semiconductor substrate 104 can be fixed to the transparent substrate 108 by curing the adhesive.
【００１４】このように、本実施の形態例では、半導体
基板１０４には、本来の電極パッド１１２とともにダミ
ー電極パッド６が配置され、ダミー電極パッド６はダミ
ーバンプ８を介して半導体基板１０４上の対応するダミ
ー配線パターン１０に接続されている。したがって、半
導体基板１０４はこれらのダミー電極パッド６、ダミー
バンプ８、ダミー配線パターン１０によっても透明基板
１０８に機械的に接続されることになり、従来より強固
に透明基板１０８に固定される。その結果、固体撮像装
置２の熱的衝撃や機械的衝撃に対する耐性が向上する。As described above, in this embodiment, the dummy electrode pads 6 are arranged on the semiconductor substrate 104 together with the original electrode pads 112, and the dummy electrode pads 6 correspond to each other on the semiconductor substrate 104 via the dummy bumps 8. Is connected to the dummy wiring pattern 10. Therefore, the semiconductor substrate 104 is also mechanically connected to the transparent substrate 108 by the dummy electrode pads 6, the dummy bumps 8, and the dummy wiring patterns 10, and is fixed to the transparent substrate 108 more firmly than before. As a result, the resistance of the solid-state imaging device 2 to thermal shock and mechanical shock is improved.
【００１５】また、本来のバンプ１１６などとともにダ
ミーバンプ８などが配置されるため、硬化前の接着剤を
半導体基板１０４の周囲に塗布した際に、接着剤はダミ
ーバンプ８や、ダミー電極パッド６、ダミー配線パター
ン１０によっても半導体基板１０４下へ流入することが
阻止される。よって、接着剤が撮像領域１１０にまで流
入することによる不具合の発生を防止することができ
る。Further, since the dummy bumps 8 and the like are arranged together with the original bumps 116 and the like, when the adhesive before curing is applied to the periphery of the semiconductor substrate 104, the adhesive is used as the dummy bumps 8, the dummy electrode pads 6, and the dummy. The wiring pattern 10 also blocks the inflow to the lower side of the semiconductor substrate 104. Therefore, it is possible to prevent the occurrence of defects caused by the adhesive flowing into the imaging region 110.
【００１６】次に、本発明の第２の実施の形態例につい
て説明する。図３は、本発明の第２の実施の形態例を示
す平面図であり、接着剤を塗布する前の状態を示してい
る。図中、図１などと同一の要素には同一の符号が付さ
れている。この第２の実施の形態例の固体撮像装置１６
が、上記実施の形態例の固体撮像装置２と異なるのは、
半導体基板表面の上記電極パッド１１２、バンプ１１
６、ダミー電極パッド６、ダミーバンプ８が配列された
辺部に直交する両辺部１１４Ａにも、複数のダミー電極
パッド６およびダミーバンプ８がそれぞれ配列されてい
る点である。各ダミー電極パッド６（したがってダミー
バンプ８）に対向する透明基板１０８上の箇所にはダミ
ー配線パターン１０が形成されて、対応するダミー電極
パッド６とダミー配線パターン１０とがダミーバンプ８
を介して接続されている。Next, a second embodiment of the present invention will be described. FIG. 3 is a plan view showing a second embodiment of the present invention, showing a state before applying an adhesive. In the figure, the same symbols are attached to the same elements as in FIG. 1 and the like. The solid-state imaging device 16 according to the second embodiment
However, the difference from the solid-state imaging device 2 of the above-described embodiment is that
The electrode pad 112 and the bump 11 on the surface of the semiconductor substrate
6, the dummy electrode pads 6 and the dummy bumps 8 are arranged on both side portions 114A orthogonal to the side portions on which the dummy electrode pads 6 and the dummy bumps 8 are arranged. Dummy wiring patterns 10 are formed on the transparent substrate 108 facing the dummy electrode pads 6 (and therefore the dummy bumps 8), and the dummy electrode pads 6 and the dummy wiring patterns 10 corresponding to each other are formed on the dummy bumps 8.
Connected through.
【００１７】したがって、第２の実施の形態例では、半
導体基板１０４は辺部１０４Ａに配列されたこれらのダ
ミー電極パッド６、ダミーバンプ８、ダミー配線パター
ン１０によっても透明基板１０８に機械的に接続される
ことになり、固体撮像装置２の場合より強固に透明基板
１０８に固定される。その結果、固体撮像装置の熱的衝
撃や機械的衝撃に対する耐性がさらに向上する。また、
辺部１１４Ａにもダミーバンプ８などが配置されるた
め、硬化前の接着剤を半導体基板１０４の周囲に塗布し
た際に、接着剤は辺部１１４Ａの箇所から半導体基板１
０４下へ流入することが阻止される。よって、接着剤が
撮像領域１１０にまで流入することによる不具合の発生
をより確実に防止することができる。Therefore, in the second embodiment, the semiconductor substrate 104 is mechanically connected to the transparent substrate 108 also by these dummy electrode pads 6, dummy bumps 8 and dummy wiring patterns 10 arranged on the side portion 104A. Therefore, the solid-state imaging device 2 is more firmly fixed to the transparent substrate 108. As a result, the resistance of the solid-state imaging device to thermal shock and mechanical shock is further improved. Also,
Since the dummy bumps 8 and the like are also arranged on the side portion 114A, when the adhesive before curing is applied to the periphery of the semiconductor substrate 104, the adhesive is applied from the side portion 114A to the semiconductor substrate 1.
04 is prevented from flowing down. Therefore, it is possible to more reliably prevent the occurrence of a defect due to the adhesive flowing into the imaging region 110.
【００１８】[0018]
【発明の効果】以上説明したように本発明では、本来の
電極パッドとともにダミー電極パッドが半導体基板に配
置され、ダミー電極パッドはダミーバンプを介して半導
体基板上の対応するダミー配線に接続されている。した
がって、半導体基板はこれらのダミー電極パッド、ダミ
ーバンプ、ダミー配線によっても透明基板に機械的に接
続されることになり、従来より強固に透明基板に固定さ
れる。その結果、固体撮像装置の熱的衝撃や機械的衝撃
に対する耐性が向上する。また、本来のバンプなどとと
もにダミーバンプなどが配列されていることから、硬化
前の接着剤を半導体基板の周囲に塗布した際に、接着剤
は本来のバンプなどとともにダミーバンプなどによって
も半導体基板下へ流入することが阻止される。よって、
接着剤が撮像領域にまで流入することによる不具合の発
生を防止することができる。As described above, in the present invention, the dummy electrode pads are arranged on the semiconductor substrate together with the original electrode pads, and the dummy electrode pads are connected to the corresponding dummy wirings on the semiconductor substrate through the dummy bumps. . Therefore, the semiconductor substrate is mechanically connected to the transparent substrate also by these dummy electrode pads, dummy bumps, and dummy wirings, so that the semiconductor substrate is more firmly fixed to the transparent substrate. As a result, the resistance of the solid-state imaging device to thermal shock and mechanical shock is improved. In addition, since the dummy bumps are arranged along with the original bumps, when the adhesive before curing is applied around the semiconductor substrate, the adhesive also flows under the semiconductor substrate due to the dummy bumps along with the original bumps. Is prevented. Therefore,
It is possible to prevent the occurrence of defects due to the adhesive flowing into the imaging area.
【図１】本発明による固体撮像装置の一例を示す平面図
である。FIG. 1 is a plan view showing an example of a solid-state imaging device according to the present invention.
【図２】本発明による固体撮像装置の一例を示す側面図
である。FIG. 2 is a side view showing an example of a solid-state imaging device according to the present invention.
【図３】本発明の第２の実施の形態例を示す平面図であ
る。FIG. 3 is a plan view showing a second exemplary embodiment of the present invention.
【図４】（Ａ）および（Ｂ）は従来の固体撮像装置を示
す平面図である。FIG. 4A and FIG. 4B are plan views showing a conventional solid-state imaging device.
【図５】従来の固体撮像装置を示す側面図である。FIG. 5 is a side view showing a conventional solid-state imaging device.
２、１０２……固体撮像装置、４、１０６……固体撮像
素子、６……ダミー電極パッド、８……ダミーバンプ、
１０……ダミー配線パターン、１２……アウターリード
部、１４……インナーリード部、１０４……半導体基
板、１０８……透明基板、１１０……撮像領域、１１２
……電極パッド、１１４……配線パターン、１１６……
バンプ、１１８……接着剤。2, 102 ... Solid-state imaging device, 4, 106 ... Solid-state imaging device, 6 ... Dummy electrode pad, 8 ... Dummy bump,
10 ... Dummy wiring pattern, 12 ... Outer lead part, 14 ... Inner lead part, 104 ... Semiconductor substrate, 108 ... Transparent substrate, 110 ... Imaging area, 112
...... Electrode pad, 114 ...... Wiring pattern, 116 ……
Bump, 118 ... Adhesive.
Claims (9)
され、前記固体撮像素子は半導体基板から成り、前記半
導体基板は、その表面中央部に撮像領域が形成され、か
つ前記撮像領域の周辺に複数の電極パッドが配列されて
おり、前記透明基板は、その表面に複数の配線パターン
が形成され、前記半導体基板および前記透明基板は板面
を相互に対向させるとともに前記半導体基板の前記電極
パッドが前記透明基板の前記配線パターンに対向する状
態で配置され、各電極パッドはバンプを介して対応する
前記配線パターンに電気的および機械的に接続され、前
記半導体基板の裏面における周辺部と同裏面周辺部に隣
接する前記透明基板上の箇所とに接着剤を塗布して前記
半導体基板が前記透明基板に固定されている固体撮像装
置であって、 前記半導体基板は、その表面に配列された複数のダミー
電極パッドと、各ダミー電極パッド上に配置されたダミ
ーバンプとを備え、 前記透明基板は、前記ダミー電極パッドに対向する箇所
にダミー配線パターンを備え、 前記ダミー電極パッドと前記ダミー配線パターンとは前
記ダミーバンプを介して相互に電気的および機械的に接
続されていることを特徴とする固体撮像装置。1. A solid-state image sensor is fixed to a transparent substrate, the solid-state image sensor is made of a semiconductor substrate, and the semiconductor substrate has an image-capturing region formed at the center of the surface thereof, and the periphery of the image-capturing region. A plurality of electrode pads are arranged on the transparent substrate, a plurality of wiring patterns are formed on the surface of the transparent substrate, the plate surfaces of the semiconductor substrate and the transparent substrate are opposed to each other, and the electrode pads of the semiconductor substrate are formed. Are arranged in a state of facing the wiring pattern of the transparent substrate, and each electrode pad is electrically and mechanically connected to the corresponding wiring pattern via a bump, and the same back surface as the peripheral portion on the back surface of the semiconductor substrate. A solid-state imaging device, wherein the semiconductor substrate is fixed to the transparent substrate by applying an adhesive to a location on the transparent substrate adjacent to a peripheral portion, The conductor substrate has a plurality of dummy electrode pads arranged on the surface thereof and dummy bumps arranged on each dummy electrode pad, and the transparent substrate has a dummy wiring pattern at a position facing the dummy electrode pad. The solid-state imaging device, wherein the dummy electrode pad and the dummy wiring pattern are electrically and mechanically connected to each other through the dummy bump.
ッドは、前記半導体基板の表面において前記撮像領域を
挟む２つの辺部に配列されていることを特徴とする請求
項１記載の固体撮像装置。2. The solid-state imaging device according to claim 1, wherein the electrode pad and the dummy electrode pad are arranged on two sides of the surface of the semiconductor substrate that sandwich the imaging region.
板の表面において前記辺部に直交する他の辺部にも配列
されていることを特徴とする請求項２記載の固体撮像装
置。3. The solid-state imaging device according to claim 2, wherein the dummy electrode pads are also arranged on another side portion orthogonal to the side portion on the surface of the semiconductor substrate.
ーリード部として前記透明基板の端部に配列され、もう
一方の端部はインナーリード部として前記半導体基板の
前記電極パッドに対向する箇所に配列されていることを
特徴とする請求項１記載の固体撮像装置。4. One end portion of the wiring pattern is arranged as an outer lead portion at an end portion of the transparent substrate, and the other end portion is provided as an inner lead portion at a position facing the electrode pad of the semiconductor substrate. The solid-state imaging device according to claim 1, wherein the solid-state imaging devices are arranged.
ッドはアルミニウムにより形成されていることを特徴と
する請求項１記載の固体撮像装置。5. The solid-state imaging device according to claim 1, wherein the electrode pad and the dummy electrode pad are made of aluminum.
により形成されていることを特徴とする請求項１記載の
固体撮像装置。6. The solid-state imaging device according to claim 1, wherein the bump and the dummy bump are formed of gold.
パターンはアルミニウムまたは金により形成されている
ことを特徴とする請求項１記載の固体撮像装置。7. The solid-state imaging device according to claim 1, wherein the wiring pattern and the dummy wiring pattern are formed of aluminum or gold.
たり塗布されていることを特徴とする請求項１記載の固
体撮像装置。8. The solid-state imaging device according to claim 1, wherein the adhesive is applied over the entire circumference of the semiconductor substrate.
成されていることを特徴とする請求項１記載の固体撮像
装置。9. The solid-state imaging device according to claim 1, wherein the transparent substrate is formed of a transparent glass plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001285942A JP4934935B2 (en) | 2001-09-19 | 2001-09-19 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001285942A JP4934935B2 (en) | 2001-09-19 | 2001-09-19 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003100999A true JP2003100999A (en) | 2003-04-04 |
| JP4934935B2 JP4934935B2 (en) | 2012-05-23 |
Family
ID=19109006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001285942A Expired - Fee Related JP4934935B2 (en) | 2001-09-19 | 2001-09-19 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4934935B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005252140A (en) * | 2004-03-08 | 2005-09-15 | Olympus Corp | Package for solid photographing device |
| JP2006269592A (en) * | 2005-03-23 | 2006-10-05 | Fuji Photo Film Co Ltd | Solid-state image sensor and manufacturing method thereof |
| JP2006332465A (en) * | 2005-05-27 | 2006-12-07 | Optrex Corp | Chip-on film semiconductor device |
| JP2007173738A (en) * | 2005-12-26 | 2007-07-05 | Fuji Xerox Co Ltd | Wiring board and flip-chip mounting structure |
| US8300124B2 (en) | 2005-11-25 | 2012-10-30 | Samsung Electro-Mechanics Co., Ltd. | Image sensor module and camera module package having the same |
| JP2013239652A (en) * | 2012-05-16 | 2013-11-28 | Sharp Corp | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01185952A (en) * | 1988-01-21 | 1989-07-25 | Oki Electric Ind Co Ltd | Flip-chip type semiconductor device |
| JPH0670242A (en) * | 1992-08-19 | 1994-03-11 | Olympus Optical Co Ltd | Solid state image pickup device |
| JPH0799214A (en) * | 1993-05-28 | 1995-04-11 | Toshiba Corp | Mounting device for photoelectric transducer and its production |
| JPH104125A (en) * | 1996-06-14 | 1998-01-06 | Toshiba Microelectron Corp | Semiconductor memory device and manufacture thereof |
-
2001
- 2001-09-19 JP JP2001285942A patent/JP4934935B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01185952A (en) * | 1988-01-21 | 1989-07-25 | Oki Electric Ind Co Ltd | Flip-chip type semiconductor device |
| JPH0670242A (en) * | 1992-08-19 | 1994-03-11 | Olympus Optical Co Ltd | Solid state image pickup device |
| JPH0799214A (en) * | 1993-05-28 | 1995-04-11 | Toshiba Corp | Mounting device for photoelectric transducer and its production |
| JPH104125A (en) * | 1996-06-14 | 1998-01-06 | Toshiba Microelectron Corp | Semiconductor memory device and manufacture thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005252140A (en) * | 2004-03-08 | 2005-09-15 | Olympus Corp | Package for solid photographing device |
| JP2006269592A (en) * | 2005-03-23 | 2006-10-05 | Fuji Photo Film Co Ltd | Solid-state image sensor and manufacturing method thereof |
| JP4677260B2 (en) * | 2005-03-23 | 2011-04-27 | 富士フイルム株式会社 | Manufacturing method of solid-state imaging device |
| JP2006332465A (en) * | 2005-05-27 | 2006-12-07 | Optrex Corp | Chip-on film semiconductor device |
| JP4699089B2 (en) * | 2005-05-27 | 2011-06-08 | オプトレックス株式会社 | Chip-on-film semiconductor device |
| US8300124B2 (en) | 2005-11-25 | 2012-10-30 | Samsung Electro-Mechanics Co., Ltd. | Image sensor module and camera module package having the same |
| JP2007173738A (en) * | 2005-12-26 | 2007-07-05 | Fuji Xerox Co Ltd | Wiring board and flip-chip mounting structure |
| JP2013239652A (en) * | 2012-05-16 | 2013-11-28 | Sharp Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4934935B2 (en) | 2012-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100600304B1 (en) | Structure of image sensor module and method for manufacturing of wafer level package | |
| JP4304163B2 (en) | Imaging module and manufacturing method thereof | |
| JP6214337B2 (en) | Electronic parts, electronic devices, and methods for manufacturing electronic parts. | |
| US7408252B2 (en) | Semiconductor device and a manufacturing method of the same | |
| JP3877860B2 (en) | Semiconductor device with solid-state image sensor and method for manufacturing the semiconductor device | |
| JP2003133518A (en) | Semiconductor module | |
| JPH09260436A (en) | Semiconductor device | |
| JP3376356B2 (en) | Thin photosensitive semiconductor device | |
| JPH11307886A (en) | Flip chip joinint land waving prevention pattern | |
| WO1999034436A1 (en) | Semiconductor device | |
| US20070108636A1 (en) | Semiconductor device | |
| JPH11260851A (en) | Semiconductor device and its manufacture | |
| JPH10289932A (en) | Carrier film and integrated circuit device using thereof | |
| JP4934935B2 (en) | Solid-state imaging device | |
| JP3490303B2 (en) | Semiconductor device package | |
| JP6128993B2 (en) | Multilayer semiconductor device, printed circuit board, electronic device, and method of manufacturing multilayer semiconductor device | |
| JP4556671B2 (en) | Semiconductor package and flexible circuit board | |
| KR100485629B1 (en) | Method for assembling camera module | |
| JP2006245359A (en) | Photoelectric conversion device, and manufacturing method thereof | |
| US20070164404A1 (en) | Semiconductor package | |
| JP4483016B2 (en) | Solid-state imaging device and manufacturing method thereof | |
| JP2756791B2 (en) | Resin-sealed semiconductor device | |
| US20090310321A1 (en) | Printed circuit board and electronic apparatus | |
| JPH0786544A (en) | Ccd device | |
| JP2004363319A (en) | Mount substrate and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080908 |
|
| RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20090817 |
|
| RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20091013 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110802 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110811 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110922 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120124 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120206 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150302 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150302 Year of fee payment: 3 |
|
| LAPS | Cancellation because of no payment of annual fees |