JPH01185952A - Flip-chip type semiconductor device - Google Patents

Flip-chip type semiconductor device

Info

Publication number
JPH01185952A
JPH01185952A JP63009513A JP951388A JPH01185952A JP H01185952 A JPH01185952 A JP H01185952A JP 63009513 A JP63009513 A JP 63009513A JP 951388 A JP951388 A JP 951388A JP H01185952 A JPH01185952 A JP H01185952A
Authority
JP
Japan
Prior art keywords
chip
bump electrode
electrode
dummy
filler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63009513A
Other languages
Japanese (ja)
Other versions
JP2810666B2 (en
Inventor
Hitoshi Tsubone
坪根 衡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP63009513A priority Critical patent/JP2810666B2/en
Publication of JPH01185952A publication Critical patent/JPH01185952A/en
Application granted granted Critical
Publication of JP2810666B2 publication Critical patent/JP2810666B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors

Abstract

PURPOSE:To prevent a chip from becoming electrically defective when a flaw is produced by a filler on the surface of the chip by a method wherein a gap between a solder bump electrode and a dummy electrode is set at a definite distance so as to limit the size of the filler. CONSTITUTION:A bump electrode 2a formed on a chip 1 and a dummy bump electrode 2b are provided; a distance 3 between the bump electrode 2a and the dummy bump electrode 2b is set to the size of 60% or less of the diameter of the bump electrode 2a. Accordingly, even when a semiconductor device is mounted on a substrate and is then coated with an epoxy-based molding material, a filler whose size exceeds 60% of the diameter of the dummy electrode 2b out of fillers contained in the molding material does not creep to the lower part of the semiconductor device. By this setup, it is possible to eliminate a wrong state that the filler produces a flaw on the surface of the semiconductor chip and that the semiconductor chip becomes electrically defective.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はフリップチップ型半導体装置に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a flip-chip semiconductor device.

(従来の技術) 従来より、実装密度を向上するためにパンツ電極を備え
る半導体チッf(フリラグチップ)が用いられている。
(Prior Art) Conventionally, semiconductor chips (free lag chips) equipped with pants electrodes have been used in order to improve packaging density.

バンプ電極の形成方法としては、例えば電気メツキ法、
選択蒸着法、ハンダが−ル法、ハンダデイツプ法等の種
々の方法が提案されている。バンプ電極は、−船釣に、
電気メツキ法によりハンダ全周いて形成されることが多
い。
Examples of methods for forming bump electrodes include electroplating,
Various methods have been proposed, such as a selective vapor deposition method, a solder dip method, and a solder dip method. Bump electrodes are suitable for boat fishing.
It is often formed with solder all around it by electroplating.

第2図は従来のバンプ電極の接続構造を概略的に示すフ
リノブチップの要部断面図であり、半導体チップ上にバ
ンプ電極が設けられている状態を示す。同図に於て半導
体チッfxoは半導体基板、例えばP型Si基板よりな
る。
FIG. 2 is a cross-sectional view of a main part of a fly-knob chip schematically showing a conventional bump electrode connection structure, and shows a state in which bump electrodes are provided on a semiconductor chip. In the figure, the semiconductor chip fxo is made of a semiconductor substrate, for example, a P-type Si substrate.

図示例では、第一層16として絶縁膜、配線電極18と
してAlx極及び第二層20としてC’VD(Chem
ical Vapor Deposition )  
法によって形成されたガラス膜(ハヒシベーション保護
膜)が半導体チップ上に順次に設けられる。
In the illustrated example, the first layer 16 is an insulating film, the wiring electrode 18 is an Alx electrode, and the second layer 20 is a C'VD (Chemical) film.
ical Vapor Deposition)
A glass film (Hahishivation protective film) formed by the method is sequentially provided on the semiconductor chip.

図示例のバンプ電極22はバリヤ層24及び・ぐラド2
6から成る。図示例において、バリヤ層24F′i第二
層20上に順次に設けられたAt−Ni合金層28、N
i層30及びCo層32から成り、さらにバリヤ層24
のCu層32上にバッド26としてハンダ層が設けられ
ている。At−Ni合金層28及びN1層30は例えば
蒸着によって、Cu層32及びパッド26は例えば電気
メツキ法によって形成されている。・ぐラド26は、例
えばCo層32上に形成されたハンダメツキ層を高温処
理し、表面張力を利用することによって、球状に形成さ
れる。電気メツキ法によるハンダバンプ電極の形成方法
は周知(例えば特開昭62−160744−i参照)で
あるので、詳細な説明を省略する。
The bump electrode 22 in the illustrated example includes a barrier layer 24 and a glass layer 2.
Consists of 6. In the illustrated example, the At-Ni alloy layer 28, the N
It consists of an i layer 30 and a Co layer 32, and further includes a barrier layer 24.
A solder layer is provided as a pad 26 on the Cu layer 32 . The At-Ni alloy layer 28 and the N1 layer 30 are formed, for example, by vapor deposition, and the Cu layer 32 and the pad 26 are formed, for example, by electroplating. - The GLAD 26 is formed into a spherical shape by, for example, treating a solder plating layer formed on the Co layer 32 at high temperature and utilizing surface tension. The method of forming solder bump electrodes by electroplating is well known (see, for example, Japanese Patent Application Laid-Open No. 160744-1/1983), and therefore detailed explanation will be omitted.

第3図はフリップチップの構成を概略的に示す側面図で
ある。フリップチップ型半導体装置は半導体チッ7DI
Oにバンプ電極22を設けて成る。
FIG. 3 is a side view schematically showing the structure of the flip chip. Flip chip type semiconductor device is semiconductor chip 7DI
A bump electrode 22 is provided at O.

図示例では、図面の簡単化のためにバンプ電極22を2
個しか設けていないが、一般に、3〜10個、多いとき
には100個近くのバンプ電極22が設けられる。
In the illustrated example, the bump electrodes 22 are
Generally, 3 to 10 bump electrodes 22 are provided, and in some cases, nearly 100 bump electrodes 22 are provided.

第4図はフリップチップの実装状態を概略的に示す側面
図である。同図において、被実装基板(配線基板)40
は表面に所定の電気回路パターンを備えるものであり、
被実装基板40の基板材料として例えばセラミック基板
が用いられる。図にも示すように、フリップチップ38
は被実装基板40に直接実装される。
FIG. 4 is a side view schematically showing the mounting state of the flip chip. In the figure, a mounted board (wiring board) 40
is equipped with a predetermined electric circuit pattern on its surface,
For example, a ceramic substrate is used as the substrate material of the mounted substrate 40. As shown in the figure, the flip chip 38
is directly mounted on the mounting board 40.

バンプ電極が、ハンダから成る・2ツドを有するフリッ
プチップの実装方法としては例えばリフロ一方式のもの
がある。この方式では、フリッグチッf 38’iフエ
イスダウンにして被実装基板40上の所定位置に配置し
、その後これらフリツプチッf 3g及び被実装基板4
0をリフロー炉内に入れ200〜220℃に加熱する。
As a mounting method for a flip chip having two bump electrodes made of solder, there is, for example, a reflow one-type method. In this method, the flip chips f38'i are placed face-down at predetermined positions on the mounting board 40, and then these flip chips f3g and the mounting board 4
0 into a reflow oven and heated to 200 to 220°C.

その結果、バンプ電極22のノ・ンダから成る・9ツド
26(第5図参照)が溶融される。その後フリツプチッ
fss及び被実装基板40はリフロー炉から取出され常
温まで冷却される。従って・やラド26も冷却され。
As a result, the nine dots 26 (see FIG. 5) of the bump electrodes 22 are melted. Thereafter, the flip chip fss and the mounting board 40 are taken out of the reflow oven and cooled to room temperature. Therefore, the Rad 26 is also cooled.

よってフリッグチッf3gが・ゼット26を介して被実
装基板40の電気回路・ぐターンと接続される。
Therefore, the flip chip f3g is connected to the electric circuit of the mounting board 40 via the wire 26.

さらにこの基板には、チップの信頼性を向上させる目的
で第5図に示すように、エポキシ系のモールド材42を
チップ表面を外部から保護できるようコーティングする
。通常このモールド材充填は150°C〜200℃の基
板加熱下にて行なわれる又、このモールド材中には通常
、モールド材の強度を向上させる目的で、10チ〜30
%(重量比)のフィラーと呼ばれるSiQ□の粉などの
充填材が含まれる。このフィラーの形状は一般には球状
で、直径が30μm〜100μmφのものが用いらしか
しながら、上記構成のハンダバンプによる、基板と半導
体チップの接続方法に於ては、第6図に示すごとく、球
状フィラー44がモールド材42の充填時に半導体チッ
f38とセラミック基板400間に入り込みモールドを
固めるとき、キュア温度150°Cで膨張したハンダ電
極22が、キーア温度1500Cから室温へ冷却される
過程で収縮するが、このとき半導体チッf38と基板4
0は図中矢印で示す方向に力をうけ縮まり、その間に入
り込んだフィラー44が半導体チップ38の表面にキズ
をつけてしまい半導体チップ38の電気的不良を発生さ
せるという不具合があった。通常接続に必要なハンダ電
極の高さは70〜100μmとされ、バンプ電極の収縮
によりデバイスに影響を及ぼす球状のフィラーがチップ
と基板の間に入り込むには十分な高さとなっている。
Further, this substrate is coated with an epoxy molding material 42 to protect the chip surface from the outside, as shown in FIG. 5, in order to improve the reliability of the chip. Usually, this molding material filling is carried out while heating the substrate at 150°C to 200°C, and in order to improve the strength of the molding material, 10 to 30
% (weight ratio) of filler such as SiQ□ powder. The shape of this filler is generally spherical, with a diameter of 30 μm to 100 μmφ. However, in the method of connecting a substrate and a semiconductor chip using a solder bump having the above configuration, a spherical filler 44 is used as shown in FIG. When filling the molding material 42, the solder electrode 22 enters between the semiconductor chip f38 and the ceramic substrate 400 and solidifies the mold, and the solder electrode 22 expands at the curing temperature of 150°C, but contracts during the cooling process from the quenching temperature of 1500°C to room temperature. At this time, the semiconductor chip f38 and the substrate 4
0 is compressed by force in the direction shown by the arrow in the figure, and the filler 44 that has entered between them scratches the surface of the semiconductor chip 38, causing an electrical defect in the semiconductor chip 38. The height of the solder electrode required for normal connection is 70 to 100 μm, which is sufficient for a spherical filler to enter between the chip and the substrate, which affects the device due to shrinkage of the bump electrode.

上記問題点を解決するため、本発明のフリップチップ型
半導体装置は、チップ上に形成されたバンプ電極と、ダ
ミーパンゾ電極を有し、前記バンプ電極と前記ダミーバ
ンプ電極間の距離をバンプ電極の直径の60係以下の寸
法とする。
In order to solve the above problems, a flip chip type semiconductor device of the present invention has a bump electrode formed on a chip and a dummy panzo electrode, and the distance between the bump electrode and the dummy bump electrode is equal to the diameter of the bump electrode. The dimensions shall be 60 or less.

(作用) 本発明のフリップチップ型半導体装置は上記のような構
成としたので、実装基板に前述した半導体装置を実装し
、その後エポキシ系モールド材全コーティングしても、
このモールド材に含有するフィラーのうち、ダミー電極
の直径の60c4″f!:越える大きさのフィラーが半
導体装置下部へ入り込むのを防止することができる。
(Function) Since the flip-chip semiconductor device of the present invention has the above-described configuration, even if the semiconductor device described above is mounted on a mounting board and then the entire epoxy molding material is coated,
Of the fillers contained in this molding material, it is possible to prevent fillers whose size exceeds the diameter of the dummy electrode by 60c4''f! from entering the lower part of the semiconductor device.

(実施例) 第1図はこの発明の実施例2示す図であり、Aは断面図
、Bは上面図である。この図に於て、1は半導体チップ
、2はハンダバンプ電極である。
(Embodiment) FIG. 1 is a diagram showing a second embodiment of the present invention, in which A is a sectional view and B is a top view. In this figure, 1 is a semiconductor chip and 2 is a solder bump electrode.

このハンダバンプ電極の大きさは70μmφとする。The size of this solder bump electrode is 70 μmφ.

通常ハンダバンプ電極は半導体チップlとセラミツク基
板との信号のやりとりを行なう必要がある数のみのハン
ダバンプ電極2aを形成するが、本発明に於てはチップ
上ハンダバンプ電極2どうしのすきま図中3が球状フィ
ラーを通過させない距離40μm以下となるよう、ダミ
ーのハンダバンプ電極2bf適当な数だけ追加し、チッ
プ上少なくともチップの周辺全てに配置する。このバン
プ間の距離は、バンプ電極の直径の60%としたもので
ある。
Normally, only the number of solder bump electrodes 2a necessary for exchanging signals between the semiconductor chip l and the ceramic substrate are formed, but in the present invention, the gap 3 between the solder bump electrodes 2 on the chip is spherical. An appropriate number of dummy solder bump electrodes 2bf are added and placed on the chip at least all around the chip so that the distance is 40 μm or less that does not allow the filler to pass through. The distance between the bumps is 60% of the diameter of the bump electrode.

次に上述したダミーバンプ電極2bの形成方法について
述べる。このダミーバンプ電Nzbは、通常のバンプ電
極と同様にバリヤ層を下層に設は形成してもよいし、単
に金属層を下層に形成した後・9ツドを形成してもよい
。ただし、通常のバンプ電極は基板との信号のやりとり
を行うため、基板と接続されているが、ダミーバンプ電
極は、ノイズ侵入の防止等のため基板とは絶縁されてい
る。
Next, a method for forming the above-mentioned dummy bump electrode 2b will be described. This dummy bump electrode Nzb may be formed by providing or forming a barrier layer on the lower layer as in the case of a normal bump electrode, or may simply be formed after forming a metal layer on the lower layer. However, while normal bump electrodes are connected to the substrate in order to exchange signals with the substrate, dummy bump electrodes are insulated from the substrate to prevent noise from entering.

又、チップが実装される実装基板におけるダミーバンプ
電極に対応する位置には金属パッドが設けられており、
基板実装時において、この金属・ぐラドとダミーバンプ
電極が良好に融着される様になっている。この金属・ぞ
ラドもダミーバンプ電極との融着のためのみに用いられ
ているものであり、他とは絶縁されている。
In addition, metal pads are provided at positions corresponding to dummy bump electrodes on the mounting board on which the chip is mounted.
When mounted on a board, this metal/gradient and dummy bump electrode are well fused together. This metal wire is also used only for fusion bonding with the dummy bump electrode, and is insulated from others.

第7図はハンダバンプ電極の大きさが70μmの場合に
おいてバンプ間キョリ3を10μm〜100μmの間で
水準をとり、半導体チップをセラミック基板に実装しS
iO2系の球状フィラーの大きさの平均値が50μmで
ばらつき30〜70μmをもつモールド材に対する重量
比30係の比率をもつモールド材を150°Cで充填し
、その后、−30°C〜150℃の温度サイクル試験を
100ωくり返したときの半導体チップにつけられたキ
ズによりチップが電気的に不良となった割合を示すグラ
フである。
Figure 7 shows that when the size of the solder bump electrode is 70 μm, the distance between the bumps 3 is set at a level between 10 μm and 100 μm, and the semiconductor chip is mounted on the ceramic substrate.
A molding material having a weight ratio of 30 to the molding material having an average size of iO2-based spherical filler of 50 μm and a variation of 30 to 70 μm was filled at 150°C, and then heated to -30°C to 150°C. It is a graph showing the percentage of chips that became electrically defective due to scratches on the semiconductor chips when the temperature cycle test at °C was repeated for 100Ω.

第7図よりハンダパンゾ間キョリ3はノ・ンダパングの
大きさ70μmφの約60%、つまり40μm以下であ
ればフィラーがチップの表面をキズつけることによる不
良率は減少することが分かる。このことはハンダバンプ
により接続層バンプ電極は収縮し、テップと基板を接続
する訳であるが、この収縮の割合は多くとも60%程度
と推定されこの縮んだキョリより小さい球状フィラーは
チップと基板のすき間に入り込んでもチップの表面にキ
ズをつけるトラブルを発生させるには至らないものと考
えられる。
From FIG. 7, it can be seen that if the solder gap 3 is less than about 60% of the size of the solder punch 70 μmφ, that is, 40 μm or less, the defective rate due to the filler scratching the surface of the chip is reduced. This means that the connection layer bump electrode shrinks due to the solder bump, connecting the tip and the board, but the percentage of this shrinkage is estimated to be about 60% at most, and the spherical filler, which is smaller than this shrinking hole, is used to connect the chip and the board. Even if it gets into the gap, it is considered that it will not cause any trouble such as scratching the surface of the chip.

ハンダバンプ電極の大きさが70μmφよう大きい場合
あるいは少さい場合であってもこのノ・ンダパンプ電極
間距離3けノ・ンダパンデ電極の大キサの少なくとも6
0チ以下であれば同様の効果が期待できる。
Even when the size of the solder bump electrode is as large as 70 μmφ or as small as 70 μmφ, the distance between the solder bump electrodes must be at least 3 mm and the distance between the solder bump electrodes must be at least 6 mm.
A similar effect can be expected if it is less than 0.

(発明の効果) 以上説明したように本発明によれば半導体チップの周囲
全てに信号とり出し用のハンダバンプ電極と、ダミーの
電極間のすきまがハンダバンプ電極の大きさの60%程
度となる距離に配置したことにより、チップと基板の接
続層のモールド充填時の加熱下でチップと基板のすき間
に入υ込む球状フィラーの大きさがハンダバンプ電極の
大きさの60チ以下のものに限定されるため、加熱層に
室温に冷却されるとき、チップと基板とのすき間に存在
する球状フィラーにてチップ表面にキズをつけられチッ
プが電気的に不良となる様なトラブルは発生しない。
(Effects of the Invention) As explained above, according to the present invention, the distance between the solder bump electrodes for signal extraction and the dummy electrodes is approximately 60% of the size of the solder bump electrodes all around the semiconductor chip. Due to this arrangement, the size of the spherical filler that enters the gap between the chip and the board during heating during mold filling of the connection layer between the chip and the board is limited to 60 cm or less, which is the size of the solder bump electrode. When the heating layer cools the chip to room temperature, problems such as the chip surface being scratched by the spherical filler existing in the gap between the chip and the substrate and causing the chip to become electrically defective do not occur.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による半導体装置の断面図及び平面図で
ある。第2図は従来のバンプ電極の構造を示す断面図で
ある。第3図は従来のフリップチップの側面図である。 第4図は従来のフリップチクff基板に実装した状態を
示す側面図である。 第5図は従来のフリラグチップ全基板に実装し、さらに
エポキシ樹脂をコートした状態を示す側面図である。第
6図はエポキシ樹脂を冷却している状態を示すものであ
って、第5図の部分拡大図である。第7図はバンプ電極
間距離と不良率2示すグラフである。 1・・・半導体チップ、2a・・・ハンダバンプ電極、
2b・・・ダミーハンダバンプ電極、3゛・・バンプ間
距離。 歩Pβセヒイ>1aN 訛百計14ダ艷1々βまimm
第1八 A距骨い故明へ侠A勾二崩問 第1図B バ)デミ1!l!の積4叙 第2図 諷 フリー、フ゛チップのや)加図 第3図 Q 亥[[林を斤、1旬1面国 第4図
FIG. 1 is a sectional view and a plan view of a semiconductor device according to the present invention. FIG. 2 is a sectional view showing the structure of a conventional bump electrode. FIG. 3 is a side view of a conventional flip chip. FIG. 4 is a side view showing a state where the device is mounted on a conventional flip-chip FF board. FIG. 5 is a side view showing a state in which a conventional free lag chip is mounted on the entire board and further coated with epoxy resin. FIG. 6 shows a state in which the epoxy resin is being cooled, and is a partially enlarged view of FIG. 5. FIG. 7 is a graph showing the distance between bump electrodes and defective rate 2. 1... Semiconductor chip, 2a... Solder bump electrode,
2b...Dummy solder bump electrode, 3゛...Distance between bumps. StepPβSehii>1aN A total of 14 accents, 1 β imm
Chapter 18 A: A long time ago, a chivalry A: Koji Kou question Figure 1 B) Demi 1! l! Product of 4 poems 2nd proverb free, 5 chip no ya) addition 3rd figure Q Pig

Claims (1)

【特許請求の範囲】[Claims]  チップ上に形成されたバンプ電極と、ダミーバンプ電
極を有し、前記バンプ電極と前記ダミーバンプ電極間の
距離をバンプ電極の直径の60%以下の寸法としたこと
を特徴とするフリップチップ型半導体装置。
1. A flip-chip semiconductor device comprising a bump electrode formed on a chip and a dummy bump electrode, the distance between the bump electrode and the dummy bump electrode being 60% or less of the diameter of the bump electrode.
JP63009513A 1988-01-21 1988-01-21 Flip chip type semiconductor device and manufacturing method thereof Expired - Lifetime JP2810666B2 (en)

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JPH01185952A true JPH01185952A (en) 1989-07-25
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003100999A (en) * 2001-09-19 2003-04-04 Sony Corp Solid state image sensor
US6650016B1 (en) * 2002-10-01 2003-11-18 International Business Machines Corporation Selective C4 connection in IC packaging
US7518223B2 (en) 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US11887560B2 (en) 2011-12-06 2024-01-30 Dolby Laboratories Licensing Corporation Perceptual luminance nonlinearity-based image data exchange across different display capabilities

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943553A (en) * 1982-09-06 1984-03-10 Hitachi Ltd Electrode structure for semiconductor element
JPS60165740A (en) * 1984-01-28 1985-08-28 エヌ・ベー・フイリップス・フルーイランペンフアブリケン Device for contacting bipolar electronic circuit element andparticularly semiconductor circuit element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943553A (en) * 1982-09-06 1984-03-10 Hitachi Ltd Electrode structure for semiconductor element
JPS60165740A (en) * 1984-01-28 1985-08-28 エヌ・ベー・フイリップス・フルーイランペンフアブリケン Device for contacting bipolar electronic circuit element andparticularly semiconductor circuit element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518223B2 (en) 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
JP2003100999A (en) * 2001-09-19 2003-04-04 Sony Corp Solid state image sensor
US6650016B1 (en) * 2002-10-01 2003-11-18 International Business Machines Corporation Selective C4 connection in IC packaging
US11887560B2 (en) 2011-12-06 2024-01-30 Dolby Laboratories Licensing Corporation Perceptual luminance nonlinearity-based image data exchange across different display capabilities

Also Published As

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