JP2006332465A - Chip-on film semiconductor device - Google Patents

Chip-on film semiconductor device Download PDF

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JP2006332465A
JP2006332465A JP2005156276A JP2005156276A JP2006332465A JP 2006332465 A JP2006332465 A JP 2006332465A JP 2005156276 A JP2005156276 A JP 2005156276A JP 2005156276 A JP2005156276 A JP 2005156276A JP 2006332465 A JP2006332465 A JP 2006332465A
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dummy
lead terminals
chip
electrodes
semiconductor chip
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JP4699089B2 (en
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Seiichi Ishii
星一 石井
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Hiroshima Opt Corp
Kyocera Display Corp
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Hiroshima Opt Corp
Kyocera Display Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the connection failure of a semiconductor chip to a flexible wiring board. <P>SOLUTION: The chip-on film semiconductor device comprises a semiconductor chip 102 having a plurality of bump electrodes 105 closely arranged along its side, and an FPC 101 having a plurality of lead terminals 103 respectively facing at and connected to the plurality of bump electrodes 105. The semiconductor chip 102 is fixed onto the FPC 101 with adhesives. The FPC 101 comprises four or more dummy lead terminals 104 at the ends of the plurality of lead terminals 103. The semiconductor chip 102 comprises four or more dummy bump electrodes 106 facing at the four or more lead terminals 104. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、フレキシブル配線基板（Flexible Printed Circuit：ＦＰＣ）上に半導体チップを搭載したチップオンフィルム（Chip On Film：ＣＯＦ）半導体装置に関し、特に、それらの相互接続構造に関する。   The present invention relates to a chip on film (COF) semiconductor device in which a semiconductor chip is mounted on a flexible printed circuit (FPC), and more particularly to an interconnection structure thereof.

近年、電子機器の小型化、高性能化、高機能化に伴い、実装基板上の半導体チップの実装密度を向上させることが要求されている。この要求に対して、バンプ電極を設けた半導チップを、フェイスダウンの状態で実装基板に位置合わせし、バンプ電極と実装基板のリード端子とを接続する、フリップチップ方式による実装方法が広く採用されている。   In recent years, with the miniaturization, high performance, and high functionality of electronic devices, it is required to improve the mounting density of semiconductor chips on a mounting substrate. In response to this requirement, a flip chip mounting method is widely used, in which a semiconductor chip provided with bump electrodes is aligned with the mounting board face-down, and the bump electrodes and lead terminals of the mounting board are connected. Has been.

この方式では、ＱＦＰ（Quad Flat Package）方式を用いてパッケージングした場合に比べ、半導体チップの実装基板上の占有面積が小さくなるため、実装密度を向上させることができる。フリップチップ方式による実装を行った半導体装置としては、例えば、ＦＰＣ（Flexible Printed Circuit）上に半導体チップを搭載した、ＣＯＦ（Chip On Film）半導体装置が知られている。   In this method, since the area occupied on the mounting substrate of the semiconductor chip is smaller than in the case of packaging using the QFP (Quad Flat Package) method, the mounting density can be improved. For example, a COF (Chip On Film) semiconductor device in which a semiconductor chip is mounted on an FPC (Flexible Printed Circuit) is known as a semiconductor device that is mounted by a flip chip method.

一般に、ＣＯＦ半導体装置の実装は、半導体チップに設けられたバンプ電極とＦＰＣのリード端子との間にＡＣＦ（Anisotropic Conductive Film）を介在させて、加熱圧着することにより行われている。ＡＣＦは、絶縁性の接着材の中に金属粒子などの導電粒子を所定量含有したものである。ＡＣＦによる接続の信頼性を向上するためには、導電粒子の粒子径を隣接するバンプ電極間隔よりも小さくし、隣接するバンプ電極間の絶縁性を確保することが必要である（例えば、特許文献１参照）。
特開２００２−２７０６４１号公報 In general, the COF semiconductor device is mounted by thermocompression bonding with an ACF (Anisotropic Conductive Film) interposed between a bump electrode provided on a semiconductor chip and a lead terminal of the FPC. ACF contains a predetermined amount of conductive particles such as metal particles in an insulating adhesive. In order to improve the reliability of connection by ACF, it is necessary to make the particle diameter of the conductive particles smaller than the interval between adjacent bump electrodes to ensure insulation between adjacent bump electrodes (for example, Patent Documents). 1).
JP 2002-270641 A

ところで、近年の実装密度の向上に伴い、バンプ電極とリード端子とを接続した接続間隔が狭くなっている。ファインピッチの場合、バンプ電極も小さくなる。この場合、バンプ電極上で接続に寄与する導電粒子数を確保するためには、上述のＡＣＦに含まれる導電粒子の粒子数を増やすことが考えられる。しかし、導電粒子の数を増やすと、バンプ電極及びリード端子間の絶縁性が低下して、リークなどの不具合発生が懸念される。したがって、導電粒子を含まないＮＣＦ（Non Conductive film）を用いた実装が行われている。   By the way, with the recent improvement in mounting density, the connection interval between the bump electrode and the lead terminal is narrowed. In the case of fine pitch, the bump electrode is also small. In this case, in order to secure the number of conductive particles that contribute to the connection on the bump electrode, it is conceivable to increase the number of conductive particles contained in the ACF. However, when the number of conductive particles is increased, the insulation between the bump electrode and the lead terminal is lowered, and there is a concern about occurrence of problems such as leakage. Therefore, mounting using an NCF (Non Conductive film) that does not include conductive particles is performed.

ＮＣＦを用いた実装では、バンプ電極とリード端子との電気的接続を得るために、バンプ電極とリード端子とを直接接続させるため、ＡＣＦを用いた場合より大きな圧力をかけて熱圧着する必要がある。この場合、熱と圧力によりＦＰＣが大きく歪むことがわかった。   In mounting using the NCF, in order to directly connect the bump electrode and the lead terminal in order to obtain an electrical connection between the bump electrode and the lead terminal, it is necessary to perform thermocompression bonding by applying a larger pressure than in the case of using the ACF. is there. In this case, it was found that the FPC is greatly distorted by heat and pressure.

図３に示すように、従来のＣＯＦ半導体装置１０では、ＦＰＣ１１に設けられたリード端子１２と、半導体チップ１３に設けられたバンプ電極１４とを接続する際、ＦＰＣ１１が熱と圧力により大きく歪む。このため、接続不良が発生してしまうという問題があった。特に、ＦＰＣ１１のリード端子１２群のうち、端から１〜４番目リード端子１２とバンプ電極１４との接続がルーズになり易い傾向にあることがわかった。   As shown in FIG. 3, in the conventional COF semiconductor device 10, when the lead terminal 12 provided on the FPC 11 and the bump electrode 14 provided on the semiconductor chip 13 are connected, the FPC 11 is greatly distorted by heat and pressure. For this reason, there was a problem that connection failure occurred. In particular, it was found that the connection between the first to fourth lead terminals 12 and the bump electrode 14 in the lead terminal 12 group of the FPC 11 tends to be loose.

本発明は、このような事情を背景としてなされたものであり、本発明の目的は、半導体チップとフレキシブル配線基板との接続不良を抑制することである。   The present invention has been made against the background of such circumstances, and an object of the present invention is to suppress poor connection between a semiconductor chip and a flexible wiring board.

本発明の第１の態様にかかるチップオンフィルム半導体装置は、その辺に沿って近接して配列された複数の電極を有する半導体チップと、前記半導体チップが接着剤によってその上に固着され、前記複数の電極のそれぞれと対向しその対向する電極に接続された複数のリード端子を有するフレキシブル配線基板と、を備えるチップオンフィルム半導体装置であって、前記フレキシブル配線基板は、前記複数のリード端子の端に４以上のダミーリード端子を備え、前記半導体チップは、前記４以上のダミーリード端子のそれぞれに対向する４以上のダミー電極を備えているものである。このような構成を有することによって、半導体チップとフレキシブル配線基板との接続不良を抑制することができる。   A chip-on-film semiconductor device according to a first aspect of the present invention includes a semiconductor chip having a plurality of electrodes arranged close to each other along a side thereof, and the semiconductor chip is fixed thereon by an adhesive, A chip-on-film semiconductor device comprising: a flexible wiring board having a plurality of lead terminals opposed to each of the plurality of electrodes and connected to the opposed electrodes; Four or more dummy lead terminals are provided at the end, and the semiconductor chip is provided with four or more dummy electrodes facing each of the four or more dummy lead terminals. By having such a configuration, connection failure between the semiconductor chip and the flexible wiring board can be suppressed.

本発明の第２の態様にかかるチップオンフィルム半導体装置は、上記のチップオンフィルム半導体装置において、前記フレキシブル配線基板は、前記複数のリード端子の両端のそれぞれに、４以上のダミーリード端子を備え、前記半導体チップは、前記複数のリード端子の両端のそれぞれにおいて、前記４以上のダミーリード端子のそれぞれに対向する４以上のダミー電極を備えているものである。このような構成を有することによって、さらに確実に半導体チップとフレキシブル配線基板との接続不良を抑制することができる。   The chip-on-film semiconductor device according to a second aspect of the present invention is the above-described chip-on-film semiconductor device, wherein the flexible wiring board includes four or more dummy lead terminals at each of both ends of the plurality of lead terminals. The semiconductor chip includes four or more dummy electrodes facing each of the four or more dummy lead terminals at each of both ends of the plurality of lead terminals. By having such a configuration, it is possible to more reliably suppress poor connection between the semiconductor chip and the flexible wiring board.

本発明の第３の態様にかかるチップオンフィルム半導体装置は、上記のチップオンフィルム半導体装置において、前記４以上のダミーリード端子及び前記複数のリード端子のそれぞれは、同一ピッチで配置されており、前記４以上のダミー電極及び前記複数の電極のそれぞれは、同一ピッチで配置されているものである。このような構成を有することによって、さらに確実に半導体チップとフレキシブル配線基板との接続不良を抑制することができる。   The chip-on-film semiconductor device according to the third aspect of the present invention is the above-described chip-on-film semiconductor device, wherein each of the four or more dummy lead terminals and the plurality of lead terminals are arranged at the same pitch, Each of the four or more dummy electrodes and the plurality of electrodes are arranged at the same pitch. By having such a configuration, it is possible to more reliably suppress poor connection between the semiconductor chip and the flexible wiring board.

本発明の第４の態様にかかるチップオンフィルム半導体装置は、上記のチップオンフィルム半導体装置において、前記４以上のダミーリード端子及び前記複数のリード端子のそれぞれは、同一形状であり、前記４以上のダミー電極及び前記複数の電極のそれぞれは、同一形状であるものである。このような構成を有することによって、さらに確実に半導体チップとフレキシブル配線基板との接続不良を抑制することができる。   The chip-on-film semiconductor device according to a fourth aspect of the present invention is the above-described chip-on-film semiconductor device, wherein each of the four or more dummy lead terminals and the plurality of lead terminals have the same shape, and the four or more Each of the dummy electrodes and the plurality of electrodes have the same shape. By having such a configuration, it is possible to more reliably suppress poor connection between the semiconductor chip and the flexible wiring board.

本発明の第５の態様にかかるチップオンフィルム半導体装置は、上記のチップオンフィルム半導体装置において、前記４以上のダミーリード端子及び前記複数のリード端子のそれぞれは、同一の材料で形成されており、前記４以上のダミー電極及び前記複数の電極のそれぞれは、同一の材料で形成されているものである。このような構成を有することによって、さらに確実に半導体チップとフレキシブル配線基板との接続不良を抑制することができる。   The chip-on-film semiconductor device according to a fifth aspect of the present invention is the above-described chip-on-film semiconductor device, wherein each of the four or more dummy lead terminals and the plurality of lead terminals are formed of the same material. Each of the four or more dummy electrodes and the plurality of electrodes are formed of the same material. By having such a configuration, it is possible to more reliably suppress poor connection between the semiconductor chip and the flexible wiring board.

本発明により、半導体チップとフレキシブル配線基板との接続不良を抑制した半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device in which connection failure between a semiconductor chip and a flexible wiring board is suppressed.

本発明の実施の形態にかかる半導体装置について、図１及び図２を参照して説明する。図１は、本実施の形態にかかるチップオンフィルム半導体装置１００の構成を模式的に示す平面図である。図２は、本実施の形態にかかるチップオンフィルム半導体装置１００の構成の一部を示す断面図である。図１に示すように、チップオンフィルム半導体装置１００は、フレキシブル配線基板（Flexible Printed Circuit：以下、ＦＰＣとする。）１０１と、半導体チップ１０２とを有する。なお、図１において、半導体チップ１０２によって見えない部分を破線で示している。   A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view schematically showing a configuration of a chip-on-film semiconductor device 100 according to the present embodiment. FIG. 2 is a cross-sectional view showing a part of the configuration of the chip-on-film semiconductor device 100 according to the present embodiment. As shown in FIG. 1, the chip-on-film semiconductor device 100 includes a flexible printed circuit (hereinafter referred to as FPC) 101 and a semiconductor chip 102. In FIG. 1, a portion that cannot be seen by the semiconductor chip 102 is indicated by a broken line.

ＦＰＣ１０１は、半導体チップ１０２を支持する基板となる。ＦＰＣ１０１は、半導体チップ１０２の辺に沿って互いに近接して配列された複数のリード端子１０３からなるリード端子群１１０を有している。図１に示すように、ＦＰＣ１０１の５箇所にリード端子群１１０が設けられている。本例の各リード端子群１１０において、同一ピッチで複数のリード端子１０３が一列に配列されている。各リード端子群１１０の両端には、それぞれ、４つのダミーリード端子１０４からなるダミーリード端子郡１２０が設けられる。各ダミーリード端子群１２０において、ダミーリード端子１０４は半導体チップ１０２の辺に沿って互いに近接して配列されている。   The FPC 101 is a substrate that supports the semiconductor chip 102. The FPC 101 includes a lead terminal group 110 including a plurality of lead terminals 103 arranged close to each other along the side of the semiconductor chip 102. As shown in FIG. 1, lead terminal groups 110 are provided at five locations on the FPC 101. In each lead terminal group 110 of this example, a plurality of lead terminals 103 are arranged in a line at the same pitch. At both ends of each lead terminal group 110, a dummy lead terminal group 120 including four dummy lead terminals 104 is provided. In each dummy lead terminal group 120, the dummy lead terminals 104 are arranged close to each other along the side of the semiconductor chip 102.

本例において、ダミーリード端子１０４は、対応するリード端子群１１０のリード端子１０３間ピッチと同一ピッチで設けられている。また、ダミーリード端子１０４は、対応するリード端子群１１０のリード端子１０３と同一形状であり、同一の材料で形成されている。各リード端子１０３は信号伝送に使用されるが、各ダミーリード端子１０４は信号伝送せず、ＦＰＣ１０１と半導体チップ１０２との間の物理的相互接続のために設けられている。   In this example, the dummy lead terminals 104 are provided at the same pitch as the pitch between the lead terminals 103 of the corresponding lead terminal group 110. The dummy lead terminals 104 have the same shape as the lead terminals 103 of the corresponding lead terminal group 110 and are formed of the same material. Each lead terminal 103 is used for signal transmission, but each dummy lead terminal 104 does not transmit a signal and is provided for physical interconnection between the FPC 101 and the semiconductor chip 102.

図１に示すように、半導体チップ１０２には複数のバンプ電極群１３０が設けられ、それぞれは、ＦＰＣ１０１上に設けられたリード端子群１１０のそれぞれと対向する位置にある。従って、バンプ電極群１３０は、半導体チップ１０２の５箇所に設けられている。図２に示すように、各バンプ電極群１３０は、半導体チップ１０２の辺に沿って互いに近接して配列された複数のバンプ電極１０５から構成されている。本例において、各バンプ電極１０５は、各リード端子１０３と同一ピッチで配置されている。すなわち、それぞれのバンプ電極１０５は、半導体チップ１０２上に、ＦＰＣ１０１に設けられたそれぞれのリード端子１０３と対向するように設けられる。   As shown in FIG. 1, a plurality of bump electrode groups 130 are provided on the semiconductor chip 102, and each is in a position facing each of the lead terminal groups 110 provided on the FPC 101. Therefore, the bump electrode group 130 is provided at five locations on the semiconductor chip 102. As shown in FIG. 2, each bump electrode group 130 includes a plurality of bump electrodes 105 arranged close to each other along the side of the semiconductor chip 102. In this example, the bump electrodes 105 are arranged at the same pitch as the lead terminals 103. That is, each bump electrode 105 is provided on the semiconductor chip 102 so as to face each lead terminal 103 provided on the FPC 101.

各バンプ電極群１３０の両端には、それぞれ、ダミーバンプ電極郡１４０が配置される。本例において、各ダミーバンプ電極郡１４０は、４つのダミーバンプ電極１０６から構成されており、４つのダミーバンプ電極１０６は、バンプ電極１０５と同様に、半導体チップ１０２の辺に沿う方向に互いに近接して配列されている。図２に示すように、４つのダミーバンプ電極１０６は、半導体チップ１０２上に、ＦＰＣ１０１上に設けられた４つのダミーリード端子１０４とそれぞれ対向する位置に設けられる。ダミーバンプ電極１０６は、対応するバンプ電極群１３０のバンプ電極１０５のピッチと等しいピッチで設けられる。   Dummy bump electrode groups 140 are disposed at both ends of each bump electrode group 130, respectively. In this example, each dummy bump electrode group 140 is composed of four dummy bump electrodes 106, and the four dummy bump electrodes 106 are arranged close to each other in the direction along the side of the semiconductor chip 102, like the bump electrodes 105. Has been. As shown in FIG. 2, the four dummy bump electrodes 106 are provided on the semiconductor chip 102 at positions facing the four dummy lead terminals 104 provided on the FPC 101. The dummy bump electrodes 106 are provided at a pitch equal to the pitch of the bump electrodes 105 of the corresponding bump electrode group 130.

すなわち、ダミーバンプ電極１０６もまた、対応するリード端子１０３略同一ピッチで形成される。また、ダミーバンプ電極１０６は、対応するバンプ電極群１３０のバンプ電極１０５と同一形状であり、同一の材料で形成されている。各バンプ電極１０５は信号伝送に使用されるが、各ダミーバンプ電極１０６は信号伝送せず、ＦＰＣ１０１と半導体チップ１０２との間の物理的相互接続のために設けられている。   That is, the dummy bump electrodes 106 are also formed at substantially the same pitch as the corresponding lead terminals 103. The dummy bump electrodes 106 have the same shape as the bump electrodes 105 of the corresponding bump electrode group 130 and are formed of the same material. Each bump electrode 105 is used for signal transmission, but each dummy bump electrode 106 does not transmit signal, and is provided for physical interconnection between the FPC 101 and the semiconductor chip 102.

ＦＰＣ１０１と半導体チップ１０２とは、ＮＣＦ（Non-Conductive Film）で固着されている。ＮＣＦは導電粒子を含有しない熱硬化性の接着シートである。このため、各リード端子１０３と各バンプ電極１０５とは互いに接触して直接に接続され、それらの間の導通が確保されている。   The FPC 101 and the semiconductor chip 102 are fixed by NCF (Non-Conductive Film). NCF is a thermosetting adhesive sheet that does not contain conductive particles. For this reason, each lead terminal 103 and each bump electrode 105 are in direct contact with each other, and are electrically connected.

ここで、上述の半導体装置１００のリード端子１０３とバンプ電極１０５との接続方法について説明する。まず、ＦＰＣ１０１に設けられたリード端子１０３上にＮＣＦを配置する。その上に、半導体チップ１０２のバンプ電極１０５とＦＰＣ１０１のリード端子１０３とを位置合わせした状態で、かつ、ダミーリード端子１０４とダミーバンプ電極１０６とを位置合わせした状態で、半導体チップ１０２を載置する。そして、半導体チップ１０２をＦＰＣ１０１に押しつけるとともに加熱する。これにより、ＦＰＣ１０１と半導体チップ１０２とは熱硬化したＮＣＦによって固着され、リード端子１０３とバンプ電極１０５とは直接接続される。   Here, a method for connecting the lead terminal 103 and the bump electrode 105 of the semiconductor device 100 will be described. First, the NCF is disposed on the lead terminal 103 provided in the FPC 101. On top of that, the semiconductor chip 102 is placed with the bump electrodes 105 of the semiconductor chip 102 and the lead terminals 103 of the FPC 101 aligned, and with the dummy lead terminals 104 and the dummy bump electrodes 106 aligned. . Then, the semiconductor chip 102 is pressed against the FPC 101 and heated. Thereby, the FPC 101 and the semiconductor chip 102 are fixed by the thermally cured NCF, and the lead terminal 103 and the bump electrode 105 are directly connected.

ＮＣＦを用いた実装では、バンプ電極１０５とリード端子１０３とを直接接続させるため、大きな圧力をかけて熱圧着する必要があり、熱と圧力によりＦＰＣ１０１が大きく歪む。上述のように、ダミーリード端子１０４及びダミーバンプ電極１０６を備えていない従来の構成においては、ＦＰＣのリード端子群のうち、端から１〜４番目において接続不良が発生する。   In mounting using NCF, since the bump electrode 105 and the lead terminal 103 are directly connected, it is necessary to apply thermocompression by applying a large pressure, and the FPC 101 is greatly distorted by heat and pressure. As described above, in the conventional configuration that does not include the dummy lead terminal 104 and the dummy bump electrode 106, connection failure occurs at the first to fourth positions from the end of the FPC lead terminal group.

しかしながら、本実施形態の構成によると、４つのダミーリード端子１０４及び４つのダミーバンプ電極１０６により、リード端子１０３とバンプ電極１０５との接続時に発生する、接続に必要なリード端子１０３とバンプ電極１０５形成領域のＦＰＣ１０１の歪みを抑制できる。したがって、リード端子１０３とバンプ電極１０５との接続工程において、リード端子１０３とバンプ電極１０５との間における接続不良の発生を抑制することができる。   However, according to the configuration of the present embodiment, formation of the lead terminal 103 and the bump electrode 105 necessary for connection, which is generated when the lead terminal 103 and the bump electrode 105 are connected by the four dummy lead terminals 104 and the four dummy bump electrodes 106. The distortion of the FPC 101 in the area can be suppressed. Therefore, it is possible to suppress the occurrence of poor connection between the lead terminal 103 and the bump electrode 105 in the connection step between the lead terminal 103 and the bump electrode 105.

本実施の形態においては、４つのダミーリード端子１０４及び４つのダミーバンプ電極１０６をリード端子１０３及びバンプ電極１０５と同一ピッチで形成した。このため、接続に必要なリード端子１０３とバンプ電極１０５形成領域のＦＰＣ１０１の歪みを効果的に抑制することができる。なお、本実施の形態においては、４つのダミーリード端子１０４及びダミーバンプ電極１０６を形成したが、これに限らず、４つ以上のダミーリード端子１０４及びダミーバンプ電極１０６を形成してもよい。また、リード端子群１１０及びバンプ電極群１３０の両端に、それぞれ、４つ以上のダミーリード端子１０４及びダミーバンプ電極１０６を設けることが好ましいが、その一方のみに設けることを妨げるものではない。   In the present embodiment, four dummy lead terminals 104 and four dummy bump electrodes 106 are formed at the same pitch as the lead terminals 103 and bump electrodes 105. For this reason, the distortion of the FPC 101 in the formation region of the lead terminal 103 and the bump electrode 105 necessary for connection can be effectively suppressed. In this embodiment, four dummy lead terminals 104 and dummy bump electrodes 106 are formed. However, the present invention is not limited to this, and four or more dummy lead terminals 104 and dummy bump electrodes 106 may be formed. Further, it is preferable to provide four or more dummy lead terminals 104 and dummy bump electrodes 106 at both ends of the lead terminal group 110 and the bump electrode group 130, respectively, but this does not prevent the provision of only one of them.

また、ダミーリード端子１０４をリード端子１０３と、ダミーバンプ電極１０６をバンプ電極１０５と同一材料で同一形状に形成した。このため、リード端子１０３とバンプ電極１０５との接続時に、押圧により発生するリード端子１０３及びバンプ電極１０５の変形とダミーリード端子１０４をリード端子１０３の変形とが略等しくなる。したがって、接続に必要なリード端子１０３とバンプ電極１０５形成領域のＦＰＣ１０１の歪みを効果的に抑制することができる。   The dummy lead terminals 104 and the dummy bump electrodes 106 are formed of the same material and in the same shape as the bump electrodes 105. For this reason, when the lead terminal 103 and the bump electrode 105 are connected, the deformation of the lead terminal 103 and the bump electrode 105 generated by pressing and the deformation of the dummy lead terminal 104 and the lead terminal 103 are substantially equal. Therefore, the distortion of the FPC 101 in the formation region of the lead terminal 103 and the bump electrode 105 necessary for connection can be effectively suppressed.

なお、本実施の形態においては、ダミーリード端子１０４をリード端子１０３と同一形状、同一の材料で形成し、ダミーバンプ電極１０６をバンプ電極１０５と同一形状、同一の材料で形成したが、これに限定されるものではなく、異なる形状、材料で形成してもよい。しかし、歪量低減の点から、リード端子１０３の高さとバンプ電極１０５の高さとを合わせた高さは、ダミーリード端子１０４の高さとダミーバンプ電極１０６の高さとを合わせた高さに等しいことが好ましい。なお、異なるリード端子群１１０間は、異なる形状、ピッチのリード端子１０３から構成され、あるいは、異なるバンプ電極群１３０間は、異なる形状、ピッチのバンプ電極１０５から構成されていてよい。   In this embodiment, the dummy lead terminal 104 is formed of the same shape and the same material as the lead terminal 103, and the dummy bump electrode 106 is formed of the same shape and the same material as the bump electrode 105. However, the present invention is not limited to this. However, it may be formed of different shapes and materials. However, from the viewpoint of reducing the amount of distortion, the total height of the lead terminal 103 and the bump electrode 105 is equal to the total height of the dummy lead terminal 104 and the dummy bump electrode 106. preferable. The different lead terminal groups 110 may be constituted by lead terminals 103 having different shapes and pitches, or the different bump electrode groups 130 may be constituted by bump electrodes 105 having different shapes and pitches.

また、本実施の形態においては、ＦＰＣ１０１と半導体チップ１０２とが熱硬化したＮＣＦによって固着され、リード端子１０３とバンプ電極１０５とが直接接続される構成について説明したが、これに限定されない。本発明は、例えば、リード端子１０３とバンプ電極１０５とをＡＣＦを介して接続し、ＡＣＦ中の導電粒子によりリード端子１０３とバンプ電極１０５との間の導通が確保されている場合などにも適用することが可能である。   In the present embodiment, the FPC 101 and the semiconductor chip 102 are fixed by the thermally cured NCF, and the lead terminal 103 and the bump electrode 105 are directly connected. However, the present invention is not limited to this. The present invention is also applicable to the case where, for example, the lead terminal 103 and the bump electrode 105 are connected via the ACF, and conduction between the lead terminal 103 and the bump electrode 105 is ensured by the conductive particles in the ACF. Is possible.

実施の形態にかかる半導体装置の構成を示す平面図である。1 is a plan view showing a configuration of a semiconductor device according to an embodiment. 実施の形態にかかる半導体装置の構成の一部を示す断面図である。It is sectional drawing which shows a part of structure of the semiconductor device concerning embodiment. 従来の半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor device.

符号の説明Explanation of symbols

１００ 半導体チップ
１０１ バンプ電極
１０２ フレキシブル配線基板
１０３ リード端子
１０４ ダミーリード端子
１０５ バンプ電極
１０６ ダミーバンプ電極
１１０ リード端子群
１２０ ダミーリード端子群
１３０ バンプ電極群
１４０ ダミーバンプ電極群 100 Semiconductor chip 101 Bump electrode 102 Flexible wiring board 103 Lead terminal 104 Dummy lead terminal 105 Bump electrode 106 Dummy bump electrode 110 Lead terminal group 120 Dummy lead terminal group 130 Bump electrode group 140 Dummy bump electrode group

Claims (5)

その辺に沿って近接して配列された複数の電極を有する半導体チップと、
前記半導体チップが接着剤によってその上に固着され、前記複数の電極のそれぞれと対向しその対向する電極に接続された複数のリード端子を有するフレキシブル配線基板と、
を備えるチップオンフィルム半導体装置であって、
前記フレキシブル配線基板は、前記複数のリード端子の端に４以上のダミーリード端子を備え、
前記半導体チップは、前記４以上のダミーリード端子のそれぞれに対向する４以上のダミー電極を備えている、チップオンフィルム半導体装置。 A semiconductor chip having a plurality of electrodes arranged close to each other along the side;
The semiconductor chip is fixed thereon by an adhesive, and a flexible wiring substrate having a plurality of lead terminals facing each of the plurality of electrodes and connected to the facing electrodes;
A chip-on-film semiconductor device comprising:
The flexible wiring board includes four or more dummy lead terminals at an end of the plurality of lead terminals,
The chip-on-film semiconductor device, wherein the semiconductor chip includes four or more dummy electrodes facing each of the four or more dummy lead terminals. 前記フレキシブル配線基板は、前記複数のリード端子の両端のそれぞれに、４以上のダミーリード端子を備え、
前記半導体チップは、前記複数のリード端子の両端のそれぞれにおいて、前記４以上のダミーリード端子のそれぞれに対向する４以上のダミー電極を備えている、
請求項１に記載のチップオンフィルム半導体装置。 The flexible wiring board includes four or more dummy lead terminals at each of both ends of the plurality of lead terminals,
The semiconductor chip includes four or more dummy electrodes facing each of the four or more dummy lead terminals at each of both ends of the plurality of lead terminals.
The chip-on-film semiconductor device according to claim 1. 前記４以上のダミーリード端子及び前記複数のリード端子のそれぞれは、同一ピッチで配置されており、
前記４以上のダミー電極及び前記複数の電極のそれぞれは、同一ピッチで配置されている、
請求項１または２に記載のチップオンフィルム半導体装置。 Each of the four or more dummy lead terminals and the plurality of lead terminals are arranged at the same pitch,
Each of the four or more dummy electrodes and the plurality of electrodes are arranged at the same pitch,
The chip-on-film semiconductor device according to claim 1 or 2. 前記４以上のダミーリード端子及び前記複数のリード端子のそれぞれは、同一形状であり、
前記４以上のダミー電極及び前記複数の電極のそれぞれは、同一形状である、
請求項１、２または３に記載のチップオンフィルム半導体装置。 Each of the four or more dummy lead terminals and the plurality of lead terminals have the same shape,
Each of the four or more dummy electrodes and the plurality of electrodes have the same shape.
The chip-on-film semiconductor device according to claim 1, 2 or 3. 前記４以上のダミーリード端子及び前記複数のリード端子のそれぞれは、同一の材料で形成されており、
前記４以上のダミー電極及び前記複数の電極のそれぞれは、同一の材料で形成されている、
請求項１、２、３または４に記載のチップオンフィルム半導体装置。 Each of the four or more dummy lead terminals and the plurality of lead terminals are formed of the same material,
Each of the four or more dummy electrodes and the plurality of electrodes are formed of the same material,
The chip-on-film semiconductor device according to claim 1, 2, 3 or 4.
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US9332641B2 (en) 2012-11-08 2016-05-03 Samsung Display Co., Ltd. Connection structure of circuit board

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