JPH10308413A - Electronic component and electronic component mount module - Google Patents

Electronic component and electronic component mount module

Info

Publication number
JPH10308413A
JPH10308413A JP9131650A JP13165097A JPH10308413A JP H10308413 A JPH10308413 A JP H10308413A JP 9131650 A JP9131650 A JP 9131650A JP 13165097 A JP13165097 A JP 13165097A JP H10308413 A JPH10308413 A JP H10308413A
Authority
JP
Japan
Prior art keywords
connection terminals
electronic component
semiconductor chip
dummy
connection terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9131650A
Other languages
Japanese (ja)
Inventor
Hiroshi Onizuka
尋志 鬼塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9131650A priority Critical patent/JPH10308413A/en
Publication of JPH10308413A publication Critical patent/JPH10308413A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a defeat in connection from being caused when a semiconductor chip which has a connection terminal at part of the circumference of the reverse surface is mounted on a liquid crystal display panel by thermocompression bonding with an anisotropic conductive agent. SOLUTION: At the reverse surface periphery of a semiconductor chip 4, a dummy connection terminal 11 is provided where the connection terminal 6 is not provided. Consequently, when the semiconductor chip 4 is bonded onto the liquid crystal display panel 1 by thermocompression across the anisotropic conductive adhesive 7, pressure can be applied to an insulating adhesive 8 by the connection terminal 6 of the semiconductor chip 4 and pressure can be applied to the insulating by the dummy connection terminal 11 as well. Consequently, a connection defective which is possibly caused when the dummy connection terminal 11 is absent can be eliminated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は電子部品及び電子
部品搭載モジュールに関する。
The present invention relates to an electronic component and an electronic component mounting module.

【0002】[0002]

【従来の技術】例えば液晶表示装置(電子部品搭載モジ
ュール)には、液晶表示パネルを駆動するためのLSI
チップ等からなる半導体チップ(電子部品)を液晶表示
パネルに異方導電性接着剤を介して搭載したものがあ
る。
2. Description of the Related Art For example, an LSI for driving a liquid crystal display panel is provided in a liquid crystal display device (electronic component mounting module).
2. Description of the Related Art There is a liquid crystal display panel in which a semiconductor chip (electronic component) including a chip or the like is mounted via an anisotropic conductive adhesive.

【0003】図4は従来のこのような液晶表示装置の一
例の一部を示したものである。この図に示す液晶表示パ
ネル1は、ガラスや樹脂等からなる下側の透明基板2と
図示しない上側の透明基板とを備え、下側の透明基板1
の一部が上側の透明基板から突出され、この突出部分の
上面に接続端子3が複数設けられた構造となっている。
半導体チップ4は、チップ本体5の下面周辺部の所定の
箇所に金バンプ等からなる接続端子6が複数設けられた
構造となっている。異方導電性接着剤7は、絶縁性接着
剤8中に導電性粒子9を混入したものからなっている。
FIG. 4 shows a part of an example of such a conventional liquid crystal display device. The liquid crystal display panel 1 shown in FIG. 1 includes a lower transparent substrate 2 made of glass, resin, or the like, and an upper transparent substrate (not shown).
Are protruded from the upper transparent substrate, and a plurality of connection terminals 3 are provided on the upper surface of the protruding portion.
The semiconductor chip 4 has a structure in which a plurality of connection terminals 6 made of gold bumps or the like are provided at predetermined positions on the periphery of the lower surface of the chip body 5. The anisotropic conductive adhesive 7 is formed by mixing conductive particles 9 into an insulating adhesive 8.

【0004】次に、半導体チップ4を下側の透明基板2
上に異方導電性接着剤7を介して搭載する場合について
説明する。まず、下側の透明基板2の接続端子3を含む
接続部分上に異方導電性接着剤7を載置し、その上に半
導体チップ4を載置する。次に、熱圧着すると、このと
きの圧力により半導体チップ4の接続端子6が下側の透
明基板2の接続端子3に接近し、その間に介在された絶
縁性接着剤8が熱と圧力を受けてその一部が流動して逃
げるとともに、この部分に存在する導電性粒子9が相対
向する接続端子3、6に共に接触し、これにより、相対
向する接続端子3、6が互いに導電接続される。また、
絶縁性接着剤8が固化することにより、半導体チップ4
の下面が下側の透明基板2の接続端子3を含む接続部分
上に接着される。かくして、半導体チップ4は下側の透
明基板2上に搭載されることになる。
Next, the semiconductor chip 4 is placed on the lower transparent substrate 2.
A case in which the semiconductor device is mounted via the anisotropic conductive adhesive 7 will be described. First, the anisotropic conductive adhesive 7 is placed on the connection portion including the connection terminal 3 of the lower transparent substrate 2, and the semiconductor chip 4 is placed thereon. Next, when thermocompression bonding is performed, the pressure at this time causes the connection terminals 6 of the semiconductor chip 4 to approach the connection terminals 3 of the lower transparent substrate 2, and the insulating adhesive 8 interposed therebetween receives heat and pressure. A portion of the conductive particles 9 flow and escape, and the conductive particles 9 present in this portion come into contact with the facing connection terminals 3 and 6, whereby the facing connection terminals 3 and 6 are conductively connected to each other. You. Also,
By solidifying the insulating adhesive 8, the semiconductor chip 4
Is adhered on the connection portion including the connection terminal 3 of the lower transparent substrate 2. Thus, the semiconductor chip 4 is mounted on the lower transparent substrate 2.

【0005】ここで、半導体チップ4のチップ本体5の
下面に設けられた接続端子6の具体的な配置の一例につ
いて、図5を参照して説明する。チップ本体5の下面は
長方形状となっている。このチップ本体5の下面の左端
部、上端部の左半分及び下端部の左半分には入力側接続
端子6aがそれぞれ一列に配置され、上端部の右半分に
は出力側接続端子6bが千鳥状に配置されている。
Here, an example of a specific arrangement of the connection terminals 6 provided on the lower surface of the chip body 5 of the semiconductor chip 4 will be described with reference to FIG. The lower surface of the chip body 5 has a rectangular shape. Input connection terminals 6a are arranged in a row at the left end of the lower surface of the chip body 5, the left half of the upper end, and the left half of the lower end, and the output connection terminals 6b are staggered at the right half of the upper end. Are located in

【0006】[0006]

【発明が解決しようとする課題】すなわち、従来のこの
ような半導体チップ4では、チップ本体5の下面の右端
部及び下端部の右半分に接続端子6a、6bが設けられ
ていない。この結果、半導体チップ4を下側の透明基板
2上にその間に異方導電性接着剤7を介在させた状態で
熱圧着するとき、半導体チップ4の接続端子6a、6b
が設けられていない部分、特にチップ本体5の下面の右
下部下に存在する絶縁性接着剤8に圧力が加わりにく
く、この影響を受けて、その近傍の接続端子6a、6b
が設けられている部分、特にチップ本体5の下面の右上
部下に存在する絶縁性接着剤8にも圧力が加わりにくく
なる。このように、接続端子6a、6bが設けられてい
る部分下に存在する絶縁性接着剤8に十分な圧力が加わ
らないと、当該接続端子6a、6bとこれに対向する接
続端子3との間に介在された絶縁性接着剤8の一部が所
期の通り逃げず、この部分に存在する導電性粒子9が当
該接続端子6a、6bとこれに対向する接続端子3とに
共に所期の通り接触しにくくなり、接続不良が生じるこ
とがあるという問題があった。この発明の課題は、接続
不良が生じないようにすることである。
That is, in such a conventional semiconductor chip 4, the connection terminals 6a and 6b are not provided at the right end of the lower surface of the chip body 5 and the right half of the lower end. As a result, when the semiconductor chip 4 is thermocompression-bonded to the lower transparent substrate 2 with the anisotropic conductive adhesive 7 interposed therebetween, the connection terminals 6a, 6b of the semiconductor chip 4
Is hardly applied to the portion where no is provided, particularly the insulating adhesive 8 existing under the lower right of the lower surface of the chip body 5, and under the influence of this, the connection terminals 6a and 6b in the vicinity thereof are affected.
The pressure is less likely to be applied to the portion where the is provided, especially the insulating adhesive 8 existing below the upper right portion of the lower surface of the chip body 5. As described above, if sufficient pressure is not applied to the insulating adhesive 8 existing below the portion where the connection terminals 6a and 6b are provided, the connection between the connection terminals 6a and 6b and the connection terminal 3 facing the connection terminals 6a and 6b will not occur. A part of the insulating adhesive 8 interposed between the connecting terminals 6a and 6b and the connecting terminal 3 opposed to the connecting terminals 6a and 6b is not expected. This makes it difficult to make contact, and there is a problem that poor connection may occur. An object of the present invention is to prevent a connection failure from occurring.

【0007】[0007]

【課題を解決するための手段】請求項1記載の発明に係
る電子部品は、方形状の領域内の所定の箇所に複数の接
続端子が設けられ、前記領域内の他の所定の箇所に複数
のダミー接続端子が設けられ、前記領域の左半分及び右
半分と上半分及び下半分とのうち少なくとも一方の両半
分において、前記接続端子及び前記ダミー接続端子のう
ち前記両半分にそれぞれ設けられたものの各合計面積比
が一方を1としたとき他方を1〜1.5としたものであ
る。請求項2記載の発明に係る電子部品搭載モジュール
は、方形状の領域内の所定の箇所に複数の接続端子が設
けられ、前記領域内の他の所定の箇所に複数のダミー接
続端子が設けられ、前記領域の左半分及び右半分と上半
分及び下半分とのうち少なくとも一方の両半分におい
て、前記接続端子及び前記ダミー接続端子のうち前記両
半分にそれぞれ設けられたものの各合計面積比が一方を
1としたとき他方を1〜1.5とされた電子部品を、該
電子部品の接続端子と対応する部分に接続端子が設けら
れた基板上に搭載したものである。
According to a first aspect of the present invention, there is provided an electronic component, wherein a plurality of connection terminals are provided at a predetermined location in a rectangular area, and a plurality of connection terminals are provided at another predetermined location in the area. Are provided in at least one of the left half and the right half and at least one of the upper half and the lower half of the region, and are provided in the two halves of the connection terminal and the dummy connection terminal, respectively. Each of the total area ratios is 1 to 1 when the other is 1 to 1.5. In the electronic component mounting module according to the second aspect of the present invention, a plurality of connection terminals are provided at a predetermined location in the rectangular area, and a plurality of dummy connection terminals are provided at another predetermined location in the area. In at least one of the left and right halves and the upper and lower halves of the region, the total area ratio of the connection terminals and the dummy connection terminals provided in the two halves is one. When the electronic component is set to 1, the other electronic component is set to 1 to 1.5, and the electronic component is mounted on a substrate provided with connection terminals at portions corresponding to the connection terminals of the electronic component.

【0008】この発明によれば、方形状の領域内に接続
端子のほかにダミー接続端子を設け、これら接続端子の
総合的な面積関係をある所定の関係としたので、例えば
電子部品を基板上にその間に異方導電性接着剤を介在さ
せた状態で熱圧着する場合、接続端子が設けられていな
い部分においてはダミー接続端子によって絶縁性接着剤
に圧力を十分に加えることができ、これに伴いダミー接
続端子の近傍における接続端子によっても絶縁性接着剤
に圧力を十分に加えることができ、これにより接続不良
が生じないようにすることができる。
According to the present invention, dummy connection terminals are provided in addition to the connection terminals in the rectangular area, and the total area relation of these connection terminals is set to a predetermined relation. In the case where thermocompression bonding is performed with an anisotropic conductive adhesive interposed between them, in areas where connection terminals are not provided, sufficient pressure can be applied to the insulating adhesive by means of dummy connection terminals. Accordingly, a sufficient pressure can be applied to the insulating adhesive by the connection terminals in the vicinity of the dummy connection terminals, so that a connection failure can be prevented.

【0009】[0009]

【発明の実施の形態】図1はこの発明の一実施形態を適
用した液晶表示装置の一部を示し、図2はこの液晶表示
装置における半導体チップの下面を示したものである。
これらの図において、図4及び図5と同一名称部分には
同一の符号を付し、その説明を適宜省略する。ただし、
図1は図2のA−A線に沿う断面図に相当するものであ
る。
FIG. 1 shows a part of a liquid crystal display device to which an embodiment of the present invention is applied, and FIG. 2 shows a lower surface of a semiconductor chip in the liquid crystal display device.
In these drawings, the same reference numerals are given to the same parts as those in FIGS. 4 and 5, and the description thereof will be omitted as appropriate. However,
FIG. 1 corresponds to a cross-sectional view taken along line AA of FIG.

【0010】図2に示すように、半導体チップ4のチッ
プ本体5の長方形状の下面の左端部、上端部の左半分及
び下端部の左半分には、図5に示す従来例の場合と同様
に、入力側接続端子6aがそれぞれ1列に設けられ、上
端部の右半分には、これまた図5に示す従来例の場合と
同様に、出力側接続端子6bが千鳥状に設けられてい
る。この実施形態における半導体チップ4において図5
に示す従来例の場合と異なる点は、チップ本体5の下面
の右端部及び下端部の右半分にダミー接続端子11がそ
れぞれ1列に設けられている点と、次に述べる点であ
る。
As shown in FIG. 2, the left end of the rectangular lower surface of the chip body 5 of the semiconductor chip 4, the left half of the upper end, and the left half of the lower end are similar to those in the conventional example shown in FIG. The input-side connection terminals 6a are provided in a row, and the output-side connection terminals 6b are provided in the right half of the upper end in a staggered manner, as in the case of the conventional example shown in FIG. . In the semiconductor chip 4 in this embodiment, FIG.
Are different from the conventional example shown in FIG. 1 in that dummy connection terminals 11 are provided in one row at the right end of the lower surface of the chip body 5 and the right half of the lower end thereof, respectively, and the following point.

【0011】次に、半導体チップ4のチップ本体5の長
方形状の下面(方形状の領域)に設けられた接続端子6
a、6b及びダミー接続端子11の総合的な面積関係に
ついて説明する。チップ本体5の下面の左半分に設けら
れた入力側接続端子6aの合計面積とチップ本体5の下
面の右半分に設けられた出力側接続端子6b及びダミー
接続端子11の合計面積との比は、一方を1としたとき
他方を1〜1.5とする。また、チップ本体5の下面の
上半分に設けられた入力側接続端子6a、出力側接続端
子6b及びダミー接続端子11の合計面積とチップ本体
5の下面の下半分に設けられた入力側接続端子6a及び
ダミー接続端子11の合計面積との比は、一方を1とし
たとき他方を1〜1.5とする。
Next, the connection terminals 6 provided on the rectangular lower surface (square region) of the chip body 5 of the semiconductor chip 4
The overall area relationship between a, 6b and the dummy connection terminal 11 will be described. The ratio of the total area of the input-side connection terminals 6a provided on the left half of the lower surface of the chip body 5 to the total area of the output-side connection terminals 6b and the dummy connection terminals 11 provided on the right half of the lower surface of the chip body 5 is When one is set to 1, the other is set to 1 to 1.5. Further, the total area of the input-side connection terminals 6a, the output-side connection terminals 6b, and the dummy connection terminals 11 provided in the upper half of the lower surface of the chip body 5, and the input-side connection terminals provided in the lower half of the lower surface of the chip body 5 The ratio of 6a to the total area of the dummy connection terminals 11 is 1 to 1.5 when one is 1.

【0012】このようにすると、接続端子6a、6b及
びダミー接続端子11によって絶縁性接着剤8をほぼ均
等に加圧することができる。この結果、半導体チップ4
を下側の透明基板2上にその間に異方導電性接着剤7を
介在させた状態で熱圧着する場合、半導体チップ4の接
続端子6a、6bが設けられていない部分においてはダ
ミー接続端子11によって絶縁性接着剤8に圧力を十分
に加えることができ、これに伴いダミー接続端子11の
近傍における接続端子6a、6bによっても絶縁性接着
剤8に圧力を十分に加えることができる。したがって、
当該接続端子6a、6bとこれに対向する接続端子3と
の間に介在された絶縁性接着剤8の一部が良好に逃げ、
この部分に存在する導電性粒子9が当該接続端子6a、
6bとこれに対向する接続端子3とに共に良好に接触
し、接続不良が生じないようにすることができる。
In this manner, the insulating adhesive 8 can be pressed almost uniformly by the connection terminals 6a and 6b and the dummy connection terminals 11. As a result, the semiconductor chip 4
Is thermocompression-bonded onto the lower transparent substrate 2 with the anisotropic conductive adhesive 7 interposed therebetween, the dummy connection terminals 11 are provided in portions of the semiconductor chip 4 where the connection terminals 6a and 6b are not provided. Accordingly, sufficient pressure can be applied to the insulating adhesive 8, and accordingly, the connecting terminals 6 a and 6 b in the vicinity of the dummy connection terminal 11 can sufficiently apply pressure to the insulating adhesive 8. Therefore,
Part of the insulating adhesive 8 interposed between the connection terminals 6a and 6b and the connection terminal 3 facing the connection terminals 6a and 6b escapes favorably,
The conductive particles 9 existing in this portion are connected to the connection terminal 6a,
6b and the opposing connection terminal 3 are in good contact with each other, so that poor connection can be prevented.

【0013】なお、上記実施形態では、半導体チップ4
の下面のみにダミー接続端子11を設けた場合について
説明したが、これに限らず、例えば図3に示すように、
下側の透明基板2の上面において半導体チップ4のダミ
ー接続端子11と対応する部分にもダミー接続端子12
を設けるようにしてもよい。このようにすると、相対向
する接続端子3、6間における熱圧着条件とダミー接続
端子11、12間における熱圧着条件とをほぼ同じとす
ることができ、ひいてはより一層接続不良が生じないよ
うにすることができる。
In the above embodiment, the semiconductor chip 4
The case where the dummy connection terminal 11 is provided only on the lower surface of the above has been described. However, the present invention is not limited to this. For example, as shown in FIG.
Dummy connection terminals 12 are also provided on the upper surface of lower transparent substrate 2 at portions corresponding to dummy connection terminals 11 of semiconductor chip 4.
May be provided. In this manner, the thermocompression bonding conditions between the opposing connection terminals 3 and 6 and the thermocompression bonding conditions between the dummy connection terminals 11 and 12 can be made substantially the same, so that further poor connection does not occur. can do.

【0014】また、半導体チップ4を搭載する対象は、
液晶表示パネル1に限らず、例えばセラミック基板やガ
ラスエポキシ基板等からなる回路基板あるいはポリイミ
ド基板等からなるフレキシブル配線基板であってもよ
い。また、基板に搭載する対象は、半導体チップ4に限
らず、CSP(chip size package)やBGA(ball grida
rray)等の電子部品であってもよい。
The object on which the semiconductor chip 4 is mounted is
Not limited to the liquid crystal display panel 1, for example, a circuit board made of a ceramic substrate, a glass epoxy substrate, or the like, or a flexible wiring board made of a polyimide substrate or the like may be used. The object to be mounted on the substrate is not limited to the semiconductor chip 4, but may be a CSP (chip size package) or a BGA (ball grida).
rray) or the like.

【0015】[0015]

【発明の効果】以上説明したように、この発明によれ
ば、方形状の領域内に接続端子のほかにダミー接続端子
を設け、これら接続端子の総合的な面積関係をある所定
の関係としたので、例えば電子部品を基板上にその間に
異方導電性接着剤を介在させた状態で熱圧着する場合、
接続端子が設けられていない部分においてはダミー接続
端子によって絶縁性接着剤に圧力を十分に加えることが
でき、これに伴いダミー接続端子の近傍における接続端
子によっても絶縁性接着剤に圧力を十分に加えることが
でき、これにより接続不良が生じないようにすることが
できる。
As described above, according to the present invention, dummy connection terminals are provided in addition to the connection terminals in the rectangular area, and the total area relation of these connection terminals is set to a predetermined relation. So, for example, when thermocompression bonding electronic components on a substrate with an anisotropic conductive adhesive between them,
In portions where connection terminals are not provided, sufficient pressure can be applied to the insulating adhesive by the dummy connection terminals, and accordingly, sufficient pressure can be applied to the insulating adhesive also by the connection terminals near the dummy connection terminals. Can be added, so that a connection failure can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施形態を適用した液晶表示装置
の要部を示す断面図。
FIG. 1 is a sectional view showing a main part of a liquid crystal display device to which an embodiment of the present invention is applied.

【図2】同液晶表示装置における半導体チップの下面
図。
FIG. 2 is a bottom view of a semiconductor chip in the liquid crystal display device.

【図3】この発明の他の実施形態を適用した液晶表示装
置の要部を示す断面図。
FIG. 3 is a cross-sectional view showing a main part of a liquid crystal display device to which another embodiment of the present invention is applied.

【図4】従来の液晶表示装置の一部を示す断面図。FIG. 4 is a cross-sectional view showing a part of a conventional liquid crystal display device.

【図5】同液晶表示装置における半導体チップの下面
図。
FIG. 5 is a bottom view of a semiconductor chip in the liquid crystal display device.

【符号の説明】 2 下側の透明基板 3、6a、6b 接続端子 4 半導体チップ 7 異方導電性接着剤 11 ダミー接続端子[Description of Signs] 2 Lower transparent substrate 3, 6a, 6b Connection terminal 4 Semiconductor chip 7 Anisotropic conductive adhesive 11 Dummy connection terminal

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 方形状の領域内の所定の箇所に複数の接
続端子が設けられ、前記領域内の他の所定の箇所に複数
のダミー接続端子が設けられ、前記領域の左半分及び右
半分と上半分及び下半分とのうち少なくとも一方の両半
分において、前記接続端子及び前記ダミー接続端子のう
ち前記両半分にそれぞれ設けられたものの各合計面積比
は一方を1としたとき他方を1〜1.5としたことを特
徴とする電子部品。
1. A plurality of connection terminals are provided at predetermined positions in a rectangular region, and a plurality of dummy connection terminals are provided at other predetermined positions in the region, and a left half and a right half of the region are provided. In at least one of the upper half and the lower half, the total area ratio of the connection terminals and the dummy connection terminals provided in the two halves is one when one is one and the other is one to one. An electronic component, wherein the electronic component is set to 1.5.
【請求項2】 方形状の領域内の所定の箇所に複数の接
続端子が設けられ、前記領域内の他の所定の箇所に複数
のダミー接続端子が設けられ、前記領域の左半分及び右
半分と上半分及び下半分とのうち少なくとも一方の両半
分において、前記接続端子及び前記ダミー接続端子のう
ち前記両半分にそれぞれ設けられたものの各合計面積比
が一方を1としたとき他方を1〜1.5とされた電子部
品を、該電子部品の接続端子と対応する部分に接続端子
が設けられた基板上に搭載したことを特徴とする電子部
品搭載モジュール。
2. A plurality of connection terminals are provided at predetermined positions in a rectangular region, and a plurality of dummy connection terminals are provided at other predetermined positions in the region, and a left half and a right half of the region are provided. And in at least one of the upper half and the lower half, when the total area ratio of the connection terminals and the dummy connection terminals provided in the two halves is one when one is one and the other is one to one. An electronic component mounting module, wherein the electronic component set to 1.5 is mounted on a substrate provided with connection terminals at portions corresponding to the connection terminals of the electronic component.
【請求項3】 前記電子部品は前記基板上に異方導電性
接着剤を介して搭載されていることを特徴とする請求項
2記載の電子部品搭載モジュール。
3. The electronic component mounting module according to claim 2, wherein said electronic component is mounted on said substrate via an anisotropic conductive adhesive.
【請求項4】 前記基板における前記電子部品のダミー
接続端子と対応する部分にダミー接続端子が設けられて
いることを特徴とする請求項2または3記載の電子部品
搭載モジュール。
4. The electronic component mounting module according to claim 2, wherein a dummy connection terminal is provided at a portion of the substrate corresponding to the dummy connection terminal of the electronic component.
JP9131650A 1997-05-07 1997-05-07 Electronic component and electronic component mount module Pending JPH10308413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9131650A JPH10308413A (en) 1997-05-07 1997-05-07 Electronic component and electronic component mount module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9131650A JPH10308413A (en) 1997-05-07 1997-05-07 Electronic component and electronic component mount module

Publications (1)

Publication Number Publication Date
JPH10308413A true JPH10308413A (en) 1998-11-17

Family

ID=15063026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9131650A Pending JPH10308413A (en) 1997-05-07 1997-05-07 Electronic component and electronic component mount module

Country Status (1)

Country Link
JP (1) JPH10308413A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474627B1 (en) * 2000-07-05 2005-03-08 샤프 가부시키가이샤 Flexible printed circuit board, integrated circuit chip mounting flexible printed circuit board, display apparatus incorporating, integrated circuit chip mounted structure, and bonding method of integrated circuit chip mounting flexible printed circuit board
JP2006332465A (en) * 2005-05-27 2006-12-07 Optrex Corp Chip-on film semiconductor device
JP2007123709A (en) * 2005-10-31 2007-05-17 Nec Electronics Corp Semiconductor device
KR100771033B1 (en) 2002-03-25 2007-10-29 소니 케미카루 앤드 인포메이션 디바이스 가부시키가이샤 Method for manufacturing connection structure
JP2008078238A (en) * 2006-09-19 2008-04-03 Nec Corp Structure and method for mounting electronic component
WO2012117960A1 (en) * 2011-03-02 2012-09-07 シャープ株式会社 Semiconductor element and display panel
JP5560713B2 (en) * 2007-10-05 2014-07-30 日本電気株式会社 Electronic component mounting method, etc.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474627B1 (en) * 2000-07-05 2005-03-08 샤프 가부시키가이샤 Flexible printed circuit board, integrated circuit chip mounting flexible printed circuit board, display apparatus incorporating, integrated circuit chip mounted structure, and bonding method of integrated circuit chip mounting flexible printed circuit board
KR100771033B1 (en) 2002-03-25 2007-10-29 소니 케미카루 앤드 인포메이션 디바이스 가부시키가이샤 Method for manufacturing connection structure
JP2006332465A (en) * 2005-05-27 2006-12-07 Optrex Corp Chip-on film semiconductor device
JP4699089B2 (en) * 2005-05-27 2011-06-08 オプトレックス株式会社 Chip-on-film semiconductor device
JP2007123709A (en) * 2005-10-31 2007-05-17 Nec Electronics Corp Semiconductor device
JP2008078238A (en) * 2006-09-19 2008-04-03 Nec Corp Structure and method for mounting electronic component
JP5560713B2 (en) * 2007-10-05 2014-07-30 日本電気株式会社 Electronic component mounting method, etc.
WO2012117960A1 (en) * 2011-03-02 2012-09-07 シャープ株式会社 Semiconductor element and display panel

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