JPH0645402A - Wiring board and method of connection thereof - Google Patents
Wiring board and method of connection thereofInfo
- Publication number
- JPH0645402A JPH0645402A JP4195617A JP19561792A JPH0645402A JP H0645402 A JPH0645402 A JP H0645402A JP 4195617 A JP4195617 A JP 4195617A JP 19561792 A JP19561792 A JP 19561792A JP H0645402 A JPH0645402 A JP H0645402A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- chip
- wiring board
- corners
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は配線基板上にＩＣ（半導
体集積回路）チップをバンプを介して直接接続するフリ
ップチップ実装に使用して好適な配線基板の接続方法及
び配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board connecting method and a wiring board suitable for flip-chip mounting in which an IC (semiconductor integrated circuit) chip is directly connected to a wiring board via bumps.
【０００２】[0002]
【従来の技術】従来、配線基板にＩＣチップを接続する
方法としては、ＩＣチップを樹脂パッケージ内に封止し
て構成したＩＣの端子をプリント配線基板に接続すると
いう方法が一般的であった。しかし、プリント配線基板
の配線パターンがファインピッチ化してくると、この方
法では、実装密度が上がらないという問題がある。そこ
で、現在では、直接、このＩＣチップをプリント配線基
板に接続することにより実装密度を向上させるようにし
ている。2. Description of the Related Art Conventionally, as a method of connecting an IC chip to a wiring board, a method of connecting terminals of an IC formed by sealing the IC chip in a resin package to a printed wiring board has been generally used. . However, when the wiring pattern of the printed wiring board has a fine pitch, this method has a problem that the mounting density cannot be increased. Therefore, at present, the mounting density is improved by directly connecting the IC chip to the printed wiring board.
【０００３】このＩＣチップを直接に配線基板に接続す
る方法としては、金線を使用したワイヤボンディング法
や配線基板あるいはＩＣチップに、はんだ、インジウム
等のバンプを設け、このバンプを介して配線基板にＩＣ
チップを直接接続するフリップチップ実装法がある。前
者のワイヤボンディング法は、後者のフリップチップ実
装法に比べて作業性及び実装密度が劣ることから、今日
ではこのフリップチップ実装法が実装密度を上げる技術
として注目されている。As a method of directly connecting the IC chip to the wiring board, a wire bonding method using a gold wire or a bump of solder, indium or the like is provided on the wiring board or the IC chip, and the wiring board is provided through the bump. IC
There is a flip chip mounting method in which chips are directly connected. The former wire bonding method is inferior in workability and mounting density to the latter flip chip mounting method, and therefore, this flip chip mounting method is now drawing attention as a technique for increasing the mounting density.
【０００４】[0004]
【発明が解決しようとする課題】ところでこのフリップ
チップ実装法により、図６に示す如くＩＣチップ１を配
線基板２にバンプを介して直接接続するときに、図７に
示す如くＩＣチップ１側及び配線基板２側に夫々所定数
の高さの等しいバンプ３及び４を形成し、このＩＣチッ
プ１のバンプ３と配線基板２のバンプ４とを重ね合わせ
る如くしてフリップチップ実装を行う如くしていた。By the way, when the IC chip 1 is directly connected to the wiring substrate 2 via the bumps as shown in FIG. 6 by the flip chip mounting method, as shown in FIG. A predetermined number of bumps 3 and 4 having the same height are formed on the wiring board 2 side, and the bumps 3 of the IC chip 1 and the bumps 4 of the wiring board 2 are overlapped with each other to perform flip chip mounting. It was
【０００５】然しながら、このＩＣチップ１側及び配線
基板２側の夫々のバンプ３及び４の夫々の先端部分の形
状は例えばはんだの表面張力により球状になっている。However, the tip portions of the bumps 3 and 4 on the IC chip 1 side and the wiring substrate 2 side are spherical due to the surface tension of the solder, for example.
【０００６】このためＩＣチップ１を配線基板２にフリ
ップチップ実装するときに斜め方向の力が加わってしま
うと図８に示す如くバンプ３及び４同志がずれてしまい
正しい接続ができないことがおこる不都合があった。For this reason, when the IC chip 1 is flip-chip mounted on the wiring board 2, if an oblique force is applied, the bumps 3 and 4 are displaced from each other as shown in FIG. was there.
【０００７】本発明は斯る点に鑑み、常に正しい接続が
できるようにすることを目的とする。In view of the above point, the present invention has an object to always make a correct connection.
【０００８】[0008]
【課題を解決するための手段】本発明配線基板の接続方
法は、例えば図１に示す如く配線基板２上にＩＣチップ
１をバンプを介して接続する配線基板の接続方法におい
て、このＩＣチップ１の４隅のバンプ５のうち少なくと
も３隅のバンプは他のバンプ３の高さよりも高く形成
し、その後このバンプ３，５を介して接続するようにし
たものである。The wiring board connecting method of the present invention is a wiring board connecting method for connecting an IC chip 1 on a wiring board 2 via bumps as shown in FIG. 1, for example. Among the bumps 5 at the four corners, at least the bumps at the three corners are formed to be higher than the height of the other bumps 3, and then the bumps 3 and 5 are connected to each other.
【０００９】また本発明配線基板の接続方法は上述にお
いて、高さを高くしたバンプ５は他の高さの低いバンプ
３よりも低融点金属であるものである。The wiring board connecting method of the present invention is such that, in the above description, the bumps 5 having a high height are made of a metal having a lower melting point than the other bumps 3 having a low height.
【００１０】また本発明配線基板は、例えば図２に示す
如く配線基板２上にＩＣチップ１をバンプを介して接続
されてなる配線基板において、このＩＣチップ１の４隅
のバンプ５に対応する電極６のうち少なくとも３隅のバ
ンプに対応する電極の面積Ｓ 0 を他の電極７の面積Ｓ1
よりも大きく形成したものである。The wiring board of the present invention is shown in FIG. 2, for example.
Connect the IC chip 1 on the wiring board 2 via bumps
The four corners of this IC chip 1
Of the electrodes 6 corresponding to the bumps 5 of the
Area S of the electrode corresponding to the pump 0The area S of the other electrode 71
It is formed larger than.
【００１１】[0011]
【作用】本発明によればＩＣチップ１の４隅のバンプ５
のうち少なくとも３隅のバンプ５の高さを他のバンプ３
の高さより高くして、このバンプ５により位置決めして
フリップチップを実装するので、常に良好な接続ができ
る。According to the present invention, the bumps 5 at the four corners of the IC chip 1 are
Of the bumps 5 at least at the three corners of the other bumps 3
Since the flip chip is mounted by positioning the bump 5 at a height higher than that of the bump 5, the connection can always be made well.
【００１２】[0012]
【実施例】以下図面を参照して、本発明配線基板の接続
方法及び配線基板の実施例につき説明しよう。図１は本
例によるＩＣチップ１の端子面を示し、本例において
は、この端子部にバンプを形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a wiring board connecting method and a wiring board according to the present invention will be described below with reference to the drawings. FIG. 1 shows a terminal surface of an IC chip 1 according to this example. In this example, bumps are formed on this terminal portion.
【００１３】この場合、本例においてはこのＩＣチップ
１の４隅の夫々のバンプ５を他のバンプ３より高くする
如くする。この４隅のバンプ５の高さを例えば５０〜５
５μｍとし、その他のバンプ３の高さを例えば３５μｍ
とする。In this case, in this example, the bumps 5 at the four corners of the IC chip 1 are made higher than the other bumps 3. The height of the bumps 5 at the four corners is, for example, 50 to 5
The height of the other bumps 3 is, for example, 35 μm.
And
【００１４】また本例においては、このバンプ３及び５
を夫々はんだより構成すると共にこの４隅の高さの高い
バンプ５をバンプ３より低融点のはんだで構成する。In this example, the bumps 3 and 5 are also used.
And the bumps 5 with high heights at the four corners are made of solder having a melting point lower than that of the bumps 3.
【００１５】この４隅の高さの高いバンプ５のはんだの
組成を例えばＳｎ６３％、Ｐｂ３７％とし、共晶はんだ
とする。この場合の融点は１９０℃である。The solder composition of the bumps 5 having high four corners is, for example, Sn63% and Pb37% to form a eutectic solder. The melting point in this case is 190 ° C.
【００１６】また４隅以外のバンプ３のはんだの組成を
例えばＳｎ９０％、Ｐｂ１０％とする。この場合の融点
は２２０℃であり高融点はんだである。The solder composition of the bumps 3 other than the four corners is, for example, Sn90% and Pb10%. In this case, the melting point is 220 ° C., which is a high melting point solder.
【００１７】また図２は本例による配線基板２を示し、
この配線基板２のＩＣチップ１の取付位置のＩＣチップ
１のバンプ３及び５に対応する位置に電極６及び７を形
成する。この電極６，７は所定の配線パターンに接続さ
れたものである。FIG. 2 shows a wiring board 2 according to this example,
Electrodes 6 and 7 are formed at positions corresponding to the bumps 3 and 5 of the IC chip 1 at the mounting position of the IC chip 1 on the wiring board 2. The electrodes 6 and 7 are connected to a predetermined wiring pattern.
【００１８】本例においては、このＩＣチップ１の４隅
のバンプ５に対応する電極６の面積Ｓ0 を他の電極７の
面積Ｓ1 より大きく、例えば電極６を縦横が夫々１００
μｍの正方形とし、電極７を縦横が夫々７０μｍの正方
形とする。In this example, the areas S 0 of the electrodes 6 corresponding to the bumps 5 at the four corners of the IC chip 1 are larger than the areas S 1 of the other electrodes 7. For example, the electrodes 6 are 100 vertically and horizontally respectively.
The electrode 7 is a square having a length of 70 μm and a length of 70 μm.
【００１９】この配線基板２の電極７上に高さが例えば
１５μｍ程度のバンプ４を設ける如くする。この場合電
極７より面積の大きい電極６にはバンプを設けない如く
する。The bumps 4 having a height of, for example, about 15 μm are provided on the electrodes 7 of the wiring board 2. In this case, no bump is provided on the electrode 6 having a larger area than the electrode 7.
【００２０】この配線基板２のバンプ４のはんだとして
はＩＣチップ１のバンプ３に使用したはんだの融点例え
ば２２０℃よりも低い融点になる組成のはんだ例えば共
晶はんだを使用する。As the solder for the bumps 4 of the wiring board 2, a solder having a composition lower than the melting point of the solder used for the bumps 3 of the IC chip 1, for example, 220 ° C., for example, a eutectic solder is used.
【００２１】本例においてはフリップチップ実装すると
きは、まず図３に示す如く、バンプ３，５が付されたＩ
Ｃチップ１をバンプ４が付された配線基板２にフリップ
チップボンダ等により位置合わせを行いマウントする。
このときはＩＣチップ１の４隅に高さの高いバンプ５が
あるため、横方向にずれることがない。In this embodiment, when flip-chip mounting is performed, first, as shown in FIG.
The C chip 1 is aligned and mounted on the wiring board 2 having the bumps 4 by a flip chip bonder or the like.
At this time, since the bumps 5 with high height are located at the four corners of the IC chip 1, there is no lateral shift.
【００２２】その後、加熱、加圧してはんだによる接合
を行うが、まず低融点はんだであるＩＣチップ１の４隅
のバンプ５が、図４に示す如く溶融する。この場合、こ
のＩＣチップ１の４隅のはんだの表面張力により、ＩＣ
チップ１の位置が多少ずれたとしても正しい場所に戻る
効果（セルフアライメント）があるため一層位置の正確
さを確保することができる。After that, soldering is carried out by heating and pressurizing. First, the bumps 5 at the four corners of the IC chip 1 which is a low melting point solder are melted as shown in FIG. In this case, due to the surface tension of the solder at the four corners of this IC chip 1, the IC
Even if the position of the chip 1 is slightly deviated, there is an effect of returning to the correct position (self-alignment), so that the accuracy of the position can be further secured.
【００２３】更に温度を上げていくとバンプ３及び４の
はんだも溶融し、図５に示す如く全ての接続が完了す
る。When the temperature is further raised, the solders of the bumps 3 and 4 are also melted, and all the connections are completed as shown in FIG.
【００２４】本例は上述の如くであるのでＩＣチップ１
を配線基板２にマウントするときに、ＩＣチップ１の４
隅のバンプ５と接続される配線基板２の電極６の表面に
はバンプがないため平坦なので、ＩＣチップ１が配線基
板２に対して横にずれることがない利益がある。Since this example is as described above, the IC chip 1
4 of the IC chip 1 when mounting the
Since there is no bump on the surface of the electrode 6 of the wiring substrate 2 connected to the bumps 5 at the corners, the surface is flat, so that there is an advantage that the IC chip 1 is not laterally displaced with respect to the wiring substrate 2.
【００２５】また本例においては、応力が最も大きくか
かるＩＣチップ１の４隅を、高さの高い大きなバンプ５
で接続しているので、この応力に対する信頼性が向上す
る。Further, in this example, the four corners of the IC chip 1 to which the greatest stress is applied are provided with the large bumps 5 having a high height.
Since the connection is made with, the reliability against this stress is improved.
【００２６】また本例によればＩＣチップ１の４隅の高
さの高い大きなバンプ５の大きな表面張力によってセル
フアライメントが行われ位置の正確さを確保することが
できる。Further, according to this example, the self-alignment is performed by the large surface tension of the large bumps 5 having high heights at the four corners of the IC chip 1, and the position accuracy can be secured.
【００２７】また本例によればＩＣチップ１の４隅の大
きなバンプ５を通じた放熱により、このＩＣチップ１の
放熱性が向上すると共にこの大きなバンプ５による接続
により小さなバンプ３，４による接続が重さでつぶれて
しまうことがなく、ＩＣチップ１の寿命が長くなる利益
がある。Further, according to this embodiment, the heat dissipation through the large bumps 5 at the four corners of the IC chip 1 improves the heat dissipation of the IC chip 1, and the connection by the large bumps 5 enables the connection by the small bumps 3, 4. There is an advantage that the IC chip 1 has a long life without being crushed by the weight.
【００２８】尚、上述実施例においてはＩＣチップ１の
４隅のバンプ５を高さの高いバンプとしたが、この４隅
のバンプのうちの３隅のバンプを高さの高いバンプで構
成するようにしても、上述実施例と同様の作用効果が得
られることは勿論である。また配線基板２に設ける面積
の大きな電極６もこのＩＣチップ１の高さの高いバンプ
に対応して設ければ良いことは勿論である。Although the bumps 5 at the four corners of the IC chip 1 are high-height bumps in the above-described embodiment, the bumps at the three corners among the bumps at the four corners are high-height bumps. Even if it does so, it is needless to say that the same effect as the above-mentioned embodiment can be obtained. Further, it goes without saying that the electrodes 6 having a large area provided on the wiring substrate 2 may be provided corresponding to the high bumps of the IC chip 1.
【００２９】また本発明は上述実施例に限ることなく本
発明の要旨を逸脱することなく、その他種々の構成が採
り得ることは勿論である。Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.
【００３０】[0030]
【発明の効果】本発明によれば、ＩＣチップ１の４隅の
バンプのうち少なくとも３隅のバンプの高さを他のバン
プの高さより高くして、この高さの高いバンプにて位置
決めをするようにして、フリップチップ実装をするよう
にしているので、常に良好な接続ができる利益がある。According to the present invention, among the bumps at the four corners of the IC chip 1, at least the bumps at the three corners are made higher in height than the other bumps, and the bumps having the high height are used for positioning. By doing so, flip-chip mounting is performed, so that there is an advantage that a good connection can always be achieved.
【図１】本発明によるＩＣチップの例を示す底面斜視図
である。FIG. 1 is a bottom perspective view showing an example of an IC chip according to the present invention.
【図２】本発明による配線基板の例を示す斜視図であ
る。FIG. 2 is a perspective view showing an example of a wiring board according to the present invention.
【図３】本発明の説明に供する線図である。FIG. 3 is a diagram for explaining the present invention.
【図４】本発明の説明に供する線図である。FIG. 4 is a diagram for explaining the present invention.
【図５】本発明の説明に供する線図である。FIG. 5 is a diagram for explaining the present invention.
【図６】フリップチップ実装の例を示す斜視図である。FIG. 6 is a perspective view showing an example of flip-chip mounting.
【図７】従来の説明に供する線図である。FIG. 7 is a diagram used for conventional description.
【図８】従来の説明に供する線図である。FIG. 8 is a diagram used for conventional description.
１ ＩＣチップ ２ 配線基板 ３，４，５ バンプ ６，７ 電極 1 IC chip 2 Wiring board 3, 4, 5 Bump 6, 7 Electrode
Claims (3)
て接続する配線基板の接続方法において、該ＩＣチップ
の４隅のバンプのうち少なくとも３隅のバンプは他のバ
ンプの高さよりも高く形成し、その後バンプを介して接
続するようにしたことを特徴とする配線基板の接続方
法。1. A wiring board connecting method for connecting an IC chip on a wiring board via bumps, wherein bumps at at least three corners of bumps at four corners of the IC chip are formed to be higher than other bumps. Then, the connection method of the wiring board is characterized in that after that, the connection is made via the bump.
いて、高さを高くしたバンプは他の高さの低いバンプよ
りも低融点金属であることを特徴とする配線基板の接続
方法。2. The method for connecting wiring boards according to claim 1, wherein the bumps having a height higher than that of the other bumps having a lower height are made of a metal having a lower melting point.
て接続されてなる配線基板において、該ＩＣチップの４
隅のバンプに対応する電極のうち少なくとも３隅のバン
プに対応する電極の面積を他の電極の面積よりも大きく
形成したことを特徴とする配線基板。3. A wiring board having an IC chip connected to the wiring board via bumps, wherein
A wiring board, characterized in that, among electrodes corresponding to the bumps at the corners, at least three electrodes corresponding to the bumps at the corners have a larger area than the other electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4195617A JPH0645402A (en) | 1992-07-22 | 1992-07-22 | Wiring board and method of connection thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4195617A JPH0645402A (en) | 1992-07-22 | 1992-07-22 | Wiring board and method of connection thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0645402A true JPH0645402A (en) | 1994-02-18 |
Family
ID=16344151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4195617A Pending JPH0645402A (en) | 1992-07-22 | 1992-07-22 | Wiring board and method of connection thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0645402A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11160584A (en) * | 1997-12-01 | 1999-06-18 | Kyocera Corp | Optical package and optical module using the same |
| US6134428A (en) * | 1995-11-06 | 2000-10-17 | Seiko Epson Corporation | Wrist mounted communicator |
| JP2007027576A (en) * | 2005-07-20 | 2007-02-01 | Rohm Co Ltd | Semiconductor device |
| JP2007234841A (en) * | 2006-02-28 | 2007-09-13 | Kyocera Corp | Wiring board, mounting component, electronic apparatus, manufacturing method of wiring board, and manufacturing method of electronic apparatus |
| JP2007258637A (en) * | 2006-03-27 | 2007-10-04 | Matsushita Electric Ind Co Ltd | Electronic component mounting system, electronic component mounting device, and method for mounting electronic component |
| JP2011086879A (en) * | 2009-10-19 | 2011-04-28 | Powertech Technology Inc | Flip chip structure of semiconductor |
-
1992
- 1992-07-22 JP JP4195617A patent/JPH0645402A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6134428A (en) * | 1995-11-06 | 2000-10-17 | Seiko Epson Corporation | Wrist mounted communicator |
| JPH11160584A (en) * | 1997-12-01 | 1999-06-18 | Kyocera Corp | Optical package and optical module using the same |
| JP2007027576A (en) * | 2005-07-20 | 2007-02-01 | Rohm Co Ltd | Semiconductor device |
| JP2007234841A (en) * | 2006-02-28 | 2007-09-13 | Kyocera Corp | Wiring board, mounting component, electronic apparatus, manufacturing method of wiring board, and manufacturing method of electronic apparatus |
| JP2007258637A (en) * | 2006-03-27 | 2007-10-04 | Matsushita Electric Ind Co Ltd | Electronic component mounting system, electronic component mounting device, and method for mounting electronic component |
| JP4595857B2 (en) * | 2006-03-27 | 2010-12-08 | パナソニック株式会社 | Electronic component mounting system and electronic component mounting method |
| JP2011086879A (en) * | 2009-10-19 | 2011-04-28 | Powertech Technology Inc | Flip chip structure of semiconductor |
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