JPH0397238A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form electrode pads not only on the periphery but also inside a semiconductor substrate and realize a high degree of integration, by mounting a plurality of electrode pads formed on the periphery and inside of the semiconductor substrate via bump electrodes by using a high density film carrier having inner leads formed as a plurality of upper and lower layers. CONSTITUTION:On the periphery and the inside of a semiconductor substrate 1, electrode pads 3a on the periphery and electrode pads 3b on the inside are arranged via an insulating film 2; Au bump electrodes 5 having the same bump height are formed on the electrode pads 3a, 3b via barrier metal (Ti/Pd film); the Au bump electrode 5 is constituted of an upper layer and a lower layer. The bump electrodes are connected with a film carrier having inner leads 6a, 6b whose connection surfaces with the Au bump electrodes are formed to have the same height. In this case, the electrode pads 3a on the periphery are connected with the lower layer inner leads 6a via the Au bump electrodes 5; the electrode pads 3b on the inside are connected with the lower inner leads 6b via the Au bump electrodes 5. Hence many electrode pads can be formed on not only the periphery but also the inside of the semiconductor substrate, and the freedom of layout is increased, thereby realizing the high degree of integration.

Description

[Detailed Description of the Invention] [Summary] A highly integrated semiconductor integrated circuit formed with a plurality of electrode pads on the periphery and inside of a semiconductor substrate has inner leads formed in multiple upper and lower layers. Because the structure is mounted using a film carrier with bump electrodes interposed, electrode pads can be formed not only on the periphery but also inside the device, allowing for high integration and a small surface area to increase the number of pins. The ability to accommodate the ground and power supply electrode pads allows for higher performance and reliability, and the smaller mounting area allows for lower costs and faster speeds. Semiconductor equipment.

[Industrial Field of Application] The present invention relates to semiconductor integrated circuits, and particularly relates to semiconductor devices that use bumps and can be mounted using high-density film carriers in highly integrated semiconductor integrated circuits that require a large number of bins. Semiconductor integrated circuits that require high functionality, such as arrays, require a large number of input and output circuit sections. However, when the number of pins exceeds 300, the chip size becomes huge due to the large number of electrode pads placed around the periphery, which reduces the yield. The problem of extremely low energy consumption is becoming more and more obvious. Therefore, we arranged a large number of electrode pads in a highly integrated manner around the periphery and inside.
There is a need for a means that can implement mounting using a film carrier using bumps.

[Prior Art] FIG. 3 is a schematic diagram of a conventional semiconductor device, in which (a) is a side sectional view and (b) is a plan view (the slatted film carrier is not shown). is a semiconductor substrate, 52 is an insulating film, 53 is an electrode pad (AI), 54 is a cover retention film (PSG film + plasma nitride film + polyimide film),
55 is an Au bump electrode (including barrier metal Ti/Pd film), 56 is an inner lead (CI/old/Au), 57 is a film (polyimide), 58 is a peripheral circuit section, and 59 is an internal circuit section.

In the figure, an insulating film 5 is formed on the periphery of the semiconductor substrate 51.
A large number of electrode pads 53 are disposed through the electrode pads 2, and an Au bump electrode 55 is formed on the electrode pad 53 through a barrier metal (Ti/Pd[).
5 is an inner lead 56 of a film carrier with a normal structure.
formed into a structure connected to the therefore,
Since a large number of electrode pads can only be placed on the periphery of the semiconductor substrate, the degree of integration decreases due to restrictions such as electrode pad pitch, and the chip size increases to accommodate the required number of electrode pads. There is a problem in that the yield is extremely low. In addition, due to the need to keep the chip size as small as possible, it is not possible to provide enough electrode pads for ground and power supply, resulting in deterioration of noise characteristics and
Deterioration of lifespan due to wiring migration is also a problem.

[Problems to be Solved by the Invention] The problems to be solved by the present invention are that, as shown in the conventional example, a large number of electrode pads can only be arranged in the peripheral area of a semiconductor substrate, As the integration density decreases and the chip size becomes huge, the yield is extremely low. Also, due to the need to keep the chip size small, there is noise due to the fact that the electrode pads for ground and power supply cannot be accommodated sufficiently. The problem was that the characteristics and the deterioration of the A1 wiring life could not be improved.

[Means for Solving the Problems] The above problem is caused by the fact that the plurality of electrode pads disposed on the periphery and inside of the semiconductor substrate are formed using film carriers and bumps with inner leads arranged in multiple upper and lower layers. This problem is solved by the semiconductor device of the present invention, which is connected through electrodes.

[Function] That is, in the semiconductor device of the present invention, a highly integrated semiconductor integrated circuit formed with a plurality of electrode pads on the periphery and inside of a semiconductor substrate has inner leads formed in multiple upper and lower layers. It is formed in a structure in which bump electrodes are mounted using a high-density film carrier with intervening bump electrodes. Therefore, a large number of electrode pads can be formed not only on the periphery but also inside the semiconductor substrate, increasing the degree of freedom in layout, and reducing the chip size by increasing the degree of integration. This innovation makes it possible to increase the number of pins in a small area, making it possible to increase functionality and increase added value. In addition, sufficient electrode pads for ground and power supply can be provided, which reduces noise characteristics and reduces A1.
It is possible to improve the deterioration of lifespan due to wiring migration. Furthermore, by being able to implement it using a smaller film carrier, it is possible to reduce costs and increase speed. It is possible to obtain a semiconductor device that enables the formation of.

[Example] The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 (aHb) is a schematic diagram of a first embodiment of the semiconductor device of the present invention, and FIG. 2 is a schematic side sectional view of the second embodiment of the semiconductor device of the present invention.

Objects that are the same throughout the country are designated by the same code.

FIG. 1 is a schematic diagram showing a first embodiment of a semiconductor device of the present invention, in which (a) shows a side sectional view, and (b) shows a plan view (however, the film carrier is not shown). 91 is a semiconductor substrate, 2 is an insulating film, 3a is a peripheral electrode pad (AI), 3b is an internal electrode pad (AI)
, 4 is a cover protective film (PSG film + plasma nitride film + polyimide film), 5 is an Au bump electrode (barrier metal Ti
/Pd film), 6a is the lower layer inner lead (Cu/N
i/Au), 6b is the upper layer inner lead (Cu/Ni
/Au), 7 is a film (polyimide), 8 is a peripheral circuit section, and 9 is an internal circuit section.

In the figure, peripheral electrode pads 3a and internal electrode pads 3b are disposed on the periphery and inside of a semiconductor substrate l with an insulating film 2 interposed therebetween, and the electrode pads (3a, 3b)
An Au bump electrode 5 having the same bump height is formed on the top via a barrier metal (Ti/Pd film), and the Au bump electrode 5 is composed of upper and lower layers, and the connection surface with the Au bump electrode 5 is the same. The inner lead (6
9 connected to a film carrier with a, 6b)
At this time, the peripheral electrode pad 3a is connected to the lower layer inner lead 6a via the Au bump electrode 5, and the internal electrode pad 3b is connected to the upper layer inner lead 6b via the Au bump electrode 5. It is formalized. Therefore, a large number of electrode pads can be arranged on the semiconductor substrate not only on the periphery but also on the inside, increasing the degree of freedom in layout, allowing for high integration, reducing the chip size, and improving yield. In addition, by improving the layout, it is possible to increase the number of pins in a small area, making it possible to increase functionality, thereby increasing added value. Furthermore, since sufficient electrode pads for ground and power supply can be provided, it is possible to improve the deterioration of noise characteristics and the deterioration of life due to migration of the A1 wiring. Moreover, since it can be implemented using a smaller film carrier, it is also possible to reduce costs and increase speed.

FIG. 2 is a schematic side sectional view showing a second embodiment of the semiconductor device of the present invention, in which 1 to 4 and 68 to 7 are the same as in FIG. 1, and 5a is an Au bump electrode with a low bump height. (Peripheral electrode pad portion), 5b indicates an Au bump electrode (internal electrode pad portion) with a high bump height.

In the figure, it is mounted by a film carrier having two layers of inner leads (6a, 6b) with different connection surfaces to the Au bump electrodes, and the electrode pads 3 at the periphery.
a is connected to the lower layer inner lead 6a via the Au bump electrode 5a with a low bump height, and the internal electrode pad 3b is connected to the upper layer inner lead 6b via the Au bump electrode 5b with a high bump height. The structure is the same as in Figure 1 except for the points marked with . In this embodiment as well, the same effects as in the first embodiment can be obtained.

Note that the bump electrodes formed in the above embodiments may be formed on the electrode pads during the wafer process of semiconductor integrated circuits, or may be formed in advance on the inner leads of the film carrier (transfer bumps). The present invention is also effective in these cases.

In addition, in the above embodiment, only the mounting using a film carrier having two layers of upper and lower inner leads is described, but in the case of mounting using a film carrier having three or more layers of inner leads with polyimide etc. sandwiched between them, The present invention is also effective against such cases.

As shown in the embodiments above, according to the semiconductor device of the present invention, a large number of electrode pads can be formed not only on the periphery but also inside the semiconductor substrate, increasing the degree of freedom in layout.
By achieving high integration, the chip size can be reduced and yields can be improved. In addition, by improving the layout, it is possible to increase the number of pins in a small area, making it possible to increase functionality, thereby increasing added value. Furthermore, since sufficient electrode pads for ground and power supply can be provided, it is possible to improve the deterioration of noise characteristics and the deterioration of life due to migration of the A1 wiring. Furthermore, the ability to implement with smaller film carriers also allows for low cost 1-hi and high-speed f-hi.

[Effects of the Invention] As described above, according to the present invention, in a highly integrated semiconductor integrated circuit that requires a large number of bins, a plurality of electrode pads formed on the periphery and inside of a semiconductor substrate can be formed in multiple upper and lower layers. The structure is mounted using a high-density film carrier with inner leads, with bump electrodes interposed between them, allowing for high integration by allowing electrode pads to be formed not only on the periphery but also inside. High functionality is achieved by enabling multiple pins in a small area, high performance and high reliability are achieved by being able to accommodate enough ground and power supply electrode pads, and low performance is achieved by reducing the mounting area. It is possible to reduce costs and increase speed. In other words, extremely high integration, high functionality, high performance,
A semiconductor device that enables formation of highly reliable, high-speed, and low-cost semiconductor integrated circuits can be obtained.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) and 1(b) show the first
FIG. 2 is a schematic side sectional view of a second embodiment of the semiconductor device of the present invention, and FIG. 3 (aHb) is a schematic diagram of a conventional semiconductor device. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3a is a peripheral electrode pad (A1), 3b is an internal electrode pad (AI), 4 is a cover protective film (PSG film + plasma nitride film + polyimide film) , 5 is an Au bump electrode (including barrier metal Ti/Pd film), 5a is an All bump electrode with a low bump height (peripheral electrode pad part), and 5b is an Au bump electrode with a high bump height (internal electrode). pad part), 6a is the lower layer inner lead (Cu/Ni/Au), 6b
9 indicates the upper layer inner lead (Cu/Ni/Au), 7 indicates the film (polyimide), 8 indicates the peripheral circuit section, and 9 indicates the internal circuit section.

Claims (4)

[Claims] (1) A plurality of electrode pads arranged on the periphery and inside the semiconductor substrate are connected via bump electrodes to a film carrier having inner leads formed in upper and lower layers in multiple layers. semiconductor devices. (2) The lower layer inner lead is connected to a peripheral electrode pad on the semiconductor substrate, and the upper layer inner lead is connected to an internal electrode pad on the semiconductor substrate. 1. Semiconductor device described in Section 1. (3) A plurality of inner leads having bump electrode connection surfaces deformed to the same height are connected to bump electrodes having the same bump height. Semiconductor equipment. (4) The semiconductor device according to claim 1, wherein the lower layer inner lead is connected to a bump electrode with a low bump height, and the upper layer inner lead is connected to a bump electrode with a high bump height. .