JP3515473B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3515473B2 JP3515473B2 JP2000075023A JP2000075023A JP3515473B2 JP 3515473 B2 JP3515473 B2 JP 3515473B2 JP 2000075023 A JP2000075023 A JP 2000075023A JP 2000075023 A JP2000075023 A JP 2000075023A JP 3515473 B2 JP3515473 B2 JP 3515473B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- base
- electrode
- pad portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置、特に高
い電流増幅率βを有する電極構造のトランジスタに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a transistor having an electrode structure having a high current amplification factor β.
【０００２】[0002]
【従来の技術】トランジスタ等の小型チップ部品は携帯
端末の普及に伴い、出きる限り小さい形状が要望され、
チップ抵抗器やチップコンデンサ並の大きさが要求され
ている。しかし特性的には小さいチップサイズにもかか
わらず、従来以上の特性を実現しなくてはならないので
ある。特に、低飽和電圧（VCE(sat)）および大きい電流
容量はユーザーから強く改善を望まれる特性である。こ
の特性を実現するために、エミッタ周辺長の増加を図る
メッシュエミッタ構造のトランジスタが提案されてい
る。2. Description of the Related Art With the widespread use of mobile terminals, small chip parts such as transistors are required to be as small as possible.
The size of chip resistors and chip capacitors is required. However, in terms of characteristics, even though the chip size is small, it is necessary to realize characteristics that are higher than conventional ones. In particular, low saturation voltage (VCE (sat)) and large current capacity are characteristics strongly desired by users for improvement. In order to realize this characteristic, a mesh-emitter structure transistor has been proposed in which the peripheral length of the emitter is increased.
【０００３】図５は多層配線を用いたメッシュエミッタ
構造のトランジスタの平面図を示しており、図６はその
Ｙ−Ｙ線断面図を示している。FIG. 5 shows a plan view of a transistor having a mesh emitter structure using multilayer wiring, and FIG. 6 shows a sectional view taken along the line YY.
【０００４】かかるトランジスタはシリコン半導体基板
よりなるコレクタ領域１と、ベース領域２と、メッシュ
状のエミッタ領域３とを有し、エミッタ領域３はベース
領域２の全面に配置され、ベース領域２のコンタクト領
域４は多数の島状にエミッタ領域３に完全に囲まれて配
置されている。ベース領域２のコンタクト領域４には第
１のベース電極５がそれぞれにコンタクトされ、エミッ
タ領域３には第１のエミッタ電極６が設けられ、さらに
その表面を被覆する層間絶縁膜７上に第１のベース電極
５とコンタクトした第２のベース電極８と第１のエミッ
タ電極６にコンタクトする第２のエミッタ電極９が設け
られている。一点破線で囲む第２のベース電極８および
第２のエミッタ電極９の中央には点線で示すボンディン
グワイヤー１０が圧着されている。Such a transistor has a collector region 1 made of a silicon semiconductor substrate, a base region 2, and a mesh-shaped emitter region 3. The emitter region 3 is arranged on the entire surface of the base region 2 and contacts the base region 2. The region 4 is arranged in a large number of islands so as to be completely surrounded by the emitter region 3. A first base electrode 5 is in contact with each contact region 4 of the base region 2, a first emitter electrode 6 is provided in the emitter region 3, and a first emitter electrode 6 is formed on the interlayer insulating film 7 covering the surface thereof. A second base electrode 8 which is in contact with the base electrode 5 and a second emitter electrode 9 which is in contact with the first emitter electrode 6. A bonding wire 10 shown by a dotted line is pressure-bonded to the centers of the second base electrode 8 and the second emitter electrode 9 surrounded by a dashed line.
【０００５】従って、ベース領域２のコンタクト領域４
の面積を減らし、エミッタ領域３をメッシュ状にしてエ
ミッタ領域３の周辺長を増加できる。またメッシュ状の
エミッタ領域３には第１のエミッタ電極６がコンタクト
されるので、最小のチップサイズでも効率よく電流容量
を増大できるメリットがある。更に多層構造によりチッ
プ全面にエミッタ領域３を配置できるので、チップ面積
を小さくできるメリットもある。Therefore, the contact region 4 of the base region 2
The area can be reduced, and the emitter region 3 can be meshed to increase the peripheral length of the emitter region 3. Further, since the first emitter electrode 6 is brought into contact with the mesh-shaped emitter region 3, there is an advantage that the current capacity can be efficiently increased even with the smallest chip size. Further, since the emitter region 3 can be arranged on the entire surface of the chip due to the multilayer structure, there is an advantage that the chip area can be reduced.
【０００６】[0006]
【発明が解決しようとする課題】かかるトランジスタで
は、第１のベース電極５および第１のエミッタ電極６と
第２のベース電極８および第２のエミッタ電極９を層間
絶縁膜７で絶縁した多層配線技術を用いて、チップ全面
に活性なベース領域２およびエミッタ領域３を形成でき
るので、小さい形状でエミッタ周辺長を稼げる利点を有
する。その反面、多層配線構造を採用するために複雑な
構造となり、製造工程も増える問題点もあった。In such a transistor, a multilayer wiring in which the first base electrode 5 and the first emitter electrode 6 and the second base electrode 8 and the second emitter electrode 9 are insulated by the interlayer insulating film 7 is used. Since the active base region 2 and the emitter region 3 can be formed on the entire surface of the chip by using the technique, there is an advantage that the peripheral length of the emitter can be obtained with a small shape. On the other hand, since the multi-layer wiring structure is adopted, the structure becomes complicated and the number of manufacturing processes also increases.
【０００７】また単層電極構造の場合は、ベース電極の
ベースボンディングパッド部分の下には通常ベース領域
を配置し、エミッタ電極のエミッタボンディングパッド
部分の下には通常エミッタ領域を配置するので、両ボン
デイングパッド部分はボンディングワイヤーを固着する
ために１辺を２００μｍ位の正方形に形成される場合が
多く、両ボンデイングパッド部分のために活性な素子領
域が大幅に減少する問題点もあった。In the case of a single-layer electrode structure, the base region is usually arranged below the base bonding pad portion of the base electrode, and the emitter region is usually arranged below the emitter bonding pad portion of the emitter electrode. In many cases, the bonding pad portion is formed in a square with a side of about 200 μm for fixing the bonding wire, and there is a problem that the active element region is significantly reduced due to both bonding pad portions.
【０００８】[0008]
【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、コレクタ領域、ベース領域およびエミッタ
領域を備え、前記エミッタ領域をメッシュ状に形成し、
前記ベース領域のコンタクト領域を前記エミッタ領域に
囲まれるように島状に設け、前記ベース領域のコンタク
ト領域にコンタクトするベース電極と前記エミッタ領域
にコンタクトするエミッタ電極を櫛歯状に形成する半導
体装置において、前記ベース電極のベースパッド部分は
メッシュ状の前記エミッタ領域上に形成し且つその下に
ある前記ベース領域のコンタクト領域とコンタクトさ
せ、前記エミッタ電極のエミッタパッド部分はメッシュ
状に形成した前記ベース領域上に形成し且つこのメッシ
ュ状に形成した前記ベース領域に囲まれた前記エミッタ
領域とコンタクトさせることを特徴とする。The present invention has been made in view of the above problems, and comprises a collector region, a base region and an emitter region, and the emitter region is formed in a mesh shape,
A semiconductor device in which a contact region of the base region is provided in an island shape so as to be surrounded by the emitter region, and a base electrode contacting the contact region of the base region and an emitter electrode contacting the emitter region are formed in a comb shape. A base pad portion of the base electrode is formed on the mesh-shaped emitter region and is in contact with a contact region of the base region below the base region, and the emitter pad portion of the emitter electrode is the mesh-shaped base region. It is characterized in that it is in contact with the emitter region formed above and surrounded by the base region formed in the mesh shape.
【０００９】また、本発明はかかる課題に鑑みてなさ
れ、メッシュ状の前記エミッタ領域は前記エミッタパッ
ド部分の下を除きほぼチップ全面に形成することを特徴
とする。The present invention has been made in view of the above problems, and is characterized in that the mesh-shaped emitter region is formed on substantially the entire surface of the chip except under the emitter pad portion.
【００１０】更に、本発明はかかる課題に鑑みてなさ
れ、前記ベースパッド部分の下にはメッシュ状の前記エ
ミッタ領域を形成することを特徴とする。Further, the present invention has been made in view of the above problems, and is characterized in that the emitter region having a mesh shape is formed under the base pad portion.
【００１１】更に、本発明はかかる課題に鑑みてなさ
れ、前記エミッタパッド部分の下には島状の前記エミッ
タ領域を形成することを特徴とする。Further, the present invention has been made in view of the above problems, and is characterized in that the island-shaped emitter region is formed under the emitter pad portion.
【００１２】[0012]
【発明の実施の形態】本発明に依る半導体装置を図１か
ら図４を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described with reference to FIGS.
【００１３】図１はメッシュエミッタ構造のトランジス
タの平面図を示している。FIG. 1 is a plan view of a transistor having a mesh emitter structure.
【００１４】かかるトランジスタはＮ+型シリコン半導
体基板とその上に積層したＮ-型エピタキシャル層より
なるコレクタ領域２１と、ベース領域２２と、メッシュ
状のエミッタ領域２３とを有し、エミッタ領域２３はベ
ース領域２２全面に配置され、ベース領域２２のコンタ
クト領域２４は多数の島状にエミッタ領域２３に完全に
囲まれて配置されている。This transistor has an N + type silicon semiconductor substrate and a collector region 21 made of an N − type epitaxial layer laminated thereon, a base region 22, and a mesh-shaped emitter region 23. The contact region 24 of the base region 22 is arranged over the entire surface of the base region 22, and is arranged so as to be completely surrounded by the emitter regions 23 in the form of a large number of islands.
【００１５】ベース領域２２のコンタクト領域２４は列
状に多数個を並べており、この列を複数形成する。そし
て隣接する列間ではベース領域２２のコンタクト領域２
４は半ピッチずれて配置されており、ベース領域２２の
周辺とコンタクト領域２４以外はメッシュ状のエミッタ
領域２３となる。A large number of contact regions 24 of the base region 22 are arranged in a row, and a plurality of these rows are formed. The contact region 2 of the base region 22 is provided between the adjacent columns.
4 are arranged with a half-pitch shift, and are the mesh-shaped emitter region 23 except for the periphery of the base region 22 and the contact region 24.
【００１６】ベース電極２５ｆは各列のコンタクト領域
２４とコンタクトし、各列毎に延在された櫛歯状の形状
をしている。またベース領域２２の周辺にはエミッタ電
極２６を囲むようにアニュラー状のベース電極２５ａが
あり、上辺中央にはボンディングをされるベースパッド
部分２５ｂが設けられている。The base electrode 25f is in contact with the contact region 24 in each column and has a comb-like shape extending in each column. Further, an annular base electrode 25a is provided around the base region 22 so as to surround the emitter electrode 26, and a base pad portion 25b to be bonded is provided at the center of the upper side.
【００１７】エミッタ電極２６ｆはベース電極２５ｆの
間に延在され、エミッタ領域２３とは小さな水玉模様で
示すようにベース領域２２の各列のコンタクト領域２４
間でコンタクトしてベース電極２５ｆと噛み合った櫛歯
状に形成される。また下辺の両側には２個のボンディン
グをされるエミッタパッド部分２６ｂが設けられてい
る。The emitter electrode 26f extends between the base electrodes 25f, and the emitter regions 23 and the contact regions 24 in each column of the base region 22 are shown by a small dot pattern.
It is formed in a comb-teeth shape that is in contact with each other and meshes with the base electrode 25f. Further, two emitter pad portions 26b to be bonded are provided on both sides of the lower side.
【００１８】本発明の特徴は単層の電極構造を採用した
ことにあり、特にベース電極のベースパッド部分２５ｂ
およびエミッタ電極のエミッタパッド部分２６ｂに改善
を加えたことにある。The feature of the present invention resides in the adoption of a single-layer electrode structure, and in particular, the base pad portion 25b of the base electrode.
And that the emitter pad portion 26b of the emitter electrode is improved.
【００１９】ベース電極のベースパッド部分２５ｂおよ
びエミッタ電極のエミッタパッド部分２６ｂはボンディ
ングワイヤーがボールボンディングで固着できる大き
さ、例えば一辺を２００μｍ以上に形成されなくてはな
らない。The base pad portion 25b of the base electrode and the emitter pad portion 26b of the emitter electrode must be formed to a size such that a bonding wire can be fixed by ball bonding, for example, one side is 200 μm or more.
【００２０】そこでベース電極のベースパッド部分２５
ｂの下にはメッシュ状のエミッタ領域２３を形成し、ベ
ースパッド部分２５ｂはその下に設けたベース領域２２
のコンタクト領域２４とコンタクトさせている。このた
めにベースパッド部分２５ｂの下もトランジスタとして
活性な領域となることができる。Therefore, the base pad portion 25 of the base electrode
A mesh-shaped emitter region 23 is formed under b, and the base pad portion 25b is formed under the base region 22.
Of the contact region 24. Therefore, the region under the base pad portion 25b can also be an active region as a transistor.
【００２１】また、エミッタ電極のエミッタパッド部分
２６ｂの下には逆にメッシュ状にベース領域２２を表面
まで露出させ、このベース領域に囲まれた島状のエミッ
タ領域２３ｉを形成し、このエミッタ領域２３ｉとエミ
ッタパッド部分２６ｂとをコンタクトさせている。この
ためにエミッタパッド部分２６ｂの下でも島状のエミッ
タ領域２３ｉをベース領域２２が囲み且つ近接のアニュ
ラー状のベース電極２５ａと接続されるので、トランジ
スタとして活性な領域となることができる。On the contrary, below the emitter pad portion 26b of the emitter electrode, the base region 22 is exposed to the surface in a mesh shape, and an island-shaped emitter region 23i surrounded by this base region is formed. 23i and the emitter pad portion 26b are in contact with each other. Therefore, even under the emitter pad portion 26b, the base region 22 surrounds the island-shaped emitter region 23i and is connected to the adjacent annular base electrode 25a, so that it can be an active region as a transistor.
【００２２】チップの外周部にはＮ＋型のアニュラーリ
ング２７にコンタクトしたフィールド電極２８が設けら
れ、空乏層の拡がりを抑制している。A field electrode 28, which is in contact with the N + type annular ring 27, is provided on the outer periphery of the chip to suppress the expansion of the depletion layer.
【００２３】図２に図１のＡ−Ａ線の断面図を示す。ベ
ース領域２２に３つの島状のエミッタ領域２３ｉがエミ
ッタパッド部分２６ｂの下に設けられ、この島状のエミ
ッタ領域２３ｉがベース領域２２で囲まれている。また
エミッタパッド部分２６ｂからはフィンガー状にエミッ
タ電極２６ｆが伸びており、メッシュ状のエミッタ領域
２３とコンタクトしている。FIG. 2 is a sectional view taken along line AA of FIG. In the base region 22, three island-shaped emitter regions 23i are provided below the emitter pad portion 26b, and the island-shaped emitter regions 23i are surrounded by the base region 22. A finger-shaped emitter electrode 26f extends from the emitter pad portion 26b and is in contact with the mesh-shaped emitter region 23.
【００２４】図３に図１のＢ−Ｂ線の断面図を示す。エ
ミッタパッド部分２６ｂの下にはベース領域２２があ
り、列状に並んだベース領域２２のコンタクト領域２４
と一体に形成されている。なお、列状に並んだベース領
域２２のコンタクト領域２４にはベースパッド部分２５
ｂ側からフィンガー状に伸びるベース電極２５ｆがコン
タクトしている。FIG. 3 is a sectional view taken along line BB of FIG. The base region 22 is provided under the emitter pad portion 26b, and the contact regions 24 of the base regions 22 arranged in rows are formed.
It is formed integrally with. In addition, in the contact region 24 of the base regions 22 arranged in rows, the base pad portion 25
A base electrode 25f extending from the b side in a finger shape is in contact.
【００２５】図４に図１のＣ−Ｃ線の断面図を示す。島
状のエミッタ領域２３ｉの間にベース領域２２が設けら
れ、図２と共に島状のエミッタ領域２３ｉがメッシュ状
のベース領域２２で囲まれていることが分かる。FIG. 4 shows a sectional view taken along the line CC of FIG. It can be seen that the base region 22 is provided between the island-shaped emitter regions 23i, and the island-shaped emitter region 23i is surrounded by the mesh-shaped base region 22 together with FIG.
【００２６】なお、両パッド部分にはボンディングワイ
ヤーが圧着される場合を実施例として説明したが、半田
バンプ等を形成しても良い。Although the case where the bonding wires are pressure-bonded to both pad portions has been described as an example, solder bumps or the like may be formed.
【００２７】[0027]
【発明の効果】本発明に依れば、第１にベース電極２５
のベースパッド部分２５ｂの下には活性なメッシュ状の
エミッタ領域２３を配置し、エミッタ電極２６のエミッ
タパッド部分２６ｂの下にはベース領域２２に囲まれた
島状のエミッタ領域２３ｉを配置するので、両パッド部
分２５ｂ、２６ｂの下も活性なトランジスタ領域として
活用できる。特に、エミッタ電極２６のエミッタパッド
部分２６ｂの下にベース領域２２を設けたことにより、
少数キャリアの引き抜きが早くなりスイッチング時間が
早くなる。このために従来の２層電極のメッシュエミッ
タ構造のトランジスタのスイッチング時間１３．５ｎＳ
に比べて、本発明でも同程度のスイッチング時間を実現
できた。According to the present invention, firstly, the base electrode 25
Since the active mesh-shaped emitter region 23 is arranged below the base pad portion 25b of the above, and the island-shaped emitter region 23i surrounded by the base region 22 is arranged below the emitter pad portion 26b of the emitter electrode 26. The area under both pad portions 25b and 26b can also be utilized as an active transistor region. In particular, by providing the base region 22 below the emitter pad portion 26b of the emitter electrode 26,
Minority carrier extraction is faster and switching time is faster. For this reason, the switching time of the conventional transistor having the mesh emitter structure of two-layer electrode is 13.5 nS.
Compared with the above, the present invention can realize the same switching time.
【００２８】第２に、飽和電圧（VCE(sat)）はエミッタ
領域２３の周辺長に大きく依存するので、本発明に依れ
ばベース電極２５のベースパッド部分２５ｂの下にもメ
ッシュ状のエミッタ領域２３を設け、エミッタ電極２６
のエミッタパッド部分２６ｂの下にも島状のエミッタ領
域２３ｉを設けてエミッタ領域２３の周辺長を稼いでい
る。このために、同一チップサイズの従来の２層電極の
メッシュエミッタ構造のトランジスタの飽和電圧（３Ｖ
/６０ｍＡ）が１１４Ｖに対して本発明では１６７Ｖと
かなり低電圧まで改善を図れているが、従来の単層電極
の場合は２６０Ｖ程度が想定されこれに比べると大幅な
改善ができている。Second, since the saturation voltage (VCE (sat)) greatly depends on the peripheral length of the emitter region 23, according to the present invention, the mesh-shaped emitter is also formed under the base pad portion 25b of the base electrode 25. The region 23 is provided and the emitter electrode 26
An island-shaped emitter region 23i is also provided under the emitter pad portion 26b to increase the peripheral length of the emitter region 23. For this reason, the saturation voltage (3V) of the conventional two-layer electrode mesh emitter structure transistor of the same chip size is used.
(/ 60 mA) of 114 V, the present invention can improve the voltage to 167 V, which is a considerably low voltage, but in the case of the conventional single-layer electrode, it is expected to be about 260 V, which is a significant improvement.
【００２９】また電流容量も同様にエミッタ領域２３の
周辺長が大きく影響するので、本発明では大幅な改善が
図れる。具体的には、同一チップサイズの従来の２層電
極のメッシュエミッタ構造のトランジスタのコレクタ電
流容量Ｉｃ（１／２ｈFEの時）が８Ａに対して本発明で
は６．８Ａと改善を図れている。Similarly, the current capacity is greatly affected by the peripheral length of the emitter region 23, so that the present invention can be greatly improved. Specifically, the collector current capacity Ic (at 1/2 h FE ) of a conventional transistor of the same chip size having a two-layer electrode mesh emitter structure is 8 A, whereas the present invention is improved to 6.8 A. .
【００３０】第３に、本発明は単層電極構造であるの
で、多層構造に比べて多層電極を形成するマスク枚数が
減少でき、工程設備も電極のスパッタ装置、層間絶縁膜
を形成するＣＶＤ装置、ホトエッチング装置等を無くす
ることができ、大幅なコストダウンが図れる利点もあ
る。Thirdly, since the present invention has a single-layer electrode structure, the number of masks for forming a multi-layer electrode can be reduced as compared with a multi-layer structure, and the process equipment is a sputtering apparatus for electrodes and a CVD apparatus for forming an interlayer insulating film. It is also possible to eliminate the photo-etching device and the like, and there is an advantage that a large cost reduction can be achieved.
【図１】本発明の半導体装置を説明する平面図である。FIG. 1 is a plan view illustrating a semiconductor device of the present invention.
【図２】本発明の半導体装置を説明する断面図であり、
図１のＡ−Ａ線の断面図である。FIG. 2 is a cross-sectional view illustrating a semiconductor device of the present invention,
It is sectional drawing of the AA line of FIG.
【図３】本発明の半導体装置を説明する断面図であり、
図１のＢ−Ｂ線の断面図である。FIG. 3 is a cross-sectional view illustrating a semiconductor device of the present invention,
It is sectional drawing of the BB line of FIG.
【図４】本発明の半導体装置を説明する断面図であり、
図１のＣ−Ｃ線の断面図である。FIG. 4 is a cross-sectional view illustrating a semiconductor device of the present invention,
It is sectional drawing of the CC line of FIG.
【図５】従来の半導体装置を説明する平面図である。FIG. 5 is a plan view illustrating a conventional semiconductor device.
【図６】従来の半導体装置を説明する断面図であり、図
５のＹ−Ｙ線の断面図である。6 is a cross-sectional view illustrating a conventional semiconductor device, which is a cross-sectional view taken along the line YY of FIG.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/33 - 21/331 H01L 29/68 - 29/737 H01L 21/28 - 21/288 H01L 29/40 - 29/51 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/28-21/288 H01L 29 / 40-29/51
Claims (4)
タ領域を備え、前記エミッタ領域をメッシュ状に形成
し、前記べ一ス領域のコンタクト領域を前記エミッタ領
域に囲まれるように島状に設け、前記べ一ス領域のコン
タクト領域にコンタクトするべ一ス電極と前記エミッタ
領域にコンタクトするエミッタ電極を櫛歯状に形成する
半導体装置において、前記ベース電極のベースパッド部
分はメッシュ状の前記エミッタ領域上に形成し且つその
下にある前記べ一ス領域のコンタクト領域とコンタクト
させ、前記エミッタ電極のエミッタパッド部分はメッシ
ュ状に形成した前記べ一ス領域上に形成し且つこのメッ
シュ状に形成した前記ベース領域に囲まれた前記エミッ
タ領域とコンタクトさせて、前記ベース電極のベースパ
ッド部分の下および前記エミッタ電極のエミッタパッド
部分の下をトランジスタ領域として活用することを特徴
とする半導体装置。1. A collector region, a base region, and an emitter region are provided, the emitter region is formed in a mesh shape, and the contact region of the base region is provided in an island shape so as to be surrounded by the emitter region. In a semiconductor device in which a base electrode that contacts a contact region of one base region and an emitter electrode that contacts the emitter region are formed in a comb shape, the base pad portion of the base electrode is formed on the mesh-shaped emitter region. And contacting the contact region of the base region thereunder, the emitter pad portion of the emitter electrode is formed on the base region formed in a mesh shape, and the base region formed in the mesh shape. The base region of the base electrode is contacted with the emitter region surrounded by
Under the pad portion and the emitter pad of the emitter electrode
A semiconductor device characterized in that a portion below the portion is utilized as a transistor region .
ミッタパッド部分の下を除き前記ベース電極のベースパ
ッド部分を含むほぼチップ全面に形成することを特徴と
する請求項1記載の半導体装置。2. The base region of the base electrode except for the portion under the emitter pad portion of the mesh-shaped emitter region.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on substantially the entire surface of the chip including the pad portion .
前記エミッタ領域を形成することを特徴とする請求項1
記載の半導体装置。3. The island-shaped emitter region is formed under the emitter pad portion.
The semiconductor device described.
は単層の電極材料より形成されることを特徴とする請求
項１または請求項２記載の半導体装置。4. The semiconductor device according to claim 1, wherein the base electrode and the emitter electrode are formed of a single layer of electrode material.
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|---|---|---|---|
| JP2000075023A JP3515473B2 (en) | 2000-03-17 | 2000-03-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000075023A JP3515473B2 (en) | 2000-03-17 | 2000-03-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001267329A JP2001267329A (en) | 2001-09-28 |
| JP3515473B2 true JP3515473B2 (en) | 2004-04-05 |
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|---|---|---|---|---|
| JP4425034B2 (en) * | 2004-03-29 | 2010-03-03 | 三洋電機株式会社 | Semiconductor device |
| JP4308060B2 (en) * | 2004-03-29 | 2009-08-05 | 三洋電機株式会社 | Semiconductor device |
| JP2006049693A (en) * | 2004-08-06 | 2006-02-16 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2006066714A (en) * | 2004-08-27 | 2006-03-09 | Matsushita Electric Ind Co Ltd | Transistor |
| JP5588615B2 (en) * | 2009-01-16 | 2014-09-10 | ローム株式会社 | Bipolar semiconductor device and manufacturing method thereof |
| JP2014232883A (en) * | 2014-07-28 | 2014-12-11 | ローム株式会社 | Bipolar semiconductor device |
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