JP2014232883A - Bipolar semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed bipolar semiconductor device and a method of manufacturing the same.SOLUTION: There is provided a bipolar semiconductor device including: a collector region 10; a base region 12 disposed on the collector region 10; an emitter region 14 disposed on the base region 12; an emitter pad region 34 disposed on the base region 12 and commonly formed with the emitter region 14; a base electrode 20 disposed on the base region 12 and connected to the base region 12 via a plurality of base contacts CB; an emitter electrode 18 disposed on the emitter region 14; and an emitter pad electrode 24 disposed on the emitter pad region 34 near the base region 12, and there is provided a method of manufacturing the bipolar semiconductor device. The semiconductor device may include an insulating layer 26 disposed on the emitter pad region 34. In such a case, the emitter pad electrode 24 is disposed on the insulating layer 26.

Description

  The present invention relates to a bipolar semiconductor device, and more particularly to a bipolar semiconductor device that has been increased in speed.

  The problem with bipolar transistors is that their switching speed is slow compared to insulated gate field effect transistors (MOSFETs). This is because in the bipolar transistor, carriers are injected from the base at the turn-on switching, so that the injected carriers remain in the base layer at the turn-off switching.

  A power bipolar transistor capable of increasing the current amplification factor while increasing the base width and widening the safe operation area and increasing the current amplification factor and the manufacturing method thereof have already been disclosed (for example, patents). Reference 1). On the other hand, bipolar that can secure the area of the emitter region for increasing the current, increase the area of the protection diode without increasing the chip area, and protect against a large reverse current corresponding to a large forward current Transistors have already been disclosed (for example, see Patent Document 2).

  In particular, in a bipolar transistor, at the time of turn-off switching, the collector current Ic flows through the center of the emitter section as a current path, so that carriers remain immediately below the emitter. Immediately below the emitter where the carriers remain, since the distance from the base electrode is long, the removal of carriers from the base electrode is delayed, and the absorption effect from the base electrode is poor.

  Conventionally, since a bonding wire has to be hit on the emitter portion, it is necessary to provide a bonding pad. Since the base electrode wiring cannot be provided in the emitter bonding pad portion, the vicinity of the emitter bonding pad is further away from the base electrode.

  For this reason, in the bipolar transistor, the arrangement of the base and the emitter is optimized or the bonding pad portion is effectively utilized by multilayer wiring or the like in order to increase the speed and efficiency. However, in the multilayer wiring, the reliability is lowered and the manufacturing cost is increased.

JP 2000-340573 A JP 2004-119777 A

  An object of the present invention is to provide a bipolar semiconductor device that has been increased in speed.

  According to one aspect of the present invention, a first conductivity type collector region, a second conductivity type base region disposed on the collector region, and a first conductivity type emitter region disposed on the base region. A base electrode disposed on the base region and connected to the base region via a plurality of base contacts, an emitter electrode disposed on the emitter region, and a bonding wire provided on the emitter electrode A bipolar semiconductor device comprising: an insulating layer interposed between the emitter region and the bonding wire and covering the emitter region under the bonding wire; and an emitter contact for conducting the emitter electrode and the emitter region Is provided.

  According to another aspect of the present invention, a first conductivity type collector region, a second conductivity type base region disposed on the collector region, and a first conductivity type emitter disposed on the base region. A region, a base electrode disposed on the base region and connected to the base region via a plurality of base contacts, an emitter electrode disposed directly only on the outer peripheral region of the emitter region, and the emitter A bipolar semiconductor device including a bonding wire provided on an electrode is provided.

  According to the present invention, it is possible to provide a bipolar semiconductor device with a high speed.

1 is a schematic plane pattern configuration diagram of a bipolar semiconductor device according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic cross-sectional structure diagram taken along line II in FIG. 1. FIG. 2 is a schematic cross-sectional structure diagram taken along line II-II in FIG. 1. FIG. 10 is an operation explanatory view of a semiconductor device according to a comparative example. FIG. 3 is an operation explanatory diagram of the bipolar semiconductor device according to the first embodiment of the present invention. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the bipolar type semiconductor device which concerns on the 1st Embodiment of this invention. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the bipolar type semiconductor device which concerns on the 1st Embodiment of this invention. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the bipolar type semiconductor device which concerns on the 1st Embodiment of this invention. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the bipolar type semiconductor device which concerns on the 1st Embodiment of this invention. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the bipolar type semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a plan pattern photograph example of a bipolar semiconductor device according to a first embodiment of the present invention. (A) Example of planar pattern photograph in which base contacts CB are arranged in a rectangular shape in the bipolar semiconductor device according to the first embodiment of the present invention, (b) An explanatory diagram of a rectangular pattern. In the bipolar type semiconductor device which concerns on the 1st Embodiment of this invention, the example of the plane pattern which has arrange | positioned the base contact CB in hexagon shape, (b) Explanatory drawing of a hexagonal pattern. FIG. 14 is a diagram showing a relationship between a cell pitch L _p and a collector-emitter saturation voltage V _{CE (sat) in} the structure of FIG. 13. An example of a turn-off switching waveform of the collector current Ic. The typical plane pattern block diagram which shows 1 process of the manufacturing method of the bipolar type semiconductor device which concerns on the modification of the 1st Embodiment of this invention. FIG. 17 is a schematic sectional view taken along the line II of FIG.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention have the following structure and arrangement of components. It is not something specific. The embodiment of the present invention can be variously modified within the scope of the claims.

[First Embodiment]
(Element structure)
A schematic planar pattern configuration of the bipolar semiconductor device according to the first embodiment of the present invention is represented as shown in FIG. 1, and a schematic cross-sectional structure taken along line II of FIG. 1 is shown in FIG. A schematic cross-sectional structure taken along line II-II in FIG. 1 is represented as shown in FIG.

  As shown in FIGS. 1 to 3, the bipolar semiconductor device according to the first embodiment is arranged on the collector region 10, the base region 12 disposed on the collector region 10, and the base region 12. An emitter region 14, an emitter pad region 34 disposed on the base region 12 and formed in common with the emitter region 14, a base region 12, and connected to the base region 12 via a plurality of base contacts CB. A base electrode 20, an emitter electrode 18 disposed on the emitter region 14, and an emitter pad electrode 24 disposed on an emitter pad region 34 near the base region 12.

  Further, as shown in FIG. 2, an insulating layer 26 is provided on the emitter pad region 34, and the emitter pad electrode 24 is provided on the emitter pad region 34 in the vicinity of the base region 12 and on the insulating layer 26. Yes.

  The base contacts may be arranged in a rectangular pattern, a hexagonal pattern, or a houndstooth pattern.

  In FIG. 1, reference numerals 12a and 14a denote a peripheral p diffusion layer and a peripheral n diffusion layer, respectively. The peripheral p diffusion layer 12 a may be formed simultaneously with the base region 12, and the peripheral n diffusion layer 14 a may be formed simultaneously with the emitter region 14.

  An interval W1 between the peripheral p diffusion layer 12a and the base region 12 is, for example, about 50 μm to 60 μm. The width WE of the emitter region 14 is about 20 μm to 30 μm, for example, and the width WCE of the emitter contact is about 10 μm to 20 μm, for example. Further, the width WB of the base electrode 20 is, for example, about 12 μm to 20 μm, and the width WCB of the base contact CB is, for example, about 2 μm to 10 μm. The diffusion depth of the base region 12 is, for example, about 2 μm to 6 μm, and the diffusion depths of the emitter region 14 and the peripheral n diffusion layer 14 a are, for example, about 0.5 μm to 3 μm.

(Description of operation)
The operation description of the semiconductor device according to the comparative example is expressed as shown in FIG. 4, and the operation description of the bipolar semiconductor device according to the first embodiment is expressed as shown in FIG.

  As shown in FIG. 4, in the semiconductor device according to the comparative example, the emitter pad electrode 24 is connected to the entire surface of the emitter pad region 34, so that the residual carrier remains in the emitter pad region 34 separated from the base region 12. Since it is concentrated in the center, carrier turn-off is slow during turn-off switching, and the turn-off switching speed is slow.

  On the other hand, in the bipolar semiconductor device according to the first embodiment, as shown in FIG. 5, an insulating layer 26 such as an oxide film is laid directly under the emitter pad electrode 24 forming the emitter bonding pad. By providing the contact portion to the emitter pad region 34 only in the vicinity of the base region 12, the collector current Ic path can be concentrated in the vicinity of the base region 12.

  In the bipolar semiconductor device according to the first embodiment, as shown in FIG. 5, since the remaining carriers are concentrated in the vicinity of the base region 12, the carriers are quickly removed during the turn-off switching, and the turn-off switching is performed. Increases speed.

  Further, in the bipolar semiconductor device according to the first embodiment, as shown in FIG. 5, since carriers are originally generated in the vicinity of the base region 12 at the time of turn-on switching, a predetermined turn-on switching speed can be secured. it can.

  Further, in the bipolar semiconductor device according to the first embodiment, an insulating layer 26 is laid immediately below the emitter pad electrode 24 forming the emitter bonding pad, so that the impact at the time of emitter wire bonding can be reduced to the emitter pad region 34 directly below. It can play the role of a cushion that is not communicated to, and can improve reliability.

(Production method)
A schematic planar pattern configuration showing one process of the manufacturing method of the bipolar semiconductor device according to the first embodiment is expressed as shown in FIGS.

  The bipolar semiconductor device manufacturing method according to the first embodiment includes a step of forming a collector region 10 and a step of forming a base region 12 on the collector region 10 as shown in FIGS. A step of forming an emitter pad region 34 in common with the emitter region 14 and the emitter region 14 on the base region 12, a step of forming the base electrode 20 on the base region 12 via a plurality of base contacts CB, and an emitter region 14 A step of forming the emitter electrode 18 thereon, and a step of forming the emitter pad electrode 24 on the emitter pad region 34 in the vicinity of the base region 12.

  Furthermore, the method for manufacturing the bipolar semiconductor device according to the first embodiment includes the step of forming the insulating layer 26 on the emitter pad region 34, and the step of forming the emitter pad electrode 24 includes the step of forming the emitter pad electrode 24. 24 is formed on the emitter pad region 34 in the vicinity of the base region 12 and on the insulating layer 26.

  A method for manufacturing the bipolar semiconductor device according to the first embodiment will be described below with reference to FIGS.

(A) First, as shown in FIG. 6, a base region 12 and a peripheral p diffusion layer 12a are formed. These regions can be formed by, for example, a boron (B) diffusion method or an ion implantation technique. Further, the peripheral p diffusion layer 12a may be formed thicker than the base region 12, and in that case, a diffusion or ion implantation technique divided into two stages can be applied.
(B) Next, as shown in FIG. 7, the emitter region 14, the emitter pad region 34, and the peripheral n diffusion layer 14a are formed. These regions can be formed by, for example, an ion implantation technique of phosphorus (P) or arsenic (As) or a diffusion method. The peripheral n diffusion layer 14a may be formed at the same time as the emitter region 14 and the emitter pad region 34, or may be formed by separate steps.
(C) Next, as shown in FIG. 8, after the insulating layer 16 is formed, a window is opened for the base contact CB and the emitter contact. As a material of the insulating layer 16, a thermal oxide film, a CVD (Chemical Vapor Deposition) oxide film, a CVD nitride film, a TEOS (Tetraethoxysilane) film, or the like can be applied.
(D) Next, as shown in FIG. 9, the emitter electrode 18 and the peripheral n-contact electrode 18a are formed, and the base electrode 20 is formed. These electrodes can be formed by a vacuum deposition method of aluminum (Al).
(E) Next, as shown in FIG. 10, the base pad electrode 22, the peripheral pad electrode 22a, and the emitter pad electrode 24 are formed. When these pad electrodes are formed, a CVD nitride film is formed on the entire surface after the step of FIG. 9, and a window is opened only in the formation region of these pad electrodes, and then an Al electrode is formed. it can. FIG. 3 shows that the CVD nitride film (not shown) is peeled off at the periphery.

  Through the above steps, finally, as shown in FIGS. 1 and 2 to 3, the bipolar semiconductor device according to the first embodiment is formed.

(Prototype result)
FIG. 11 shows an example of a photograph of a planar pattern produced as a prototype of the bipolar semiconductor device according to the first embodiment. The chip size in FIG. 11 is 0.9 mm square, and the current capacity is about 2 A. The emitter area is about 5 × 10 ⁵ (μm ² ), and the emitter peripheral length is about 10 mm.

  As shown in FIG. 11, a base bonding wire 30 is formed on the base pad electrode 22, and an emitter bonding wire 32 is formed on the emitter pad electrode 24.

  In the bipolar semiconductor device according to the first embodiment, a plane pattern photograph in which base contacts CB are arranged in a rectangular shape is shown in FIG. 12A, and an explanatory diagram thereof is shown in FIG.

  Further, in the bipolar semiconductor device according to the first embodiment, a plane pattern photograph in which base contacts CB are arranged in a hexagonal shape is shown in FIG. 13A, and an explanatory diagram thereof is shown in FIG. When the base contact CB is arranged in a rectangular shape, as shown in FIG. 12B, the base contact CB is arranged in a hexagonal shape with a relatively large area at the center of the rectangle that becomes a current injection invalid region. In this case, since the area of the central portion of the triangle is relatively small and the distance from the base contact CB is equal, current injection can be performed efficiently. The ratio of the beauty region per unit area is 21.5% when the base contact CB is arranged in a rectangular shape, whereas when the base contact CB is arranged in a hexagonal shape, it is 8. Reduced to 1%.

(Experimental result)
In the structure example of FIG. 13 in which the base contact CB is arranged in a hexagonal shape as the bipolar semiconductor device according to the first embodiment, the relationship between the cell pitch L _p and the collector-emitter saturation voltage V _{CE (sat)} is For example, a result as shown by a curve B in FIG. 14 is obtained. A corresponds to the case where the base contacts CB are arranged in a rectangular shape.

For example, when the pattern pitch L _p is about 100 μm, for example, the value of the collector-emitter saturation voltage V _{CE (sat)} is about 143 mV when the base contact CB is arranged in a rectangular shape at Ic = 1A. On the other hand, when the base contact CB is arranged in a hexagonal shape, it is about 128 mV. As is clear from FIG. 14, in the structure example of FIG. 13 in which the base contacts CB are arranged in a hexagonal shape, there is a pattern pitch L _p that minimizes the collector-emitter saturation voltage V _{CE (sat)} . The minimum value of the collector-emitter saturation voltage V _{CE (sat)} is, for example, about 100 mV, and the pattern pitch L _p is, for example, about 60 μm to 80 μm.

  Further, in the structure example of FIG. 13 in which the base contact CB is arranged in a hexagonal shape as the bipolar semiconductor device according to the first embodiment, the turn-off switching waveform of the collector current Ic is expressed as shown in FIG. The Compared to the conventional structure, in the bipolar semiconductor device according to the first embodiment, the turn-off switching speed is improved by about 30%.

  According to the bipolar semiconductor device and the manufacturing method thereof according to the first embodiment, it is possible to provide a bipolar semiconductor device and a manufacturing method thereof that are increased in speed.

(Modification)
A schematic planar pattern configuration showing one process of the manufacturing method of the bipolar semiconductor device according to the modification of the first embodiment is expressed as shown in FIG. Further, a schematic cross-sectional structure taken along line II of FIG. 16 is expressed as shown in FIG.

  The bipolar semiconductor device according to the modification of the first embodiment is characterized in that the emitter pad electrode 24 is disposed only in the vicinity of the base region 12. Only the opening 28 is formed without forming the insulating layer 26 in the center of the emitter pad region 34. Since the other structure is the same as that of the bipolar semiconductor device according to the first embodiment, a duplicate description is omitted. In addition, since the manufacturing method of the bipolar semiconductor device according to the modification of the first embodiment is the same as the manufacturing method of the bipolar semiconductor device according to the first embodiment, the duplicate description is omitted.

  According to the bipolar semiconductor device and the manufacturing method thereof according to the modification of the first embodiment, it is possible to provide a bipolar semiconductor device and a manufacturing method thereof that are increased in speed.

[Other embodiments]
As described above, the present invention has been described with reference to the first embodiment and its modifications. However, the discussion and the drawings that form a part of this disclosure are illustrative and are intended to limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, a semiconductor device having a structure in which n-type and p-type conductivity types are reversed may be formed. In the above embodiment, the semiconductor device having one bipolar transistor has been described as an example. However, the present invention can be applied to a semiconductor device having a plurality of bipolar transistors. The present invention can also be applied to a bipolar semiconductor device having a pn junction other than a bipolar transistor, such as a thyristor, a triac, or a gate turn-off thyristor (GTO).

  As described above, the present invention includes various embodiments not described herein.

  Since the bipolar semiconductor device of the present invention exhibits high-speed switching performance, it can be applied to a wide range of fields such as various power conversion devices from low power to large power, power modules, and in-vehicle bipolar semiconductor devices.

DESCRIPTION OF SYMBOLS 10 ... Collector region 12 ... Base region 12a ... Peripheral p diffusion layer 14 ... Emitter region 14a ... Peripheral n diffusion layer 16, 26 ... Insulating layer 18 ... Emitter electrode 18a ... Peripheral n contact electrode 20 ... Base electrode 22 ... Base Pad electrode 22a ... peripheral pad electrode 24 ... emitter pad electrode 28 ... opening 30 ... base bonding wire 32 ... emitter bonding wire 34 ... emitter pad region E ... emitter pad B ... base pad CB ... base contact WE ... emitter region 14 Width WB ... Width WCE of base electrode 20 ... Width WCB of emitter contact ... Width W1 of base contact CB ... Space between peripheral p diffusion layer 12a and base region 12

Claims (7)

A collector region of a first conductivity type;
A base region of a second conductivity type disposed on the collector region;
An emitter region of a first conductivity type disposed on the base region;
A base electrode disposed on the base region and connected to the base region via a plurality of base contacts;
An emitter electrode disposed on the emitter region;
A bonding wire provided on the emitter electrode;
An insulating layer interposed between the emitter region and the bonding wire and covering the emitter region under the bonding wire;
A bipolar semiconductor device, comprising: an emitter contact for conducting the emitter electrode and the emitter region.   2. The bipolar semiconductor device according to claim 1, wherein the emitter contact is disposed so as to surround the bonding wire in a plan view.   The emitter electrode is directly disposed on the first region of the outer peripheral portion of the emitter region through the emitter contact, and the insulating layer is formed on a second region other than the first region of the emitter region. The bipolar semiconductor device according to claim 1, wherein the bipolar semiconductor device is disposed indirectly via a pin.   The bipolar semiconductor device according to claim 1, wherein the base contacts are arranged in a rectangular pattern.   The bipolar semiconductor device according to claim 1, wherein the base contacts are arranged in a hexagonal pattern.   The bipolar semiconductor device according to claim 1, wherein the base contacts are arranged in a staggered pattern. A collector region of a first conductivity type;
A base region of a second conductivity type disposed on the collector region;
An emitter region of a first conductivity type disposed on the base region;
A base electrode disposed on the base region and connected to the base region via a plurality of base contacts;
An emitter electrode disposed directly only on the outer peripheral region of the emitter region;
A bipolar semiconductor device, comprising: a bonding wire provided on the emitter electrode.