JP4308060B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4308060B2
JP4308060B2 JP2004094688A JP2004094688A JP4308060B2 JP 4308060 B2 JP4308060 B2 JP 4308060B2 JP 2004094688 A JP2004094688 A JP 2004094688A JP 2004094688 A JP2004094688 A JP 2004094688A JP 4308060 B2 JP4308060 B2 JP 4308060B2
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electrode
base
emitter
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emitter electrode
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JP2005285912A (en
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修 赤木
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Sanyo Electric Co Ltd
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Priority to CNB2005100041017A priority patent/CN100394613C/en
Priority to KR1020050014153A priority patent/KR100616050B1/en
Priority to US11/065,344 priority patent/US7598521B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

本発明は半導体装置に係り、特にエミッタ抵抗の低減を図る半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that reduces emitter resistance.

図４を参照して従来の半導体装置を、ｎｐｎ型トランジスタを例に説明する。   A conventional semiconductor device will be described with reference to FIG. 4 by taking an npn transistor as an example.

図４（Ａ）は半導体素子１００の全体の概要図であり、図４（Ｂ）は、１層目の電極構造の平面図であり、図４（Ｃ）は図４（Ｂ）のＣ−Ｃ線断面図である。   4A is a schematic view of the entire semiconductor element 100, FIG. 4B is a plan view of the first-layer electrode structure, and FIG. 4C is a cross-sectional view of FIG. FIG.

ｎ＋型シリコン半導体基板５１上に、例えばｎ型エピタキシャル層を積層するなどしてコレクタ領域５２を設ける。コレクタ領域５２表面にはｐ型不純物領域であるベース領域５３を設け、ベース領域５３表面には格子状にｎ＋型不純物を拡散して、エミッタ領域５４が形成される。これによりベース領域５３は島状に分離され、エミッタ領域５４と交互に配置される。尚、島状に分離されているのは表面的な構造であり、エミッタ領域５４より深く形成されるベース領域５３は、深い領域で１つの連続した領域となっている。 A collector region 52 is provided on the n + -type silicon semiconductor substrate 51 by, for example, laminating an n-type epitaxial layer. A base region 53 which is a p-type impurity region is provided on the surface of the collector region 52, and an emitter region 54 is formed on the surface of the base region 53 by diffusing n + -type impurities in a lattice shape. As a result, the base regions 53 are separated into island shapes and are alternately arranged with the emitter regions 54. It is to be noted that the island structure is separated from the surface structure, and the base region 53 formed deeper than the emitter region 54 is one continuous region in a deep region.

このように島状に分割されたベース領域とその周辺のエミッタ領域で形成されるトランジスタを、以下セルと称し、多数のセルが配置された領域を動作領域５８と称する。   A transistor formed of the base region divided into islands and the emitter region around the island is hereinafter referred to as a cell, and a region where a large number of cells are arranged is referred to as an operation region 58.

ベース領域５３およびエミッタ領域５４に接続するベース電極およびエミッタ電極はそれぞれ２層構造となっている。   Each of the base electrode and the emitter electrode connected to the base region 53 and the emitter region 54 has a two-layer structure.

１層目となる第１ベース電極５６は、島状または短冊状に設けられ、第１絶縁膜２５に設けた第１ベースコンタクトホールＢＣ１を介してベース領域５３とコンタクトする。第１エミッタ電極５７は、格子状に設けられ、第１絶縁膜２５に設けた第１エミッタコンタクトホールＥＣ１を介してエミッタ領域５４とコンタクトする。   The first base electrode 56 which is the first layer is provided in an island shape or a strip shape, and is in contact with the base region 53 via the first base contact hole BC1 provided in the first insulating film 25. The first emitter electrode 57 is provided in a lattice shape and is in contact with the emitter region 54 through the first emitter contact hole EC1 provided in the first insulating film 25.

これら第１のベース電極５６およびエミッタ電極５７上に、２層目となる第２ベース電極６６および第２エミッタ電極６７が設けられ、第２絶縁膜２６に設けた第２ベースコンタクトホール（ここでは不図示）、第２エミッタコンタクトホールＥＣ２（ここでは不図示）を介して接続する。   A second base electrode 66 and a second emitter electrode 67 which are second layers are provided on the first base electrode 56 and the emitter electrode 57, and a second base contact hole (here, the second insulating film 26). And a second emitter contact hole EC2 (not shown here) for connection.

第２ベース電極６６は、すべての島状の第１ベース電極５６と短冊状の第１ベース電極５６の一部上に設けられてこれらとコンタクトする。第２エミッタ電極６７は短冊状の第１ベース電極５６上方に設けられ、第１エミッタ電極５７とコンタクトする。   The second base electrode 66 is provided on and in contact with a part of all the island-shaped first base electrodes 56 and the strip-shaped first base electrodes 56. The second emitter electrode 67 is provided above the strip-shaped first base electrode 56 and is in contact with the first emitter electrode 57.

このように、第２ベース電極６６および第２エミッタ電極６７を第１層目の電極を平板状に覆う形状とし、これらの２層目の電極にワイヤボンドすることで、ワイヤボンドが可能な領域を拡大することができ、組み立て時の汎用性が高まる。また、第２ベース電極６６と第２エミッタ電極６７は、それぞれの矩形の１辺で隣り合うのみであるので、マスクの合わせずれや、所望のレジストパターンを得るための離間距離はこの部分のみを考慮すればよい（例えば特許文献１参照。）。
特開２０００−４０７０３号公報 As described above, the second base electrode 66 and the second emitter electrode 67 are shaped so as to cover the first layer electrode in a flat plate shape and wire bonded to these second layer electrodes, thereby enabling wire bonding. The versatility at the time of assembly increases. In addition, since the second base electrode 66 and the second emitter electrode 67 are adjacent to each other only on one side of the respective rectangles, the mask misalignment and the separation distance for obtaining a desired resist pattern are limited to this portion. What is necessary is just to consider (for example, refer patent document 1).
JP 2000-40703 A

図５には、上記の半導体チップ１００を実装する場合を示す。   FIG. 5 shows a case where the semiconductor chip 100 is mounted.

組み立て工程において、例えば図５の如く、チップの１つの辺（図ではチップの下辺となる辺）側にベースおよびエミッタの両端子を配置する場合がある。このような場合には、１つのチップ辺に沿って並んだ外部端子（例えばリード）２００と、第２エミッタ電極６７および第２ベース電極６６とを接続するので、平板状の電極構造であれば図のごとくボンディングワイヤ１５０により接続できる。   In the assembly process, for example, as shown in FIG. 5, there are cases where both terminals of the base and the emitter are arranged on one side of the chip (in the figure, the lower side of the chip). In such a case, since the external terminals (for example, leads) 200 arranged along one chip side are connected to the second emitter electrode 67 and the second base electrode 66, a flat electrode structure can be used. It can be connected by the bonding wire 150 as shown.

ここで、バイポーラトランジスタの特性向上のためにはエミッタ抵抗の低減が望ましい。このため例えば第２エミッタ電極６７の面積を大きく確保したり、ボンディングワイヤをなるべく短くするなどの工夫がなされる。   Here, it is desirable to reduce the emitter resistance in order to improve the characteristics of the bipolar transistor. For this reason, for example, the area of the second emitter electrode 67 is ensured to be large, or the bonding wire is made as short as possible.

また、特に、パッケージの薄型化に伴い、ボンディングワイヤのループを低くする要望がある。このとき低いループがチップ端部に接触しないように、ワイヤボンド位置を図の如くチップの端部付近にする場合がある。   In particular, as the package becomes thinner, there is a desire to reduce the bonding wire loop. At this time, the wire bond position may be near the end of the chip as shown in the figure so that the low loop does not contact the end of the chip.

しかし、電流経路となる部分は第１エミッタ電極５７と第２エミッタ電極６７の２層部分と第２エミッタ電極６７だけの１層部分があり、ワイヤボンド位置がチップ端部になると、例えば図では上辺側の第１エミッタ電極５７からワイヤボンド位置までのエミッタ抵抗が高くなってしまう。このため、エミッタ抵抗の低減またはチップの薄型化が進まない問題があった。   However, the current path portion has a two-layer portion of the first emitter electrode 57 and the second emitter electrode 67 and a one-layer portion of only the second emitter electrode 67. The emitter resistance from the first emitter electrode 57 on the upper side to the wire bond position is increased. For this reason, there has been a problem that emitter resistance is reduced or the chip is not thinned.

本発明は上述した種々の問題点に鑑みてなされたものであり、第１に、コレクタ領域となる一導電型半導体基板と、前記基板上に設けられた逆導電型のベース領域と、前記ベース領域表面に格子状に設けられた一導電型のエミッタ領域と、前記ベース領域とコンタクトする第１ベース電極と、前記エミッタ領域とコンタクトする第１エミッタ電極と、前記第１ベース電極および前記第１エミッタ電極上に絶縁膜を介して設けられ前記第１ベース電極と接続する１つの平板状の第２ベース電極と、前記第１ベース電極および前記第１エミッタ電極上に前記絶縁膜を介して設けられ前記第１エミッタ電極と接続する１つの平板状の第２エミッタ電極とを具備し、前記第２エミッタ電極下方の第１ベース電極および第１エミッタ電極は並行に複数配置され、該複数の第１ベース電極は端部で束ねられて前記第２ベース電極に接続することにより解決するものである。   The present invention has been made in view of the various problems described above. First, a one-conductivity-type semiconductor substrate serving as a collector region, a reverse conductivity-type base region provided on the substrate, An emitter region of one conductivity type provided in a grid pattern on the surface of the region, a first base electrode in contact with the base region, a first emitter electrode in contact with the emitter region, the first base electrode, and the first base electrode One flat second base electrode provided on the emitter electrode via an insulating film and connected to the first base electrode, and provided on the first base electrode and the first emitter electrode via the insulating film A flat plate-like second emitter electrode connected to the first emitter electrode, and a plurality of the first base electrode and the first emitter electrode below the second emitter electrode are arranged in parallel. Is a first base electrode of said plurality of solves by connecting to the second base electrode are bundled at the end.

また、前記第１ベース電極が束ねられる端部付近の第２ベース電極および第２エミッタ電極に、外部端子との接続手段が固着されることを特徴とするものである。   The second base electrode and the second emitter electrode in the vicinity of the end where the first base electrode is bundled are fixedly connected to an external terminal.

第２に、半導体基板にコレクタ領域とベース領域とエミッタ領域を設け、前記ベース領域にコンタクトする第１ベース電極と前記エミッタ領域にコンタクトする第１エミッタ電極と、前記第１ベース電極および第１エミッタ電極上に絶縁膜を介して設けられた第２ベース電極および第２エミッタ電極とを有する半導体チップと、前記半導体チップの１つの辺に沿って配置されたベース端子およびエミッタ端子と、前記ベース端子と前記第２ベース電極および前記エミッタ端子と第２エミッタ電極とをそれぞれ接続する接続手段とを具備し、前記第２エミッタ電極下方の前記第１ベース電極および第１エミッタ電極は前記１つの辺に垂直に配置されることにより解決するものである。   Second, a semiconductor substrate is provided with a collector region, a base region, and an emitter region, a first base electrode that contacts the base region, a first emitter electrode that contacts the emitter region, the first base electrode, and the first emitter A semiconductor chip having a second base electrode and a second emitter electrode provided on the electrode via an insulating film; a base terminal and an emitter terminal arranged along one side of the semiconductor chip; and the base terminal And a connecting means for connecting the second base electrode and the emitter terminal to the second emitter electrode, respectively, and the first base electrode and the first emitter electrode below the second emitter electrode are on the one side. This is solved by arranging them vertically.

また、前記第２エミッタ電極下方の第１ベース電極および第１エミッタ電極は並行に複数配置され、該複数の第１ベース電極は端部で束ねられて前記第２ベース電極に接続することを特徴とするものである。   In addition, a plurality of first base electrodes and first emitter electrodes below the second emitter electrode are arranged in parallel, and the plurality of first base electrodes are bundled at an end portion and connected to the second base electrode. It is what.

また、前記接続手段は、前記１つの辺に沿った前記半導体チップの端部付近に固着されることを特徴とするものである。   Further, the connection means is fixed to the vicinity of the end portion of the semiconductor chip along the one side.

また、前記第２エミッタ電極下方の前記第１エミッタ電極は、前記第２エミッタ電極と前記第２ベース電極とが隣接する辺と並行に配置されることを特徴とするものである。   Further, the first emitter electrode below the second emitter electrode is characterized in that the second emitter electrode and the second base electrode are arranged in parallel with adjacent sides.

また、前記第２エミッタ電極は前記第２ベース電極より大きいことを特徴とするものである。   Further, the second emitter electrode is larger than the second base electrode.

本発明によれば以下の効果が得られる。   According to the present invention, the following effects can be obtained.

第１に、２層目の電極を平板状とし、外部端子が配置されるチップ辺に対して垂直方向に、第１エミッタ電極を形成することにより、第１エミッタ電極と第２エミッタ電極の２層の電極によりワイヤボンド位置まで接続でき、チップ端部にワイヤボンドする場合であってもワイヤボンド位置から最も遠い第１エミッタ電極５７までのエミッタ抵抗を低減できる。   First, the second-layer electrode is formed into a flat plate shape, and the first emitter electrode is formed in the direction perpendicular to the chip side where the external terminal is disposed, so that 2 The electrode of the layer can be connected to the wire bond position, and even when wire bonding is performed on the chip end, the emitter resistance to the first emitter electrode 57 farthest from the wire bond position can be reduced.

第２に、チップ端部にワイヤボンドできるので、ボンディングワイヤも短縮化でき、これによってもエミッタ抵抗の低減に寄与できる。   Secondly, since wire bonding can be performed on the chip end portion, the bonding wire can be shortened, which can contribute to reduction of the emitter resistance.

第３に、チップ端部にワイヤボンドできるので、ボンディングワイヤのループを低くでき、薄型パッケージへの実装が図れる。   Third, since wire bonding can be performed on the chip end, the bonding wire loop can be lowered, and mounting on a thin package can be achieved.

図１から図３を参照して本発明の実施の形態をｎｐｎ型のバイポーラトランジスタを例に詳述する。   The embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 by taking an npn bipolar transistor as an example.

図１は本発明の実施形態である半導体装置１０の構造を示す。図１（Ａ）は２層目の電極構造を示す平面図であり、図１（Ｂ）は１層目の電極構造と拡散領域を示す平面図である。   FIG. 1 shows a structure of a semiconductor device 10 according to an embodiment of the present invention. FIG. 1A is a plan view showing a second-layer electrode structure, and FIG. 1B is a plan view showing a first-layer electrode structure and a diffusion region.

本実施形態のｎｐｎ型バイポーラトランジスタ１０は、コレクタ領域２と、ベース領域３と、エミッタ領域４と、第１ベース電極６と、第１エミッタ電極７と、第２ベース電極１６と、第２エミッタ電極１７とから構成される。   The npn-type bipolar transistor 10 of this embodiment includes a collector region 2, a base region 3, an emitter region 4, a first base electrode 6, a first emitter electrode 7, a second base electrode 16, and a second emitter. And the electrode 17.

半導体基板１は、高濃度のｎ＋型半導体基板であり、その上に例えばｎ型エピタキシャル層を成長させるなどしてコレクタ領域２を設ける。   The semiconductor substrate 1 is a high-concentration n + type semiconductor substrate, and a collector region 2 is provided thereon by, for example, growing an n-type epitaxial layer.

ベース領域３は、コレクタ領域２表面に設けられた１つのｐ型拡散領域である。ベース領域３表面には、格子状にｎ＋型不純物を拡散してエミッタ領域４を形成する。これによりベース領域３は図中の正方形状に示す島状に分離される。尚、島状に分離されているのは表面的な構造であり、エミッタ領域４より深く形成されるベース領域３は、深い領域で１つの連続した領域となっている。島状に分割されたベース領域３とその周辺のエミッタ領域４で形成されるセルが多数配置されて動作領域８を構成する。   Base region 3 is one p-type diffusion region provided on the surface of collector region 2. An emitter region 4 is formed on the surface of the base region 3 by diffusing n + -type impurities in a lattice pattern. As a result, the base region 3 is separated into island shapes shown in a square shape in the figure. It is to be noted that the island structure is separated from the surface structure, and the base region 3 formed deeper than the emitter region 4 is one continuous region in a deep region. A large number of cells formed by the base region 3 divided into island shapes and the emitter region 4 around the base region 3 are arranged to constitute the operation region 8.

ベース領域３およびエミッタ領域４に接続するベース電極およびエミッタ電極はそれぞれ２層構造となっている。また、図示は省略するがコレクタ領域２はコレクタ電極に電気的に接続する。   Each of the base electrode and the emitter electrode connected to the base region 3 and the emitter region 4 has a two-layer structure. Although not shown, the collector region 2 is electrically connected to the collector electrode.

図１（Ａ）のごとく、２層目となる第２ベース電極１６および第２エミッタ電極１７は第１ベース電極６および第１エミッタ電極７上に第２の絶縁膜を介してそれぞれ１つづつ設けられる。第２ベース電極１６と第２エミッタ電極１７はそれぞれ平板状で隣接して配置される。第２ベース電極１６の幅は、１本のボンディングワイヤが固着できる面積があれば十分である。第２エミッタ電極１７は、第２ベース電極１６より大きく動作領域８の半分以上を覆って設けられる。   As shown in FIG. 1A, the second base electrode 16 and the second emitter electrode 17 which are the second layer are respectively provided on the first base electrode 6 and the first emitter electrode 7 via the second insulating film. Provided. The second base electrode 16 and the second emitter electrode 17 are flat and adjacent to each other. The width of the second base electrode 16 is sufficient if there is an area where one bonding wire can be fixed. The second emitter electrode 17 is provided so as to be larger than the second base electrode 16 and cover more than half of the operating region 8.

図１（Ｂ）のごとく、第１ベース電極６は２つのパターンからなる。すなわち島状のベース領域３と重畳するような島状のパターンの第１ベース電極６ａと、複数の島状のベース領域３を例えば縦の串で連結し、各串を動作領域８外で束ねてはしご状にしたパターンの第１ベース電極６ｂである。串を束ねた部分は第２ベース電極１６下方まで延在される。   As shown in FIG. 1B, the first base electrode 6 has two patterns. That is, the first base electrode 6 a having an island shape that overlaps the island-shaped base region 3 and a plurality of island-shaped base regions 3 are connected by, for example, vertical skewers, and the skewers are bundled outside the operation region 8. It is the 1st base electrode 6b of the pattern made into the shape of a ladder. The portion where the skewers are bundled extends to the lower side of the second base electrode 16.

第２ベース電極１６下方は島状の第１ベース電極６ａが配置され、第２エミッタ電極１７下方ははしご状の第１ベース電極６ｂが配置される。そして、各第１ベース電極６は、第１の絶縁膜に設けた第１ベースコンタクトホールＢＣ１を介してベース領域３とコンタクトする。   Below the second base electrode 16, an island-shaped first base electrode 6a is disposed, and below the second emitter electrode 17, a ladder-shaped first base electrode 6b is disposed. Each first base electrode 6 is in contact with the base region 3 through a first base contact hole BC1 provided in the first insulating film.

第１エミッタ電極７も２つのパターンからなる。すなわち、はしご状の第１ベース電極６の間に配置される短冊状のパターンの第１エミッタ電極７ａと、島状の第１ベース電極６の間に配置される格子状のパターンの第１エミッタ電極７ｂであり、格子状の第１エミッタ電極７ｂは短冊状の第１エミッタ電極７ａの一部に接続する。そして、各第１エミッタ電極７は、第１の絶縁膜に設けた第１エミッタコンタクトホールＥＣ１を介してエミッタ領域４とコンタクトする。   The first emitter electrode 7 also has two patterns. That is, the strip-shaped first emitter electrode 7 a disposed between the ladder-shaped first base electrodes 6 and the grid-patterned first emitter disposed between the island-shaped first base electrodes 6. The grid-shaped first emitter electrode 7b is connected to a part of the strip-shaped first emitter electrode 7a. Each first emitter electrode 7 is in contact with the emitter region 4 through a first emitter contact hole EC1 provided in the first insulating film.

そして、第１エミッタ電極７ａおよび第１ベース電極６ｂの串の部分は、第２エミッタ電極と第２ベース電極とが隣接する辺と並行に配置される。   The skew portion of the first emitter electrode 7a and the first base electrode 6b is arranged in parallel with the side where the second emitter electrode and the second base electrode are adjacent to each other.

図２（Ａ）は、図１（Ａ）（Ｂ）を重ねた平面図である。また、図２（Ｂ）は図２（Ａ）のＡ−Ａ’線断面図であり、２層目の電極をハッチングで示す。   2A is a plan view in which FIGS. 1A and 1B are overlapped. 2B is a cross-sectional view taken along the line A-A ′ of FIG. 2A, and the second-layer electrode is indicated by hatching.

第２エミッタ電極１７下方では、エミッタ領域４は第１絶縁膜２５に設けた第１エミッタコンタクトホールＥＣ１を介して、第１エミッタ電極７ａに接続し、更に第２絶縁膜２６に設けた第２エミッタコンタクトホールＥＣ２を介して第２エミッタ電極１７に接続する。すなわち、第２エミッタ電極１７下方においては、エミッタ領域４は、第１および第２エミッタコンタクトホールＥＣ１、ＥＣ２を介してほぼダイレクトに、第２エミッタ電極１７に接続する。   Below the second emitter electrode 17, the emitter region 4 is connected to the first emitter electrode 7 a via the first emitter contact hole EC 1 provided in the first insulating film 25, and is further provided in the second insulating film 26. The second emitter electrode 17 is connected via the emitter contact hole EC2. That is, below the second emitter electrode 17, the emitter region 4 is connected to the second emitter electrode 17 almost directly through the first and second emitter contact holes EC1 and EC2.

また、第２エミッタ電極１７下方のベース領域３は、第１ベース電極６ｂと第１ベースコンタクトホールＢＣ１を介してコンタクトし、動作領域８外で束ねられて第２ベース電極側まで延在され、第２ベースコンタクトホールＢＣ２により第２ベース電極１６とコンタクトする。   The base region 3 below the second emitter electrode 17 is in contact with the first base electrode 6b via the first base contact hole BC1, and is bundled outside the operation region 8 and extends to the second base electrode side. The second base electrode 16 is brought into contact with the second base contact hole BC2.

一方第２ベース電極１６下方では、エミッタ領域４は第１エミッタコンタクトホールＥＣ１を介して格子状パターンの第１エミッタ電極７ｂとコンタクトする。そして、その第１エミッタ電極７ｂは短冊状パターンの第１エミッタ電極７ａに接続し、第２エミッタコンタクトホールＥＣ２を介して第２エミッタ電極１７に接続する。   On the other hand, below the second base electrode 16, the emitter region 4 is in contact with the first emitter electrode 7b having a lattice pattern through the first emitter contact hole EC1. The first emitter electrode 7b is connected to the first emitter electrode 7a having a strip pattern, and is connected to the second emitter electrode 17 through the second emitter contact hole EC2.

また、第２ベース電極１６下方のベース領域３は、第１ベースコンタクトホールＢＣ１を介して第１ベース電極６ａとコンタクトし、第１ベース電極６ａは第２ベースコンタクトホールＢＣ２を介して第２ベース電極１６とコンタクトする。すなわち、第２ベース電極１６下方では、ベース領域３は、第２ベース電極１６と、第１および第２のベースコンタクトホールＢＣ１、ＢＣ２を介してほぼダイレクトに接続する。   The base region 3 below the second base electrode 16 is in contact with the first base electrode 6a through the first base contact hole BC1, and the first base electrode 6a is in contact with the second base through the second base contact hole BC2. Contact the electrode 16. That is, below the second base electrode 16, the base region 3 is connected almost directly to the second base electrode 16 via the first and second base contact holes BC1 and BC2.

本実施形態では、第２ベース電極１６はワイヤボンドが圧着できる面積を確保すれば十分とし、第２エミッタ電極１７はできる限りその占有面積を大きくしてエミッタ抵抗の低減に寄与している。   In the present embodiment, it is sufficient if the second base electrode 16 has an area where wire bonds can be crimped, and the second emitter electrode 17 contributes to the reduction of the emitter resistance by increasing the occupied area as much as possible.

また、第２ベース電極１６および第２エミッタ電極１７が平板状であるため、ボンディングワイヤの固着位置の制限が少なく、チップを実装する際の汎用性が高まる。   In addition, since the second base electrode 16 and the second emitter electrode 17 have a flat plate shape, there are few restrictions on the bonding wire fixing position, and versatility when mounting a chip is enhanced.

更に、本実施形態でははしご状の第１ベース電極６ｂが動作領域８外で束ねられる付近にワイヤボンドする場合、ボンディングワイヤの固着位置からほぼ直線的に第１エミッタ電極７が延在する。これによりエミッタ抵抗の低減に寄与できるものであるが、これについて、以下に説明する。   Further, in the present embodiment, when wire bonding is performed in the vicinity where the ladder-shaped first base electrode 6b is bundled outside the operation region 8, the first emitter electrode 7 extends substantially linearly from the bonding wire fixing position. This can contribute to the reduction of the emitter resistance, which will be described below.

図３は上記の半導体素子１０をパッケージに実装する場合を示す。図３（Ａ）は平面図であり、図３（Ｂ）は断面図である。図は一例であり外部端子としてリードを採用しているが、これに限らず、例えばセラミックなどの絶縁性基板に導電パターンを設けたチップサイズパッケージなどでも同様に適用できる。   FIG. 3 shows a case where the semiconductor element 10 is mounted on a package. 3A is a plan view, and FIG. 3B is a cross-sectional view. The figure is an example, and leads are adopted as external terminals. However, the present invention is not limited to this, and the present invention can be similarly applied to, for example, a chip size package in which a conductive pattern is provided on an insulating substrate such as ceramic.

図の如く外部端子２００が、１つのチップ辺（図ではチップ下辺）に沿って複数設けられ、更に、ベース端子およびエミッタ端子が共にその同一辺側の外部端子として導出するように実装する場合には、本実施形態の電極構造が有利となる。   In the case where a plurality of external terminals 200 are provided along one chip side (the lower side of the chip in the figure) as shown in the figure, and the base terminal and the emitter terminal are both led out as external terminals on the same side. The electrode structure of this embodiment is advantageous.

本実施形態では、第１エミッタ電極７ａおよび第１ベース電極６ｂの串の部分は、第２エミッタ電極と第２ベース電極とが隣接する辺と並行に配置されている。すなわち、チップ端部に破線の位置にボンディングワイヤ１５０をワイヤボンドし、第２エミッタ電極１７および第２ベース電極１６と、外部端子２００とをそれぞれ接続することができる。そして図の如くボンディングワイヤを固着する場合、外部端子２００が配置されるチップ１０の１辺に対して垂直に短冊状の第１エミッタ電極７が配置される。つまり第１エミッタ電極７の大部分は、ボンディングワイヤ１５０直下から直線的に延在することになるため、第１エミッタ電極７の取り出し抵抗の増大を防ぐことができる。   In the present embodiment, the skew portion of the first emitter electrode 7a and the first base electrode 6b is arranged in parallel with the side where the second emitter electrode and the second base electrode are adjacent to each other. That is, the bonding wire 150 is wire-bonded to the chip end at the position of the broken line, and the second emitter electrode 17 and the second base electrode 16 can be connected to the external terminal 200, respectively. When the bonding wires are fixed as shown in the figure, the strip-shaped first emitter electrode 7 is disposed perpendicular to one side of the chip 10 on which the external terminal 200 is disposed. That is, most of the first emitter electrode 7 extends linearly from directly below the bonding wire 150, so that an increase in extraction resistance of the first emitter electrode 7 can be prevented.

従ってボンディングワイヤ１５０は必要最小限の長さでよく、広い面積の第２エミッタ電極１７と共にエミッタ抵抗の低減に寄与できる。   Therefore, the bonding wire 150 may be the minimum necessary length, and can contribute to the reduction of the emitter resistance together with the second emitter electrode 17 having a large area.

更に、第１エミッタ電極７の抵抗の増大を防ぐ電極構造でなおかつ図３（Ｂ）のごとく、チップ端部にワイヤボンドすることができ、薄型パッケージに実装することができる。ワイヤボンドにおいては、チップ端部とボンディングワイヤとが接触しないようにループ高さを設定する必要がある。このため具体的には、本実施形態と同一サイズのチップにおいてチップ中央付近にワイヤボンドする場合（破線）では、パッケージの厚みは０．９ｍｍ程度必要になる。しかし、本実施形態によれば、ワイヤボンド位置をチップ端部にすることによりワイヤボンドのループを低くできるので、パッケージ厚を例えば０．７５ｍｍ程度まで薄型化できる。   Furthermore, the electrode structure prevents the resistance of the first emitter electrode 7 from increasing, and as shown in FIG. 3B, wire bonding can be performed on the chip end portion, and the first emitter electrode 7 can be mounted on a thin package. In wire bonding, it is necessary to set the loop height so that the chip end portion does not contact the bonding wire. Therefore, specifically, in the case of wire bonding near the center of the chip (broken line) in a chip of the same size as the present embodiment, the thickness of the package needs to be about 0.9 mm. However, according to this embodiment, since the wire bond loop can be lowered by setting the wire bond position to the chip end, the package thickness can be reduced to, for example, about 0.75 mm.

以上、本実施形態ではｎｐｎ型バイポーラトランジスタについて説明したが、ｐｎｐ型でも同様に実施でき、同様の効果が得られる。

As described above, the npn-type bipolar transistor has been described in the present embodiment. However, the pnp-type transistor can be similarly implemented, and the same effect can be obtained.

本発明を説明するための平面図である。It is a top view for demonstrating this invention. 本発明を説明するための（Ａ）平面図、（Ｂ）断面図である。It is (A) top view and (B) sectional view for explaining the present invention. 本発明を説明するための（Ａ）平面図、（Ｂ）断面図である。It is (A) top view and (B) sectional view for explaining the present invention. 従来技術を説明するための（Ａ）平面図、（Ｂ）平面図、（Ｃ）断面図である。It is (A) top view, (B) top view, and (C) sectional drawing for demonstrating a prior art. 従来技術を説明するための平面図である。It is a top view for demonstrating a prior art.

符号の説明Explanation of symbols

１ 半導体基板
２ コレクタ領域
３ ベース領域
４ エミッタ領域
６ 第１ベース電極
７ 第１エミッタ電極
８ 動作領域
１０ 半導体素子
１６ 第２ベース電極
１７ 第２エミッタ電極
２５ 第１絶縁膜
２６ 第２絶縁膜
５１ 半導体基板
５２ コレクタ領域
５３ ベース領域
５４ エミッタ領域
５６ 第１ベース電極
５７ 第１エミッタ電極
５８ 動作領域
６６ 第２ベース電極
６７ 第２エミッタ電極
１００ 半導体素子
１５０ ボンディングワイヤ
２００ 外部端子
ＢＣ１ 第１ベースコンタクトホール
ＥＣ１ 第１エミッタコンタクトホール
ＢＣ２ 第２ベースコンタクトホール
ＥＣ２ 第２エミッタコンタクトホール
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Collector area | region 3 Base area | region 4 Emitter area | region 6 1st base electrode 7 1st emitter electrode 8 Operation | movement area | region 10 Semiconductor element 16 2nd base electrode 17 2nd emitter electrode 25 1st insulating film 26 2nd insulating film 51 Semiconductor Substrate 52 Collector region 53 Base region 54 Emitter region 56 First base electrode 57 First emitter electrode 58 Operating region 66 Second base electrode 67 Second emitter electrode 100 Semiconductor element 150 Bonding wire 200 External terminal BC1 First base contact hole EC1 First 1 emitter contact hole BC2 2nd base contact hole EC2 2nd emitter contact hole

Claims (6)

コレクタ領域となる一導電型半導体基板と、
前記基板上に設けられた逆導電型のベース領域と、
前記ベース領域表面に格子状に設けられた一導電型のエミッタ領域と、
前記ベース領域とコンタクトする第１ベース電極と、
前記エミッタ領域とコンタクトする第１エミッタ電極と、
前記第１ベース電極および前記第１エミッタ電極上に絶縁膜を介して設けられ前記第１ベース電極と接続する１つの平板状の第２ベース電極と、
前記第１ベース電極および前記第１エミッタ電極上に前記絶縁膜を介して設けられ前記第１エミッタ電極と接続する１つの平板状の第２エミッタ電極とを具備し、
前記第２エミッタ電極下方の第１ベース電極および第１エミッタ電極は並行に複数配置され、該複数の第１ベース電極は端部で束ねられて前記第２ベース電極に接続し、
前記第２エミッタ電極下方の前記第１エミッタ電極は、前記第２エミッタ電極と前記第２ベース電極とが隣接する辺と並行に配置されることを特徴とする半導体装置。 A one-conductivity type semiconductor substrate to be a collector region;
A reverse conductivity type base region provided on the substrate;
An emitter region of one conductivity type provided in a grid pattern on the surface of the base region;
A first base electrode in contact with the base region;
A first emitter electrode in contact with the emitter region;
A flat plate-like second base electrode provided on the first base electrode and the first emitter electrode via an insulating film and connected to the first base electrode;
A flat second emitter electrode provided on the first base electrode and the first emitter electrode via the insulating film and connected to the first emitter electrode;
A plurality of first base electrodes and first emitter electrodes below the second emitter electrode are arranged in parallel, and the plurality of first base electrodes are bundled at an end portion and connected to the second base electrode ,
The semiconductor device according to claim 1, wherein the first emitter electrode below the second emitter electrode is arranged in parallel with a side where the second emitter electrode and the second base electrode are adjacent to each other . 前記第１ベース電極が束ねられる端部付近の第２ベース電極および第２エミッタ電極に、外部端子との接続手段が固着されることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein means for connecting to an external terminal is fixed to the second base electrode and the second emitter electrode in the vicinity of the end where the first base electrode is bundled. 半導体基板にコレクタ領域とベース領域とエミッタ領域を設け、前記ベース領域にコンタクトする第１ベース電極と前記エミッタ領域にコンタクトする第１エミッタ電極と、前記第１ベース電極および第１エミッタ電極上に絶縁膜を介して設けられた第２ベース電極および第２エミッタ電極とを有する半導体チップと、
前記半導体チップの１つの辺に沿って配置されたベース端子およびエミッタ端子と、
前記ベース端子と前記第２ベース電極および前記エミッタ端子と第２エミッタ電極とをそれぞれ接続する接続手段とを具備し、
前記第２エミッタ電極下方の前記第１ベース電極および第１エミッタ電極は前記１つの辺に垂直に配置され、
前記第２エミッタ電極下方の前記第１エミッタ電極は、前記第２エミッタ電極と前記第２ベース電極とが隣接する辺と並行に配置されることを特徴とする半導体装置。 A semiconductor substrate is provided with a collector region, a base region, and an emitter region, a first base electrode that contacts the base region, a first emitter electrode that contacts the emitter region, and insulation on the first base electrode and the first emitter electrode A semiconductor chip having a second base electrode and a second emitter electrode provided via a film;
A base terminal and an emitter terminal arranged along one side of the semiconductor chip;
Connecting means for connecting the base terminal and the second base electrode and the emitter terminal and the second emitter electrode, respectively;
The first base electrode and the first emitter electrode below the second emitter electrode are disposed perpendicular to the one side ,
Wherein the first emitter electrode of the second emitter electrode lower to a semiconductor device and the second emitter electrode and said second base electrode and said Rukoto disposed parallel to the adjacent sides. 前記第２エミッタ電極下方の第１ベース電極および第１エミッタ電極は並行に複数配置され、該複数の第１ベース電極は端部で束ねられて前記第２ベース電極に接続することを特徴とする請求項３に記載の半導体装置。   A plurality of first base electrodes and first emitter electrodes below the second emitter electrode are arranged in parallel, and the plurality of first base electrodes are bundled at an end portion and connected to the second base electrode. The semiconductor device according to claim 3. 前記接続手段は、前記１つの辺に沿った前記半導体チップの端部付近に固着されることを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the connection unit is fixed to the vicinity of an end portion of the semiconductor chip along the one side. 前記第２エミッタ電極は前記第２ベース電極より大きいことを特徴とする請求項１または請求項３に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second emitter electrode is larger than the second base electrode.
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