CN100394613C - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN100394613C CN100394613C CNB2005100041017A CN200510004101A CN100394613C CN 100394613 C CN100394613 C CN 100394613C CN B2005100041017 A CNB2005100041017 A CN B2005100041017A CN 200510004101 A CN200510004101 A CN 200510004101A CN 100394613 C CN100394613 C CN 100394613C
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- emitter electrode
- base electrode
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- 239000004065 semiconductor Substances 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims description 12
- 230000008021 deposition Effects 0.000 abstract 1
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- TVEXGJYMHHTVKP-UHFFFAOYSA-N 6-oxabicyclo[3.2.1]oct-3-en-7-one Chemical compound C1C2C(=O)OC1C=CC2 TVEXGJYMHHTVKP-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Abstract
The invention solves the problem of a bipolar transistor, including an electrode of a first layer and a flat electrode of a second layer, in which assembling flexibility is high because the deposition area of wire bonding is less limited, and displacement in the alignment of mask and isolation distance for obtaining the desired resist pattern can be determined, only by considering the base electrode 6 and emitter electrode of the second layer are provided adjacent only at the one side of the rectangular shape, that reduction in emitter resistance and reduction in thickness of chip cannot be accelerated in according to the arrangement of external terminals. The base electrodes of the first layer are formed as ladder patterns, and the emitter electrode of the first layer is allocated in parallel between the patterns. Moreover, the electrode layer of the second layer is formed as the flat layer, and the parallel emitter electrode and base electrode of the first layer are allocated in parallel to a side adjacent to the electrode of the second layer. Accordingly, the emitter resistance can be reduced, even if the wire bond is deposited to the second electrode adjacent to the end portion, where the base electrode of the first layer is bundled in the form of a ladder, resulting in making contribution to reduction in the thickness of chip.
Description
Technical field
The present invention relates to semiconductor device, particularly relate to the semiconductor device of seeking to reduce emitter resistance.
Background technology
With reference to Fig. 4, be example explanation existing semiconductor devices with the npn transistor npn npn.
Fig. 4 (A) is the synoptic diagram of semiconductor element 100 integral body, and Fig. 4 (B) is the plane graph of ground floor electrode structure, and dotted line shows second layer electrode, and Fig. 4 (C) is the C-C line profile of Fig. 4 (B).
Lamination n type epitaxial loayer etc. for example is provided with collector region 52 on n+ type silicon semiconductor substrate 51.52 surfaces are provided as the base region 53 of p type extrinsic region in the collector region, and clathrate ground spreads n+ type impurity on base region 53 surfaces, forms emitter region 54.Thus, base region 53 is separated by island, and and emitter region 54 alternately dispose.In addition, what be separated into island is the structure on surface, and the base region 53 that forms deeply than emitter region 54 constitutes a continuous zone in darker zone.
Like this, be called as element below the transistor that is formed by the base region 53 that is divided into island and its peripheral emitter region 54, the zone that has disposed a plurality of elements is called as operating space 58.
The base electrode and the emitter electrode that are connected on base region 53 and the emitter region 54 form double-layer structure respectively.
On these first base electrodes 56 and emitter electrode 57, be provided as second base electrode 66 and second emitter electrode 67 of the second layer, and be situated between by the second base stage contact hole (not shown) that on second dielectric film 26, is provided with, the second emitter contact hole EC2 (not shown) connection at this at this.
Like this, second base electrode 66 and second emitter electrode 67 constitute the shape that tabulars cover the ground floor electrodes, by engaging at the enterprising line lead of these second layer electrodes, but can enlarge the zone of wire-bonded, the versatility when improving assembling.In addition, because second base electrode 66 is only adjacent on one side of each rectangle with second emitter electrode 67, so the contraposition deviation of mask or the spacing distance that is used to the resist pattern that obtains stipulating only consider that this part gets final product (reference example such as patent documentation 1).
Patent documentation 1: the spy opens the 2000-40703 communique
Fig. 5 represents to install the state of described semiconductor chip 100.
In assembling procedure,, dispose the two-terminal of base stage B and emitter E in a limit of chip (in the drawings for constituting the limit of chip bottom) side sometimes for example as Fig. 5.At this moment, because outside terminal (for example lead-in wire) will be along limit arranged side by side 200 is connected with second emitter electrode 67 and second base electrode 66, so, then as shown in the figure, can pass through closing line 150 connections if second layer electrode is flat electrode structure.
At this,, it is desirable to reduce emitter resistance for improving the characteristic of bipolar transistor.Therefore, for example guarantee to make the area of second emitter electrode 67 to shorten closing line etc. more greatly or as far as possible.
In addition, especially be accompanied by the slimming of packaging part, and wish to reduce the loop of closing line.At this moment, as shown in the figure, the closing line position is positioned near the chip end, so that contact chip end not, low loop.
But according to the position of the contact hole that connects ground floor, second layer electrode, the part that constitutes current path has two layer segments of first emitter electrode 57 and second emitter electrode 67 and a layer segment of second emitter electrode 67 only.When the wire-bonded position was the chip end, for example in the drawings, the emitter resistance from first emitter electrode 57 of last avris to the wire-bonded position raise.Therefore, the reduction of emitter resistance or the slimming of chip have been hindered.
Summary of the invention
The present invention develops in view of described each problem points, and a first aspect of the present invention provides a kind of semiconductor device, and it comprises: a conductive-type semiconductor substrate, and it is used as the collector region; Contrary conductivity type base region, it is set on the described substrate; One conductivity type emitter region, its by clathrate be arranged on the described base region surface; First base electrode, it contacts with described base region; First emitter electrode, it contacts with described emitter region; Tabular second base electrode, its Jie is set on described first base electrode and described first emitter electrode by dielectric film, and is connected with described first base electrode; Tabular second emitter electrode, its Jie is set on described first base electrode and described first emitter electrode by described dielectric film, and be connected with described first emitter electrode, below described second emitter electrode, described first emitter electrode forms rectangle, this first emitter electrode and first base electrode are provided with a plurality of abreast, and these a plurality of first base electrodes are in the end pack, form scalariform, be connected on described second base electrode, below described second base electrode, described first base electrode forms island, and described first emitter electrode forms clathrate.
In addition, be fixed with the jockey that is connected with outside terminal at described first base electrode on by near second base electrode the end of pack and second emitter electrode.
A second aspect of the present invention provides a kind of semiconductor device, it comprises: semiconductor chip, collector region, base region and emitter region are set on Semiconductor substrate, and it has first base electrode that contacts with described base region, first emitter electrode that contacts with described emitter region, being situated between is arranged on second base electrode, second emitter electrode on described first base electrode and first emitter electrode by dielectric film; Base terminal and emitter terminal, described base terminal and emitter terminal are along a limit configuration of described semiconductor chip; Jockey, it connects described base terminal and described second base electrode and the described emitter terminal and second emitter electrode respectively, wherein, below described second emitter electrode, described first emitter electrode forms rectangle, this first emitter electrode and first base electrode are provided with a plurality of abreast, and described first base electrode and first emitter electrode dispose perpendicular to a described limit, described a plurality of first base electrode is in the end pack, form scalariform, be connected on described second base electrode, below described second base electrode, described first base electrode forms island, and described first emitter electrode forms clathrate.
Described jockey is fixed near the end of the described semiconductor chip on a described limit.
Described first emitter electrode of described second emitter electrode below and the limit of described second emitter electrode and the described second base electrode adjacency dispose abreast.
In addition, described second emitter electrode is bigger than described second base electrode.
According to the present invention, obtain following effect.
The first, by second layer electrode is formed tabular, forming first emitter electrode with respect to the vertical direction in chip limit that disposes outside terminal, can utilize first emitter electrode and the two-layer electrode of second emitter electrode to be connected to the wire-bonded position.That is, even wire-bonded under the situation of chip end, also can reduce from the wire-bonded position emitter resistance to farthest first emitter electrode 57.
The second, but because wire-bonded in the chip end, so closing line can shorten, thus, also can reduce emitter resistance.
The 3rd, but because wire-bonded in the chip end, so can reduce the loop of closing line, realizes the installation to slim packaging part.
Description of drawings
Fig. 1 (A), (B) are plane graphs of the present invention;
Fig. 2 (A) is a plane graph of the present invention, (B) is profile;
Fig. 3 (A) is a plane graph of the present invention, (B) is profile;
Fig. 4 (A) is the plane graph of prior art, (B) is plane graph, (C) is profile;
Fig. 5 is the plane graph of explanation prior art.
Symbol description
1 Semiconductor substrate
2 collector regions
3 base regions
4 emitter regions
6 first base electrodes
7 first emitter electrodes
8 operating spaces
10 semiconductor elements
16 second base electrodes
17 second emitter electrodes
25 first dielectric films
26 second dielectric films
51 Semiconductor substrate
52 collector regions
53 base regions
54 emitter regions
56 first base electrodes
57 first emitter electrodes
58 operating spaces
66 second base electrodes
67 second emitter electrodes
100 semiconductor elements
150 closing lines
200 outside terminals
The BC1 first base stage contact hole
The EC1 first emitter contact hole
The BC2 second base stage contact hole
The EC2 second emitter contact hole
Embodiment
With reference to Fig. 1～Fig. 3, be that example describes embodiments of the invention in detail with npn type bipolar transistor.
Fig. 1 represents the structure as the semiconductor device 10 of the embodiment of the invention.Fig. 1 (A) is the plane graph of expression second layer electrode structure, and Fig. 1 (B) is the plane graph of expression ground floor electrode structure and diffusion zone.
The npn type bipolar transistor 10 of present embodiment is made of collector region 2, base region 3, emitter region 4, first base electrode 6, first emitter electrode 7, second base electrode 16, second emitter electrode 17.
The base electrode and the emitter electrode that connect on base region 3 and emitter region 4 constitute double-layer structure respectively.In addition, though omitted diagram, collector region 2 is connected electrically on the collector electrode.
Shown in Fig. 1 (A), second base electrode 16 and second emitter electrode, 17 Jie that constitute the second layer are arranged on respectively on first base electrode 6 and first emitter electrode 7 one by one by second dielectric film (not shown).Second base electrode 16 and second emitter electrode 17 respectively with tabular in abutting connection with configuration.As long as the width of second base electrode 16 has the area that can fix a closing line (broken circle symbol) just enough.Second emitter electrode, 17 to the second base electrodes 16 are big, its overlap action zone 8 over half.
Shown in Fig. 1 (B), first base electrode 6 is made of two patterns.Promptly, constitute by the first base electrode 6a and the first base electrode 6b, wherein, the first base electrode 6a is and island base region 3 overlapping such island-shaped pattern, the first base electrode 6b for example connects a plurality of island base regions 3 with vertical polyphone, and tandem is respectively gone here and there outside operating space 8, forms the pattern of scalariform.Make the part of string tandem extend to second base electrode, 16 belows.
Second base electrode, 16 belows configuration island, the first base electrode 6a, second emitter electrode, 17 belows configuration scalariform, the first base electrode 6b.And each first base electrode 6 is situated between and is contacted with base region 3 by the first base stage contact hole BC1 that is located on first dielectric film (not shown).
And, the limit configured in parallel of the part of the string of the first emitter electrode 7a and the first base electrode 6b and second emitter electrode and the second base electrode adjacency.
Fig. 2 (A) is the plane graph after making Fig. 1 (A), (B) overlapping.In addition, Fig. 2 (B) is the A-A line profile of Fig. 2 (A), and the electrode of the second layer is represented by hacures.
Below second emitter electrode 17, emitter region 4 is situated between and is connected on the first emitter electrode 7a by the first emitter contact hole EC1 that is arranged on first dielectric film 25, and further Jie is connected on second emitter electrode 17 by the second emitter contact hole EC2 that is arranged on second dielectric film 26.That is, below second emitter electrode 17, emitter region 4 is situated between and is directly connected to basically on second emitter electrode 17 by first and second emitter contact hole EC1, EC2.
In addition, the base region 3 of second emitter electrode, 17 belows is situated between and is contacted with the first base electrode 6b by the first base stage contact hole BC1, outside operating space 8,, extend to the second base electrode side, contact with second base electrode 16 by the second base stage contact hole BC2 by tandem.
On the other hand, below second base electrode 16, emitter region 4 Jie are contacted by the first emitter electrode 7b of the first emitter contact hole EC1 and clathrate pattern.And this first emitter electrode 7b is connected with the first emitter electrode 7a of rectangle pattern, and Jie is connected with second emitter electrode 17 by the second emitter contact hole EC2.
In addition, the base region 3 of second base electrode, 16 belows is situated between and is contacted with the first base electrode 6a by the first base stage contact hole BC1, and the first base electrode 6a is situated between and is contacted with second base electrode 16 by the second base stage contact hole BC2.That is, below second base electrode 16, base region 3 is situated between and directly is connected with second base electrode 16 basically by first and second base stage contact hole BC1, BC2.
In the present embodiment, as long as second base electrode 16 guarantees that but the area of wire-bonded crimping is just enough, second emitter electrode 17 increases its occupied area as far as possible, to reduce emitter resistance.
In addition, because second base electrode 16 and second emitter electrode 17 are tabular,, improved the versatility when chip is installed so the restriction of the fixed position of closing line reduces.
In addition, in the present embodiment, when the first base electrode 6b of scalariform carried out wire-bonded near by tandem outside operating space 8, the first emitter electrode 7a roughly extended on linearity ground from the fixed position of closing line.Thus, can reduce emitter resistance, below be described.
Fig. 3 is illustrated on the packaging part situation when described semiconductor element 10 is installed.Fig. 3 (A) is a plane graph, and Fig. 3 (B) is a profile.Among the figure, as an example, adopt lead-in wire as outside terminal, but be not limited thereto, the chip size packages etc. that conductive pattern for example is set on insulating properties substrates such as pottery can be suitable for too.
As shown in the figure, (among the figure for chip bottom) is provided with a plurality of outside terminals 200 along a chip limit, in addition, base terminal B and emitter terminal E is being installed, and when making it all as the outside terminal derivation of this same avris, is favourable to the electrode structure of present embodiment.
In the present embodiment, the part of the string of the first emitter electrode 7a and the first base electrode 6b and the parallel configuration in the limit of second emitter electrode 17 and second base electrode, 16 adjacency.That is, can at dotted line position wire-bonded closing line 150, can connect second emitter electrode 17 and second base electrode 16 and outside terminal 200 respectively in the chip end.And, as shown in the figure, when fixed engagement line 150, vertically dispose the rectangle first emitter electrode 7a with respect to a limit of the chip 10 of configuring external terminal 200.That is, the major part of first emitter electrode 7 straight-line extension under the closing line 150 increases so can prevent the taking-up resistance of first emitter electrode 7.
Therefore, closing line 150 is as long as for necessary Min. length, can reduce emitter resistance together with large-area second emitter electrode 17.
In addition, can constitute the electrode structure of the resistance increase that prevents first emitter electrode 7, and, shown in Fig. 3 (B), can carry out wire-bonded in the chip end, can be installed in the slim packaging part.In wire-bonded, must set the loop height so that the chip end do not contact with closing line 150.Therefore, specifically, with the chip of present embodiment same size in, when carrying out wire-bonded near chip central authorities (dotted line), the thickness of packaging part is necessary for about 0.9mm.But, according to present embodiment, owing to can be positioned at the loop that the chip end reduces wire-bonded by making the wire-bonded position, so the thickness of packaging part can be reduced to for example 0.75mm.
More than, in the present embodiment, npn type bipolar transistor has been described, but also can have implemented equally the pnp type, obtain identical effect.
Claims (6)
1. a semiconductor device is characterized in that, comprising: a conductive-type semiconductor substrate, and it constitutes the collector region; Contrary conductivity type base region, it is set on the described substrate; One conductivity type emitter region, its by clathrate be arranged on the described base region surface; First base electrode, it contacts with described base region; First emitter electrode, it contacts with described emitter region; Tabular second base electrode, its Jie is set on described first base electrode and described first emitter electrode by dielectric film, and is connected with described first base electrode; Tabular second emitter electrode, its Jie is set on described first base electrode and described first emitter electrode by described dielectric film, and be connected with described first emitter electrode, below described second emitter electrode, described first emitter electrode forms rectangle, this first emitter electrode and first base electrode are provided with a plurality of abreast, and these a plurality of first base electrodes are in the end pack, form scalariform, be connected on described second base electrode, below described second base electrode, described first base electrode forms island, and described first emitter electrode forms clathrate.
2. semiconductor device as claimed in claim 1 is characterized in that, is fixed with the jockey that is connected with outside terminal at described first base electrode on by near second base electrode the end of pack and second emitter electrode.
3. semiconductor device, it is characterized in that, comprise: semiconductor chip, collector region, base region and emitter region are set on Semiconductor substrate, have first base electrode that contacts with described base region, first emitter electrode that contacts with described emitter region, being situated between is arranged on second base electrode, second emitter electrode on described first base electrode and first emitter electrode by dielectric film; Base terminal and emitter terminal, described base terminal and emitter terminal are along a limit configuration of described semiconductor chip; Jockey, it connects described base terminal and described second base electrode and the described emitter terminal and second emitter electrode respectively, wherein, below described second emitter electrode, described first emitter electrode forms rectangle, this first emitter electrode and first base electrode are provided with a plurality of abreast, and described first base electrode and first emitter electrode dispose perpendicular to a described limit, described a plurality of first base electrode is in the end pack, form scalariform, be connected on described second base electrode, below described second base electrode, described first base electrode forms island, and described first emitter electrode forms clathrate.
4. semiconductor device as claimed in claim 3 is characterized in that, described jockey is fixed near the end of described semiconductor chip along a described limit.
5. as claim 1 or 3 described semiconductor devices, it is characterized in that described first emitter electrode of described second emitter electrode below and the limit of described second emitter electrode and the described second base electrode adjacency dispose abreast.
6. as claim 1 or 3 described semiconductor devices, it is characterized in that described second emitter electrode is bigger than described second base electrode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP094688/2004 | 2004-03-29 | ||
| JP2004094688A JP4308060B2 (en) | 2004-03-29 | 2004-03-29 | Semiconductor device |
| JP094688/04 | 2004-03-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1677688A CN1677688A (en) | 2005-10-05 |
| CN100394613C true CN100394613C (en) | 2008-06-11 |
Family
ID=35050089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100041017A Expired - Fee Related CN100394613C (en) | 2004-03-29 | 2005-01-06 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4308060B2 (en) |
| KR (1) | KR100616050B1 (en) |
| CN (1) | CN100394613C (en) |
| TW (1) | TWI252585B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5341435B2 (en) * | 2008-08-26 | 2013-11-13 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| JP2010080925A (en) | 2008-08-26 | 2010-04-08 | Sanyo Electric Co Ltd | Semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4024568A (en) * | 1974-09-27 | 1977-05-17 | Hitachi, Ltd. | Transistor with base/emitter encirclement configuration |
| JPH11283990A (en) * | 1998-03-30 | 1999-10-15 | Ntt Electornics Corp | Semiconductor device |
| JP2000040703A (en) * | 1998-07-24 | 2000-02-08 | Sanyo Electric Co Ltd | Electrode structure of transistor |
| JP2001267329A (en) * | 2000-03-17 | 2001-09-28 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2003069015A (en) * | 2001-08-22 | 2003-03-07 | Sanyo Electric Co Ltd | Semiconductor device |
-
2004
- 2004-03-29 JP JP2004094688A patent/JP4308060B2/en not_active Expired - Fee Related
- 2004-11-10 TW TW093134244A patent/TWI252585B/en not_active IP Right Cessation
-
2005
- 2005-01-06 CN CNB2005100041017A patent/CN100394613C/en not_active Expired - Fee Related
- 2005-02-21 KR KR1020050014153A patent/KR100616050B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4024568A (en) * | 1974-09-27 | 1977-05-17 | Hitachi, Ltd. | Transistor with base/emitter encirclement configuration |
| JPH11283990A (en) * | 1998-03-30 | 1999-10-15 | Ntt Electornics Corp | Semiconductor device |
| JP2000040703A (en) * | 1998-07-24 | 2000-02-08 | Sanyo Electric Co Ltd | Electrode structure of transistor |
| JP2001267329A (en) * | 2000-03-17 | 2001-09-28 | Sanyo Electric Co Ltd | Semiconductor device |
| JP2003069015A (en) * | 2001-08-22 | 2003-03-07 | Sanyo Electric Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005285912A (en) | 2005-10-13 |
| JP4308060B2 (en) | 2009-08-05 |
| TW200532913A (en) | 2005-10-01 |
| CN1677688A (en) | 2005-10-05 |
| KR20060043030A (en) | 2006-05-15 |
| KR100616050B1 (en) | 2006-08-28 |
| TWI252585B (en) | 2006-04-01 |
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