JP4797445B2 - Insulated gate bipolar transistor - Google Patents

Description

  The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT).

  Conventionally, as one of the IGBTs, there is an IGBT having a structure in which a reverse conducting diode is incorporated in order to improve a reverse surge withstand capability. FIG. 19 shows a cross-sectional view of the IGBT having such a structure, and FIG. 20 shows an electric circuit diagram of the IGBT having such a structure.

The IGBT shown in FIG. 19 includes a P ⁺ type layer 11, an N ⁻ type drift layer 12 formed on the P ⁺ type layer 11, a P type base region 13 joined to the N ⁻ type drift layer 12, A semiconductor substrate 1 having an N ⁺ type emitter region 14 formed on the inner surface side of a P type base region 13 is provided.

Then, on the surface of the semiconductor substrate 1, the surface side portion of the P-type base region 13 located between the N ⁻ -type drift layer 12 and the N ⁺ -type emitter region 14 is used as a channel region, and a gate is formed on the channel region. A gate electrode 16 is formed via the insulating film 15.

An emitter electrode 18 is formed on the surface of the semiconductor substrate 1 via an interlayer insulating film 17. The emitter electrode 18 is electrically connected to the P-type base region 13 and the N ⁺ -type emitter region 14 through a contact hole formed in the interlayer insulating film 17.

A collector electrode 21 is formed on the back side of the semiconductor substrate 1. The collector electrode 21 is electrically connected to the P ⁺ type layer 11. In the semiconductor substrate 1, a P-type base region 13, an N ⁺ -type emitter region 14, a gate insulating film 15, a gate electrode 16 and the like are formed, and a region functioning as an IGBT element is the element region 2.

Further, in the semiconductor substrate 1, in the peripheral region 3 located on the outer periphery of the element region 2, N ^- on the inner surface side of the type drift layer 12, spaced apart from the P-type base region 13, N ^- -type drift layer 12 Also, an N ⁺ type layer 20 having a high impurity concentration is formed. This becomes the cathode of the reverse conducting diode 22 described later.

A reverse conducting electrode 19 is formed on the surface of the N ⁺ type layer 20. The N ⁺ type layer 20 is electrically connected to the reverse conducting electrode 19, and is electrically connected to the collector electrode 21 through the reverse conducting electrode 19.

Thus, the ^{N +} -type layer 20 N ^- provided -type drift layer 12, ^{N +} -type layer 20 that is electrically connected to the collector electrode 21, as shown in FIG. 20, N ^- -type drift layer 12 The cathode of the PN junction diode (reverse conducting diode) 22 composed of the P-type base region 13 is connected to the collector electrode 21 and the anode is connected to the emitter electrode 18 (see, for example, Patent Document 1) ).
Japanese Patent No. 2959127

  However, for example, when the power supply voltage is erroneously connected in the reverse direction to the IGBT having the above structure, a large current flows between the emitter and the collector.

  For this reason, for example, when the wire wiring connected to the reverse conducting diode 22, the IGBT package, or the like cannot withstand the large current, or the electronic device using the IGBT cannot withstand the large current. In some cases, there is a problem that the IGBT and the electronic device that employs the IGBT are destroyed.

  On the other hand, when the wire wiring connected to the reverse conducting diode is made thick so as to withstand a large current, it is necessary to provide a large bonding pad on the IGBT element, which causes a problem that the element size becomes large.

  In view of the above points, the present invention has an object to provide an IGBT capable of reducing the amount of current flowing between an emitter and a collector when a power supply voltage is erroneously connected to the IGBT in the reverse direction, and a method for manufacturing the IGBT. To do.

In order to achieve the above object, according to the first aspect of the present invention, the second semiconductor layer (12) includes the fifth semiconductor layer (20) formed on the inner surface side of the second semiconductor layer (12). In the IGBT having a built-in reverse conducting diode composed of the first semiconductor layer and the third semiconductor layer (13), an electrical connection is made between the fifth semiconductor layer (20) and the second electrode (21). It is characterized by comprising a resistor (34) connected to.

  Thereby, when the power supply voltage is erroneously connected to the IGBT in the reverse direction, the amount of current flowing between the emitter and the collector can be reduced as compared with the conventional IGBT.

Here, as the resistor, for example, a resistor that is configured separately from the semiconductor substrate on which the IGBT element is formed, that is, a resistor that is externally attached to the IGBT, or the invention according to claim 2 is used. It is possible to use a resistance element (34) formed on the same semiconductor substrate (1) as the semiconductor substrate (1) on which the IGBT element is formed, that is, a built-in element in the IGBT.

  In addition, in the case where an externally attached resistor is used as the resistor, a material for forming the resistor is required separately from the IGBT, or the IGBT and the resistor are separated from the IGBT manufacturing process. A process of connecting the two is necessary.

On the other hand, when a resistor element formed on a semiconductor substrate is used as a resistor as in the invention described in claim 2, the formation of the resistor element and the resistor element are performed within the manufacturing process of the IGBT. Connection to the IGBT element becomes possible.

  Thus, according to the present invention, there is no need to separately prepare a material for forming the resistance element separately from the formation of the IGBT, so that the resistance element is compared with the case where a resistor externally attached to the IGBT is used. It is possible to reduce the material required for forming the resistor and to omit the connecting step between the resistance element and the IGBT.

Specifically, as the resistive element, for example, a diffused resistor is used, or the resistive element is formed on the surface of the semiconductor substrate (1) via the insulating film (36) as in the invention described in claim 3. A resistive element (34) can be used. For example, a so-called poly resistor made of polysilicon can be used.

Further, for example, when the power supply voltage is 10 V and the current flowing between the emitter and the collector is to be 1 A or less, the resistance value of the resistance element (34) is set to 10Ω as in the invention according to claim 4. It is preferable to set it to 1 MΩ or less.

In the invention according to claim 5, it is formed on the surface of the semiconductor substrate (1), electrically connected to the fifth semiconductor layer (20), and one end side of the resistance element (34) ( 34a) is electrically connected to the third electrode (19) and is formed on the surface of the semiconductor substrate (1), and is electrically connected to the other end side (34b) of the resistance element (34). The fourth electrode (35) is provided, and the third electrode (19) and the fourth electrode (35) have a laminated structure.

  Thereby, compared with the case where the third electrode and the fourth electrode are not stacked, the third electrode on the semiconductor substrate and the region where the fourth pole is formed can be reduced, and the chip area of the IGBT is reduced. it can. The third electrode can be stacked on the fourth electrode, or the fourth electrode can be stacked on the third electrode.

In the invention described in claim 6 , the resistor element (34) is connected in series between the first electrode (18) and the second electrode (21), and at least the cathode is the first electrode (18). And a bidirectional Zener diode (51) whose anode is electrically connected to the second electrode (21).

  Thereby, compared with the case where this diode is not provided, the reverse surge withstand capability of the IGBT between the first electrode and the second electrode can be improved.

Further, in the invention described in claim 7 , between the first electrode (18) and the second electrode (21), the resistor element (34) is connected in parallel, and at least the cathode is the first electrode (18). And a bidirectional Zener diode (51) whose anode is electrically connected to the second electrode (21).

  Even in this case, the reverse surge withstand capability of the IGBT between the first electrode and the second electrode can be improved as compared with the case where the diode is not provided.

  Furthermore, according to the present invention, the voltage applied to the resistance element can be a constant voltage, and the current flowing through the resistance element can be reduced to a predetermined magnitude or less. That is, according to the present invention, the resistance element can be protected.

In the invention according to claim 8, in the method of manufacturing an insulated gate bipolar transistor, in the step of forming the gate electrode (16), simultaneously with the formation of the gate electrode (16), on the insulating film (36), A resistance element (34) electrically connected between the fifth semiconductor layer (20) and the second electrode (21) is formed.

  For example, when the resistance element is made of polysilicon, it can be formed simultaneously with the gate electrode. Thereby, the manufacturing process can be reduced in a process different from the gate electrode as compared with the manufacturing method of forming the resistance element.

  Note that each means described in the claims and the reference numerals in parentheses of each means described above are an example showing a correspondence relationship with specific means described in the embodiment described later.

(First embodiment)
In FIG. 1, the top view of IGBT in 1st Embodiment of this invention is shown. 2 is a sectional view taken along line AA in FIG. 1, and FIG. 3 is an electric circuit diagram of the IGBT in FIGS. 1 to 3, the same components as those of the IGBT shown in FIGS. 19 and 20 are denoted by the same reference numerals as those in FIGS. 19 and 20. In FIG. 2, only a part of the element region 2 is shown.

  The IGBT of this embodiment includes a reverse conducting diode 22 as in the conventional IGBT shown in FIG.

Specifically, as shown in FIG. 2, the semiconductor substrate 1 includes a P ⁺ type layer 11, an N ⁺ type layer 31 formed on the P ⁺ type layer 11, and an N ⁺ type layer 31. And an N ⁻ type drift layer 12 formed. Note that the N ⁺ -type layer 31 may be omitted.

The semiconductor substrate 1 has an element region 2 and an outer peripheral region 3, and an IGBT element is formed in the element region 2. That is, in the element region 2, a plurality of P-type base region 13 is spaced apart from each other, N ^- an internal type drift layer 12, N ^- on the surface of the type drift layer 12, N ^- the type drift layer 12 The PN junction is formed to terminate. Further, the N ⁺ -type emitter region 14 is formed inside the P-type base region 13 and on the surface of the P-type base region 13 so that the PN junction with the P-type base region 13 terminates.

  In the element region 2, a gate electrode 16 is formed on the surface of the semiconductor substrate 1 via a gate insulating film 15. An emitter electrode 18 is formed on the gate electrode 16 via an interlayer insulating film 17. Is formed.

  As shown in FIG. 1, the emitter electrode 18 has, for example, a substantially square shape in the planar layout of the semiconductor substrate 1. An emitter bonding pad 32 is provided on a part of the emitter electrode 18, and a gate electrode bonding pad 33 is disposed adjacent to the emitter electrode 18.

On the other hand, in the outer peripheral region 3 of the semiconductor substrate 1, as shown in FIG. 2, an N ⁺ type layer 20 serving as a cathode of the reverse conducting diode 22 is formed inside the N ⁻ type drift layer 12. The N ⁺ -type layer 20 is electrically connected to the collector electrode 21 through a polysilicon resistor 34 and first and second reverse conducting electrodes 19 and 35 described later.

In this way, the reverse conducting diode 22 constituted by the N ⁻ type drift layer 12 and the P type base region 13 is electrically connected between the emitter electrode 18 and the collector electrode 21 of the IGBT.

As for the correspondence relationship between the present embodiment and the present invention, the P type corresponds to the first conductivity type, and the N type corresponds to the second conductivity type. The P ⁺ type layer 11 corresponds to the first semiconductor layer, the N ⁻ type drift layer 12 corresponds to the second semiconductor layer, the P type base region 13 corresponds to the third semiconductor layer, and the N ⁺ type emitter region. 14 corresponds to the fourth semiconductor layer, and the N ⁺ -type layer 20 corresponds to the fifth semiconductor layer. The emitter electrode 18 corresponds to the first electrode, and the collector electrode 21 corresponds to the second electrode.

  And unlike the conventional IGBT shown in FIG. 19, the IGBT of this embodiment incorporates a limiting resistor 34 connected in series to the reverse conducting diode 22 as shown in FIGS. This limiting resistor 34 limits the current flowing through the reverse conducting diode.

  Specifically, as shown in FIG. 2, in the outer peripheral region 3, a polysilicon resistor (a limiting resistor) made of polysilicon via an insulating film 36 such as a silicon oxide film on the surface of the semiconductor substrate 1. 34 is formed. FIG. 1 shows only the positional relationship between the polysilicon resistor 34 and the first reverse conducting electrode 19 and the second reverse conducting electrode 35 described later in a direction parallel to the surface of the semiconductor substrate 1. This polysilicon resistor 34 corresponds to a resistor or a resistance element of the present invention.

  The polysilicon resistor 34 has, for example, a strip pattern as shown in FIGS. 1 and 2 and is formed in a part of the outer peripheral region 3 (left corner in the figure). The shape and position of the polysilicon resistor 34 can be arbitrarily changed.

  The resistance value of the polysilicon resistor 34 can be arbitrarily changed according to the allowable amount of current flowing between the emitter and the collector. For example, when the power supply voltage is 10 V and the current flowing through the reverse conducting diode 22 is desired to be 1 A or less, the resistance value of the polysilicon resistor 34 is preferably set to 10 Ω or more and 1 MΩ or less. Therefore, the pattern width, length, thickness, impurity concentration, etc. of the polysilicon resistor 34 are set so as to obtain such a desired resistance value.

  As shown in FIG. 2, the first reverse conducting electrode 19 and the second reverse conducting electrode 35 are formed on the polysilicon resistor 34 via the interlayer insulating film 37 so as to be separated from each other. The first reverse conducting electrode 19, the second reverse conducting electrode 35, and the emitter electrode 18 are made of, for example, Al metal. One end 34 a of both ends 34 a and 34 b of the polysilicon resistor 34 is electrically connected to the first reverse conducting electrode 19, and the other end 34 b is electrically connected to the second reverse conducting electrode 35. .

As shown in FIG. 2, the first reverse conducting electrode 19 is also electrically connected to the N ⁺ type layer 20. Further, as shown in FIG. 1, the first reverse conducting electrode 19 is arranged around the emitter electrode 18 in, for example, a rectangular frame shape.

  On the other hand, a bonding pad (not shown) is provided on the second reverse conducting electrode 35, and the second reverse conducting electrode 35 is electrically connected to the collector electrode 21 through the bonding pad as shown in FIG. It is connected to the.

Thus, in the present embodiment, the polysilicon resistor 34 is electrically connected between the N ⁺ type layer 20 and the collector electrode 21.

In the outer peripheral region 3, a P-type region 38 having a depth from the substrate surface larger than that of the P-type base region 13 is formed on the inner surface side of the N ⁻ -type drift layer 12 and in the vicinity of the element region 2. ing. By this P-type region 38, the withstand voltage of the reverse conducting diode 22 is improved as compared with the case where the P-type region 38 is not provided. In the present embodiment, the P-type region 38 and the N ⁻ -type drift layer 12 also constitute the reverse conducting diode 22. The P-type region 38 can be omitted.

  Next, a method for manufacturing the IGBT having the above structure will be described. 4 to 8 show the manufacturing process of this IGBT. 4 to 8 correspond to FIG. A known manufacturing method can be used as a manufacturing method of the IGBT element itself, and the manufacturing method of this embodiment mainly includes a step of forming the polysilicon resistor 34 and the like. Is different.

First, as shown in FIGS. 4A to 4C, a step of preparing the semiconductor substrate 1 is performed. That is, as shown in FIG. 4A, a substrate made of a P ⁺ type layer 11 is prepared, and as shown in FIG. 4B, an N ⁺ type layer 31 is formed on the surface of the P ⁺ type layer 11. Then, as shown in FIG. 4C, the N ⁻ type drift layer 12 is formed on the surface of the N ⁺ type layer 31.

Subsequently, as shown in FIG. 5A, a P-type region 38 is formed on the inner surface side of the N ⁻ -type drift layer 12 by an ion implantation method.

  Subsequently, as shown in FIG. 5B, the gate insulating film 15 is formed on the formation region of the element region 2 on the surface of the semiconductor substrate 1, and on the formation region of the outer peripheral region 3. Then, an insulating film 36 is formed.

At this time, the gate insulating film 15 is formed at least on the channel formation scheduled region, and the insulating film 36 is formed at least in a region different from the channel formation scheduled region. The insulating film 36 is thicker than the gate insulating film 15 and is formed by, for example, the LOCOS method. Further, in the insulating film 36, the portion 36a located on the region where the N ⁺ -type layer 20 is to be formed is made thinner than the other portions.

  Subsequently, as shown in FIG. 6A, after forming a polysilicon film on the surface of the semiconductor substrate 1, patterning is performed, and further, impurities are introduced into the patterned polysilicon, whereby the element region 2 is formed. In the planned formation region, the gate electrode 16 is formed on the gate insulating film 15, and in the planned formation region of the outer peripheral region 3, the polysilicon resistor 34 is formed on the insulating film 36.

Subsequently, as shown in FIG. 6B, the P-type base region is formed on the inner surface side of the N ⁻ -type drift layer 12 in the region where the element region 2 is to be formed by ion implantation using the gate electrode 16 as a mask. 13 is formed.

Subsequently, as shown in FIG. 7A, in the region where the element region 2 is to be formed, an N ⁺ -type emitter region 14 is formed on the inner surface side of the P-type base region 13 and the outer peripheral region is formed by ion implantation. 3, the N ⁺ -type layer 20 is formed below the thin portion 36 a of the insulating film 36.

Subsequently, as shown in FIG. 7B, the interlayer insulating film 17 made of BPSG or the like is formed on the surface of the gate electrode 16, and the surface of the polysilicon resistor 34 is made of BPSG or the like. An interlayer insulating film 37 is formed. Further, holes are formed in the interlayer insulating film 37 on the upper portion of the N ⁺ -type layer 20 and on both ends of the polysilicon resistor 34.

Subsequently, as shown in FIG. 8A, an Al metal film is formed on the surface of the semiconductor substrate 1 and patterned to be connected to the P-type base region 13 and the N ⁺ -type emitter region 14. The emitter electrode 18, the first reverse conducting electrode 19 connected to the N ⁺ -type layer 20 and one end 34 a of the polysilicon resistor 34, and the second reverse conducting electrode 35 connected to the other end 34 b of the polysilicon resistor 34. Form at the same time.

  Thereafter, as shown in FIG. 8B, a collector electrode 21 is formed on the back surface side of the semiconductor substrate 1. Through these steps, the IGBT shown in FIG. 2 can be manufactured.

  Next, main features of the present embodiment will be described.

(1) In this embodiment, as shown in FIG. 2, a polysilicon resistor 34 is electrically connected between the N ⁺ -type layer 20 and the collector electrode 21. That is, as shown in FIG. 3, the reverse conducting diode 22 and the polysilicon resistor 34 are connected in series between the emitter electrode 18 and the collector electrode 21.

  Thereby, when the power supply voltage is erroneously connected to the IGBT in the reverse direction, the amount of current flowing between the emitter and the collector can be reduced as compared with the conventional IGBT as shown in FIG.

  As a result, in the conventional IGBT as shown in FIG. 19, only a part of applications (electronic devices) that can withstand a large current can be applied. However, according to the present embodiment, the applicable applications can be expanded.

  Further, the wire diameter of the wire wiring connected to the reverse conducting diode can be made smaller than that of the conventional IGBT as shown in FIG. 19, and the bonding pad provided on the IGBT element can be made smaller. Therefore, the chip size can be reduced as compared with the conventional IGBT as shown in FIG.

  (2) In the present embodiment, the polysilicon resistor 34 is formed on the surface of the semiconductor substrate 1 on which the IGBT element is formed. That is, in this embodiment, a resistor connected in series to the reverse conducting diode 22 is built in the IGBT.

  By the way, as described in other embodiments to be described later, as a resistor, a resistor separate from the semiconductor substrate 1 on which the IGBT element is formed is used, and this resistor is externally attached to the IGBT. You can also. However, in the case of external attachment, a material for forming a resistor is required separately from the IGBT element. In addition to the manufacturing process of the IGBT element, a process for connecting the IGBT element and the resistor is required.

On the other hand, by forming the resistor in the IGBT as in the present embodiment, the polysilicon resistor 34 and the polysilicon resistor 34 and the N ⁺ type layer 20 are formed within the manufacturing process of the IGBT element. Can be connected. Therefore, it is not necessary to separately prepare a material necessary for forming the polysilicon resistor 34 as compared with the case of external attachment. Therefore, the material necessary for forming the resistor can be reduced, and the polysilicon resistor 34 and the IGBT can be reduced. The connection step with the element can be omitted.

In particular, in the present embodiment, the polysilicon resistor 34 is formed simultaneously with the formation of the IGBT gate electrode 16 in the step shown in FIG. Further, in the step shown in FIG. 8A, the first reverse conducting electrode 19 for connecting the polysilicon resistor 34 and the N ⁺ type layer 20 and the polysilicon resistor 34 are electrically connected to the collector electrode 21. Therefore, the second reverse conducting electrode 35 is formed simultaneously with the emitter electrode 18.

  Thereby, compared with the case where the gate electrode 16 and the polysilicon resistor 34 are formed separately, or the case where the first and second reverse conducting electrodes 19 and 35 and the emitter electrode 18 are separately formed, The number can be reduced.

(Second Embodiment)
9 and 10 are plan views of IGBTs in the first and second examples of the second embodiment of the present invention. 9 and 10 correspond to FIG. 1. In FIGS. 9 and 10, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1.

  In the first embodiment, as shown in FIG. 1, the case where the polysilicon resistor 34 is disposed only in one of the four corners has been described as an example. However, as illustrated in FIG. 9, each of the four corners is disposed. A polysilicon resistor 34 can also be disposed.

  For example, when four polysilicon resistors 34 are arranged in the outer peripheral region 3 and one bonding pad 41 is provided for electrically connecting the second reverse conducting electrode 35 and the collector electrode 21, the second reverse conducting electrode 35 is provided. Are arranged in a substantially rectangular frame shape on the outer periphery of the first reverse conducting electrode 19 so that the other ends 34b of the four polysilicon resistors 34 are electrically connected to one bonding pad 41 by the lead-out wiring 35a. Further, one end 34 a of the four polysilicon resistors 34 is electrically connected to the first reverse conducting electrode 19.

  Thus, by setting the number of the polysilicon resistors 34 to four, it is possible to disperse the heat generated during the resistance conduction, and the heat generation of the polysilicon resistors 34 compared to the case where the number of the polysilicon resistors 34 is one. The amount can be reduced. The number of polysilicon resistors 34 is not limited to four, and can be changed to an arbitrary number.

  As shown in FIG. 10, the number of bonding pads 41 can be changed to the same four as the polysilicon resistors 34 with respect to the IGBT shown in FIG. 9. Thus, by increasing the number of bonding pads 41, it is possible to omit lead wires 35a (see FIG. 9) for connecting the other ends 34b of the polysilicon resistors 34 to each other. As a result, the chip size can be reduced as compared with the IGBT shown in FIG.

  The number of bonding pads 41 can be arbitrarily changed. However, it is preferable that the number of bonding pads 41 is the same as the number of polysilicon resistors 34 from the viewpoint of omitting the lead wirings 35a.

(Third embodiment)
In FIG. 11, the top view of IGBT in 3rd Embodiment of this invention is shown. 12 is a cross-sectional view taken along line BB in FIG. 11, and FIG. 13 is an electric circuit diagram of the IGBT in FIGS. In addition, in FIGS. 11-13, the code | symbol same as FIGS. 1-3 is attached | subjected to the component similar to IGBT shown in FIGS. 1-3.

This embodiment is an example in which a first bidirectional Zener diode 42 electrically connected between the gate electrode 16 and the N ⁺ type layer 20 is added to the IGBT shown in FIGS.

  As shown in FIG. 11, the first bidirectional Zener diode 42 is disposed, for example, between the gate electrode bonding pad 33 and the first reverse conducting electrode 19 in the outer peripheral region 3 of the semiconductor substrate 1. .

  As shown in FIG. 12, the first bidirectional Zener diode 42 is made of, for example, polysilicon, and is formed on the insulating film 36. On the first bidirectional Zener diode 42, the gate lead-out wiring 43 and the first reverse conducting electrode 19 are formed apart from each other via the interlayer insulating film 37.

One end 42 a of the first bidirectional Zener diode 42 is electrically connected to the gate lead-out wiring 43, and the other end 42 b is directly connected to the N ⁺ via the first reverse conducting electrode 19. The mold layer 20 is electrically connected.

  Thus, in the present embodiment, as shown in FIG. 13, the first bidirectional Zener diode 42 is electrically connected between the collector electrode 21 and the gate electrode 16. Thereby, the collector voltage can be clamped by the breakdown voltage of the Zener diode.

  Therefore, in the IGBT described in the first embodiment, the breakdown voltage of the IGBT is determined by the depth of the P-type base region 13, whereas according to the present embodiment, the breakdown voltage of the IGBT is adjusted by this Zener diode. be able to. Further, it is possible to avoid the latch-up that is caused by the overvoltage applied to the collector electrode 21 as a trigger.

  In the present embodiment, the case where the first bidirectional Zener diode 42 is arranged at the position shown in FIGS. 11 and 12 on the surface of the semiconductor substrate 1 has been described as an example, but the collector electrode 21 and the gate electrode As long as the first bidirectional Zener diode 42 is electrically connected to the semiconductor substrate 1, the first bidirectional Zener diode 42 may be disposed at another position on the surface of the semiconductor substrate 1.

  In the present embodiment, the case where the first bidirectional Zener diode 42 is used has been described as an example. However, other diodes may be used as long as the diode can clamp the collector voltage.

(Fourth embodiment)
In FIG. 14, the top view of IGBT in 4th Embodiment of this invention is shown. FIG. 15 is a sectional view taken along line BB in FIG. 14 and 15, the same reference numerals as those in FIGS. 11 and 12 are attached to the same components as those of the IGBT shown in FIGS. 11 and 12.

  In the first to third embodiments, the case where each of the first reverse conducting electrode 19 and the second reverse conducting electrode 35 has a one-layer electrode structure has been described as an example. However, as in the present embodiment, the first reverse conducting electrode is used. 19 and the second reverse conducting electrode 35 may have a two-layer electrode structure.

  The present embodiment is an example in which the first reverse conducting electrode 19 and the second reverse conducting electrode 35 have a two-layer electrode structure with respect to the IGBT having the structure shown in FIGS. 11 to 13 described in the third embodiment. . The first reverse conducting electrode 19 corresponds to the third electrode of the present invention, and the second reverse conducting electrode 35 corresponds to the fourth electrode of the present invention.

  As shown in FIG. 15, a part of the second reverse conducting electrode 35 is formed on the first reverse conducting electrode 19 via the interlayer insulating film 37, and the first reverse conducting electrode 19 is the first layer. The second reverse conducting electrode 35 is the second layer. Therefore, as shown in FIG. 14, in the planar layout, the first reverse conducting electrode 19 and the second reverse conducting electrode 35 overlap each other.

  The IGBT having such a structure is manufactured by changing the formation process of the first reverse conducting electrode 19 and the second reverse conducting electrode 35 with respect to the manufacturing process of the IGBT described in the first embodiment.

  For example, between the step shown in FIG. 7B and the step shown in FIG. 8A, the step of forming the first reverse conducting electrode 19 and the interlayer insulating film 37 on the first reverse conducting electrode 19 are formed. Add a process to form. Then, in the process shown in FIG. 8A, the emitter electrode 18 and the second reverse conducting electrode 35 are formed simultaneously. In this way, the IGBT shown in FIGS. 14 and 15 can be manufactured.

  As described above, the first reverse conducting electrode 19 and the second reverse conducting electrode 35 have a two-layer electrode structure, so that the first reverse conducting electrode 19 and the IGBT shown in FIGS. The outer peripheral region 3 where the second reverse conducting electrode 35 is formed can be reduced.

  In the present embodiment, the case where the second reverse conducting electrode 35 is formed on the first reverse conducting electrode 19 has been described as an example. On the contrary, the first reverse conducting electrode 35 is formed on the first reverse conducting electrode 35. A reverse conducting electrode 19 can also be formed.

  In the present embodiment, the case where the first reverse conducting electrode 19 and the second reverse conducting electrode 35 have a two-layer electrode structure is described as an example with respect to the IGBT of the third embodiment. Similarly, in the IGBT, the first reverse conducting electrode 19 and the second reverse conducting electrode 35 may have a two-layer electrode structure.

(Fifth embodiment)
In FIG. 16, the top view of IGBT in 5th Embodiment of this invention is shown. FIG. 17 is a cross-sectional view taken along line CC in FIG. 11, and FIG. 18 is an electric circuit diagram of the IGBT in FIGS. 16 to 18, the same reference numerals as those in FIGS. 1 to 3 and FIGS. 11 to 13 are attached to the same components as those of the IGBT shown in FIGS. 1 to 3 and the IGBT shown in FIGS. .

  The IGBT of the present embodiment is an example in which a second bidirectional Zener diode connected in parallel to the polysilicon resistor 34 is added to the combination of the second embodiment and the third embodiment.

  That is, in the present embodiment, as shown in FIG. 16, the first bidirectional Zener diode 42 is arranged in the outer peripheral region 3 of the semiconductor substrate 1 as in the IGBT shown in FIG. 11 described in the third embodiment. ing. Since the configuration and arrangement location of the first bidirectional Zener diode 42 are the same as those in the third embodiment, the description thereof is omitted here.

  Further, as shown in FIG. 16, polysilicon resistors 34 are arranged at the four corners of the outer peripheral region 3 of the semiconductor substrate 1 in the same manner as the IGBT shown in FIG. 9 described in the second embodiment. . One of these polysilicon resistors 34 is shown on the right end side in FIG. Since the polysilicon resistor 34 is the same as that described in the second embodiment, the description thereof is omitted here.

  In this embodiment, as shown in FIG. 16, the second bidirectional Zener diode 51 is disposed between the polysilicon resistors 34. The second bidirectional Zener diode 51 corresponds to the diode of the present invention.

  The second bidirectional Zener diode 51 is arranged continuously with the polysilicon resistor 34, and the second bidirectional Zener diode 51 and the polysilicon resistor 34 have a substantially rectangular frame shape.

  The second bidirectional Zener diode 51 is made of polysilicon and is formed on the semiconductor substrate 1 with an insulating film 36 as shown on the left end side in FIG. A first reverse conducting electrode 19 and a second reverse conducting electrode 35 are formed on the second bidirectional Zener diode 51 via an interlayer insulating film 37.

  As shown in FIG. 16, the first reverse conducting electrode 19 is arranged in a substantially rectangular frame shape inside the polysilicon resistor 34 and the second bidirectional Zener diode 51. On the other hand, as shown in FIG. 16, the second reverse conducting electrode 35 is disposed outside the polysilicon resistor 34 and the second bidirectional Zener diode 51 in a substantially rectangular frame shape.

  In the second bidirectional Zener diode 51, one end 51a, which is the center side of the semiconductor substrate 1 (the center side in FIGS. 16 and 17), is electrically connected to the first reverse conducting electrode 19, and the outer peripheral side (see FIG. The other end 51 b, which is the end side of 16 and 17, is electrically connected to the second reverse conducting electrode 35.

  Note that the polysilicon resistor 34 also has one end 34 a electrically connected to the first reverse conducting electrode 19 and the other end 34 b electrically connected to the second reverse conducting electrode 35.

  Therefore, as shown in FIG. 18, in the state where the emitter electrode 18 and the collector electrode 21 are electrically connected via the polysilicon resistor 34 and the reverse conducting diode 22, the second bidirectional Zener diode 51 is The emitter electrode 18 and the collector electrode 21 are connected in parallel with the polysilicon resistor 34.

  Moreover, the IGBT of this embodiment is manufactured by changing the manufacturing method demonstrated in 1st Embodiment as follows, for example. That is, in the process shown in FIG. 6A, the gate electrode 16 and the polysilicon resistor 34 are formed, and at the same time, the second bidirectional Zener diode 51 is also formed. At this time, the first bidirectional Zener diode 42 is also formed at the same time.

  As described above, in the present embodiment, the second bidirectional Zener diode 51 is connected in parallel to the polysilicon resistor 34.

  Thereby, the voltage applied to the polysilicon resistor 34 can be made constant, and the current flowing through the polysilicon resistor 34 can be made to be a predetermined magnitude or less. In other words, the polysilicon resistor 34 can be protected so that it is not destroyed by a large current flowing.

  Further, since the second bidirectional Zener diode 51 is electrically connected between the collector and the emitter, the first to fourth embodiments that do not have the second bidirectional Zener diode 51 will be described. Compared to the IGBT, the reverse surge resistance between the collector and the emitter can be improved.

  In the present embodiment, the case where the second bidirectional Zener diode 51 is used has been described as an example. However, a unidirectional Zener diode can be used instead of the second bidirectional Zener diode 51. In this case, the cathode of the Zener diode is electrically connected to the emitter electrode 18 and the anode is electrically connected to the collector electrode 21.

  The case where the second bidirectional Zener diode 51 is connected in parallel to the polysilicon resistor 34 has been described as an example for the purpose of both protecting the polysilicon resistor 34 and improving the reverse surge withstand capability. On the other hand, when the purpose is only to improve the reverse surge withstand capability, the second bidirectional Zener diode 51 may be connected in series with the polysilicon resistor 34 and the reverse conducting diode 22 between the collector and the emitter. it can.

  In the present embodiment, the case where the Zener diode 51 is used has been described as an example. However, other diodes may be used as long as the reverse surge withstand capability and the polysilicon resistance 34 can be protected. .

(Other embodiments)
(1) In the first embodiment, the case where the polysilicon resistor 34 is formed simultaneously with the gate electrode 16 in the step shown in FIG. 6A has been described as an example. It can also be formed by this process. However, the case where the polysilicon resistor 34 is formed simultaneously with the gate electrode 16 as in the first embodiment is preferable in that the manufacturing process can be simplified.

(2) In the first embodiment, the case where the P-type base region 13, the N ⁺ -type emitter region 14, and the N ⁺ -type layer 20 are formed after the gate insulating film 15 and the gate electrode 16 are formed has been described as an example. Before forming the gate insulating film 15 and the gate electrode 16, the P-type base region 13, the N ⁺ -type emitter region 14, and the N ⁺ -type layer 20 can also be formed.

(3) In each of the above-described embodiments, a case where the polysilicon resistor 34 formed on the surface of the semiconductor substrate 1 via the insulating film 36 is connected between the N ⁺ type layer 20 and the collector electrode 21. Although described as an example, if a resistive element is formed on the same semiconductor substrate 1 as the semiconductor substrate 1 on which the IGBT element is formed, that is, a resistive element built in the IGBT, another resistive element may be used. it can.

  For example, a diffused resistor formed in the semiconductor substrate can be used in place of the polysilicon resistor 34.

  Further, instead of the resistance element built in the IGBT, the IGBT element is formed by using a resistance element formed on a semiconductor substrate different from the semiconductor substrate 1 on which the IGBT element is formed, or a general resistor. It can also be externally attached.

  (4) In each of the above-described embodiments, the case where the present invention is applied to a planar type IGBT has been described as an example. However, the present invention can also be applied to a trench gate type IGBT.

In this case, a gate electrode is formed inside the trench formed in the P-type base region 13 via a gate insulating film, and an N ⁺ -type emitter region 14 adjacent to the trench on the inner surface side of the P-type base region 13. Is formed. At this time, a portion adjacent to the trench gate is a channel region between the N ⁺ -type emitter region 14 and the N ⁻ -type drift layer 12.

(5) In the above embodiments, P-type base region 13, N ^- inside the type drift layer 12, N ^- N on the surface side of the type drift layer 12 ^- joint -type drift layer 12 is terminated However, as long as the P-type base region 13 is joined to the N ⁻ -type drift layer 12, other shapes can be used.

  (6) In each of the above-described embodiments, the case where the first conductivity type is the P type and the second conductivity type is the N type has been described as an example. Conversely, the first conductivity type is the N type, The two conductivity type may be a P type. That is, in the IGBT of each of the above-described embodiments, each conductivity type can be set to the opposite conductivity type.

It is a top view of IGBT in 1st Embodiment of this invention. It is the sectional view on the AA line in FIG. It is an electric circuit diagram of IGBT in FIG. It is sectional drawing for demonstrating the manufacturing process of IGBT shown by FIG. It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 6 is a cross-sectional view for explaining a manufacturing step subsequent to FIG. 5. FIG. 7 is a cross-sectional view for explaining a manufacturing step subsequent to FIG. 6. FIG. 8 is a cross-sectional view for explaining a manufacturing step subsequent to FIG. 7. It is a top view of IGBT in the 1st example of 2nd Embodiment of this invention. It is a top view of IGBT in the 2nd example of 2nd Embodiment of this invention. It is a top view of IGBT in 3rd Embodiment of this invention. It is the BB sectional view taken on the line in FIG. FIG. 13 is an electric circuit diagram of the IGBT in FIGS. 11 and 12. It is a top view of IGBT in 4th Embodiment of this invention. It is the BB sectional view taken on the line in FIG. It is a top view of IGBT in 5th Embodiment of this invention. It is CC sectional view taken on the line in FIG. FIG. 18 is an electric circuit diagram of the IGBT in FIGS. 16 and 17. It is sectional drawing of conventional IGBT. It is an electrical circuit diagram of a conventional IGBT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element area | region, 3 ... Outer periphery area | region,
11 ... P ⁺ type layer, 12 ... N ^- type drift layer, 13 ... P type base region,
14 ... N ⁺ type emitter region, 15 ... gate insulating film, 16 ... gate electrode,
17 ... interlayer insulating film, 18 ... emitter electrode, 19 ... first reverse conducting electrode,
20 ... N ⁺ type layer, 21 ... collector electrode, 22 ... reverse conducting diode,
31 ... N ⁺ type layer, 34 ... polysilicon resistor, 35 ... second reverse conducting electrode,
36 ... insulating film, 37 ... interlayer insulating film, 38 ... P-type region,
41 ... Bonding pad, 42 ... First bidirectional Zener diode,
43: Gate lead-out wiring, 51: Second bidirectional Zener diode.

Claims (8)

The first conductivity type first semiconductor layer (11), the second conductivity type second semiconductor layer (12) formed on the first semiconductor layer (11), and the second semiconductor layer (12) are joined. A semiconductor substrate (1) having a third semiconductor layer (13) of the first conductivity type and a fourth semiconductor layer (14) of the second conductivity type formed on the inner surface side of the third semiconductor layer (13); ,
A gate insulating film (15) is formed on the channel region, with the surface side portion of the third semiconductor layer (13) positioned between the second semiconductor layer (12) and the fourth semiconductor layer (14) serving as a channel region. ) Formed through the gate electrode (16),
A first electrode (18) electrically connected to the third semiconductor layer (13) and the fourth semiconductor layer (14);
A second electrode (21) electrically connected to the first semiconductor layer (11);
A second conductivity type second conductive layer formed on the inner surface side of the second semiconductor layer (12) with a higher impurity concentration than the second semiconductor layer (12) and electrically connected to the second electrode (21). In an IGBT comprising 5 semiconductor layers (20),
An insulated gate bipolar transistor comprising a resistor (34) electrically connected between the fifth semiconductor layer (20) and the second electrode (21). The insulated gate bipolar transistor according to claim 1, wherein the resistor is a resistance element (34) formed on the semiconductor substrate (1). The insulated gate bipolar transistor according to claim 2, wherein the resistance element (34) is formed on the surface of the semiconductor substrate (1) via an insulating film (36). The insulated gate bipolar transistor according to any one of claims 1 to 3, wherein the resistance element (34) is 10Ω or more and 1MΩ or less. It is formed on the surface of the semiconductor substrate (1), is electrically connected to the fifth semiconductor layer (20), and is electrically connected to one end side (34a) of the resistance element (34). A third electrode (19);
A fourth electrode (35) formed on the surface of the semiconductor substrate (1) and electrically connected to the other end side (34b) of the resistance element (34);
The insulated gate bipolar transistor according to any one of claims 2 to 4, wherein the third electrode (19) and the fourth electrode (35) have a laminated structure. Between the first electrode (18) and the second electrode (21), the resistor element (34) is connected in series, and at least the cathode is electrically connected to the first electrode (18), 6. The insulated gate bipolar transistor according to claim 2, further comprising a bidirectional Zener diode (51) whose anode is electrically connected to the second electrode (21). Between the first electrode (18) and the second electrode (21), connected in parallel to the resistance element (34), and at least a cathode is electrically connected to the first electrode (18), 6. The insulated gate bipolar transistor according to claim 2, further comprising a bidirectional Zener diode (51) whose anode is electrically connected to the second electrode (21). Providing a semiconductor substrate (1) having a first semiconductor layer (11) of a first conductivity type and a second semiconductor layer (12) of a second conductivity type formed on the first semiconductor layer (11); ,
Forming a first conductive type third semiconductor layer (13) on the inner surface side of the second semiconductor layer (12);
Forming a second conductive type fourth semiconductor layer (14) on the inner surface side of the third semiconductor layer (13);
A fifth semiconductor layer (20) having a higher impurity concentration than that of the second semiconductor layer (12) is formed on the inner surface side of the second semiconductor layer (12) and spaced apart from the third semiconductor layer (13). And a process of
Forming a gate insulating film (15) on the surface of the semiconductor substrate (1) and on a channel formation planned region;
Forming an insulating film (36) thicker than the gate insulating film (15) on the surface of the semiconductor substrate (1) and on a region different from the channel formation scheduled region;
Forming a gate electrode (16) on the gate insulating film (15);
Forming a first electrode (18) electrically connected to the third semiconductor layer (13) and the fourth semiconductor layer (14);
In a method for manufacturing an insulated gate bipolar transistor, comprising: forming a second electrode electrically connected to the first semiconductor layer (11) and the fifth semiconductor layer (20).
In the step of forming the gate electrode (16), simultaneously with the formation of the gate electrode (16), between the fifth semiconductor layer (20) and the second electrode (21) on the insulating film (36). A method of manufacturing an insulated gate bipolar transistor, comprising: forming a resistance element (34) electrically connected to the gate electrode.

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