JP4078895B2

JP4078895B2 - Semiconductor device

Info

Publication number: JP4078895B2
Application number: JP2002184675A
Authority: JP
Inventors: 功吉川
Original assignee: Fuji Electric Device Technology Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2002-06-25
Filing date: 2002-06-25
Publication date: 2008-04-23
Anticipated expiration: 2022-06-25
Also published as: JP2004031575A

Description

【０００１】
【発明の属する技術分野】
この発明は、電力変換装置などに搭載される半導体装置に関する。
【０００２】
【従来の技術】
電流容量が大きいパワー半導体装置では、半導体基板の表面と裏面に主電極を配置し、主電流を半導体基板に対して縦方向に流す縦型半導体装置が主流である。
図６は、半導体装置の要部平面図である。この半導体チップ２００はＩＧＢＴチップであり、チップ周辺部には耐圧構造２０１、その内側には活性領域２０２が形成される。この活性領域２０２には、エミッタ電極やゲートパッドなどが形成される。
【０００３】
縦型半導体装置では、半導体装置の阻止耐圧を確保するために、主電流が流れる活性領域の周囲に耐圧構造を配置している。この耐圧構造は、フィールドリミティングリングやフィールドプレートなどが代表的であり、半導体基板の表面に形成される。
一方、横型半導体装置の耐圧構造は、シングルリサーフおよびダブルリサーフなどの構造が多用されている。
【０００４】
このダブルリサーフにすると、横型半導体装置のドリフト層（ベース層）の濃度設計の自由度を広げることが可能であり、前記のフィールドリミッティングリングやフィールドプレートに比べて、耐圧構造の占める面積を低減できる。
図７は、耐圧構造２０１としてフィールドリミティングリングを適用した縦型のＩＧＢＴで、図６のＸ−Ｘ線で切断した要部断面図である。
【０００５】
図中の１はｎ形のドリフト層、２はｐ形のウエル領域、５はｎ形のエミッタ領域、６は絶縁膜（ゲート電極下はゲート絶縁膜）、８はゲート電極、１０は絶縁膜、１１はエミッタ電極、１３はｎ形のバッファ層、１４はｐ形のコレクタ層、１５はコレクタ電極、６１はフローティングリング、６２はｐ形もしくはｎ形のストッパ領域、９、６３は導電膜である。便宜的に最外周に配置されるウエル領域２の中央部より外側を耐圧構造２０１と内側を活性領域２０２とする。
【０００６】
図８は、縦型ＩＧＢＴの耐圧構造２０１として、横型半導体装置に多用されているリサーフ構造を適用したものである。ここではダブルリサーフ構造を例として挙げた。耐圧構造２０１としてダブルリサーフ構造を採用すると、フィールドリミティング構造に比べて、製造プロセスにおいて、イオン注入時の濃度の制御が必要となるものの、耐圧構造に要する面積を縮小することができる。
【０００７】
図８において、図７と同じ構成については同じ符号を付して説明は省略する。３は第１領域、１０は絶縁膜である。
図７、図８の耐圧構造は、半導体装置がオフ状態のときに、活性領域を構成するウエル領域２から広がる空乏層を、半導体チップ２００の外周方向へ（活性領域２０２から遠ざける方向）延ばすことで、ウエル領域２の近傍で電界集中を緩和する。
【０００８】
【発明が解決しようとする課題】
しかし、耐圧構造２０１が占める領域（耐圧構造領域）は、半導体装置がオフ状態の場合には、阻止耐圧を確保するために有効な領域であるが、半導体装置がオン状態の場合は、この耐圧構造領域には主電流が流れないために、無用な領域となる。
【０００９】
このため、電流容量が小さい（半導体チップが小さい）縦型半導体装置ほど、素子面積（活性領域の面積＋耐圧構造領域の面積でほぼ半導体チップ２００の面積となる）に占める耐圧構造領域の面積の割合が大きくなり、その結果、活性領域の面積の割合は小さくなる。そのため、主電流通電領域の面積が減少して、オン電圧は大きくなる。
【００１０】
この発明の目的は、前記の課題を解決して、主電流通電領域を増大し、オン電圧の低減を図ることができる半導体装置を提供することにある。
【００１１】
【課題を解決するための手段】
前記の目的を達成するために、絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と接続し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に形成される第１導電形の第５半導体領域と、前記最外周に配置された第２半導体領域の表面層に形成される第４半導体領域と前記第５半導体領域との間に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主ゲート電極と前記第５半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極と、前記第５半導体領域上に形成され、第２主電極と接続するための第２副電極とを具備することを特徴とする半導体装置。
【００１２】
(請求項２) 絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と分離し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に形成される第１導電形の第５半導体領域と、最外周に配置された前記第２半導体領域と対向して前記第３半導体領域の表面層に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主ゲート電極と、前記第５半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極と、前記第５半導体領域上に形成され、第２主電極と接続するための第２副電極とを具備する構成とする。
【００１３】
また、絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と接続し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に形成される第１導電形の第５半導体領域と、前記最外周に配置された第２半導体領域の表面層に形成される第４半導体領域と前記第５半導体領域との間に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主ゲート電極と前記第５半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極と、前記第５半導体領域上に形成され、第２主電極と接続するための第２副電極とを具備し、前記第２副電極と接続し、前記第５半導体領域の表面層に形成される第２導電形の第７半導体領域を有するとよい。
また、前記第５半導体領域上に絶縁膜を介して前記第１主電極と前記第２副電極が対向して形成されるとよい。
また、絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と接続し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に環状に形成される第８半導体領域と、最外周に配置された前記第２半導体領域の表面層に形成された第４半導体領域と前記第８半導体領域との間に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主ゲート電極と、前記第８半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極とを具備し、
前記第８半導体領域を、互いの半導体領域の表面層に交互に形成される第１導電形の環状の第９半導体領域と第２導電形の環状の第１０半導体領域とで構成し、最上段に形成される第９半導体領域上に形成され、前記第２主電極と接続する第２副電極を有する構成とする。
【００１４】
また、絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と分離し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に環状に形成される第８半導体領域と、最外周に配置された前記第２半導体領域に対向して前記第３半導体領域の表面層に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主ゲート電極と、前記第８半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極とを具備し、
前記第８半導体領域を、互いの半導体領域の表面層に交互に形成される第１導電形の環状の第９半導体領域と第２導電形の環状の第１０半導体領域とで構成し、露出した第９半導体領域上に形成され、前記第２主電極と接続する第２副電極を有する構成とする。
【００１５】
また、絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と接続し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に環状に形成される第１１半導体領域と、最外周に配置された前記第２半導体領域の表面層に形成される第４半導体領域と前記１１半導体領域との間に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主ゲート電極と、前記第１１半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極とを具備し、
前記第１１半導体領域を、前記第３半導体領域の環状の長手方向に、互いに接して環状の長手方向に交互に形成される第１導電形の第１２半導体領域と第２導電形の第１３半導体領域とから形成し、前記第１２半導体領域上に形成され、前記第２主電極と接続する第２副電極を有する構成とする。
【００１６】
また、絶縁ゲート構造を有する縦型の半導体装置において、第１導電形の第１半導体領域と、該第１半導体領域の表面層に複数個形成される第２導電形の第２半導体領域と、最外周に配置された該第２半導体領域と分離し、該第２半導体領域の外側の前記第１半導体領域の表面層に該第２半導体領域を取り囲む環状に形成される第２導電形の第３半導体領域と、全ての前記第２半導体領域の表面層に形成される第１導電形の第４半導体領域と、前記第３半導体領域の表面層に環状に形成される第１１半導体領域と、最外周に配置される前記第２半導体領域に対向して前記第３半導体領域の表面層に形成される第１導電形の第６半導体領域と、全ての前記第２半導体領域の前記第４半導体領域と前記第１半導体領域に挟まれた領域にゲート絶縁膜を介して形成される主電極と、前記１１半導体領域と前記第６半導体領域に挟まれた領域上にゲート絶縁膜を介して形成される副ゲート電極と、前記第４半導体領域上に形成される第１主電極と、前記縦型の半導体装置の裏面電極としての第２主電極とを具備し、
前記第１１半導体領域を、前記第３半導体領域の環状の長手方向に、互いに接して環状の長手方向に交互に形成される第１導電形の第１２半導体領域と第２導電形の第１３半導体領域とから形成し、前記第１２半導体領域上に形成され、前記第２主電極と接続する第２副電極を有する構成とする。
【００１７】
また、前記第１１半導体領域上に絶縁膜を介して前記第１主電極と前記第２副電極が対向して形成されるとよい。
【００１８】
【００１９】
【発明の実施の形態】
図１は、この発明の第１実施例の半導体装置の構成図で、同図（ａ）は要部平面図、同図（ｂ）は要部断面図である。要部平面図は、図１（ｂ）の最上層から半導体基板面までの層が分かるように描いた。また、図８と同一箇所には同一の符号を記した。
【００２０】
縦型半導体装置は、耐圧クラス６００ＶのＩＧＢＴで耐圧構造がダブルリサーフであり、この耐圧構造に、ＭＯＳＦＥＴを形成した場合である。また、この半導体装置は、半導体チップの大きさが２．５ｍｍ□で電流容量は５Ａの場合である。厚さが５００μｍ、比抵抗約６０Ωｃｍのｎ形の半導体基板１００を用いた。半導体基板１００の一方の主面の表面層に、複数個のｐ形のウエル領域２を形成し、このウエル領域２の表面層にｎ形のエミッタ領域５を形成する。エミッタ領域５と半導体基板１００（ドリフト層１）に挟まれたウエル領域２上に絶縁膜６（ゲート絶縁膜）を介してゲート電極８を形成する。エミッタ領域５とウエル領域２に接するようにエミッタ電極１１を形成する。
【００２１】
基板裏面には後述するようにバッファ層１３、コレクタ層１４、コレクタ電極１５を形成して、ＩＧＢＴセル部を構成する。尚、活性領域２０２内に形成する縦型半導体装置セルは、プレーナゲート構造のＩＧＢＴセルに限るものではない。例えば、ウエル領域２内にトレンチを形成し、トレンチ内に絶縁膜を介してゲート電極を形成したトレンチゲート構造のＩＧＢＴセルでもよい。また基板裏面の構造を変更して縦型のＭＯＳＦＥＴセルを構成してもよい。また、図中の９は導電膜であり、削除しても構わない。
【００２２】
つぎに、耐圧構造について説明する。耐圧構造２０１は、半導体基板１００の外周部にｐ形の第１領域３を形成し、第１領域３の表面層にｎ形の第２領域４を形成し、ダブルリサーフを構成する。図１は、活性領域２０２の最外側のウエル領域２と第１領域３が接している場合を示したものである。
第１領域３内の第２領域４とは離れた位置にｎ形のエミッタ領域５１を形成し、第２領域４とエミッタ領域５１とに挟まれた第１領域３上に絶縁膜（ゲート絶縁膜）を介してゲート電極８１を形成する。エミッタ領域５１並びにゲート電極８１は縦型のＩＧＢＴセルのエミッタ領域５並びにゲート電極８にそれぞれ接続される。図１に示すように、第１領域３がウエル領域２と接している場合、エミッタ領域５１を第１領域内の活性領域２０２寄りに設けると、共通のエミッタ電極１１で一括して配線することができる。また、ゲート電極８とゲート電極８１との接続も容易である。
【００２３】
第２領域４の外周部に補助コレクタ１２を形成し、エミッタ電極１１と補助コレクタ電極１２は第２領域上に形成した絶縁膜１０を介して対向して張り出して形成される。
第１領域３とウエル領域２は通常は、不純物濃度および拡散深さが異なるが、同一条件で形成しても構わない。
【００２４】
前記のダブルリサーフを形成するためのイオン種と注入量（ドーズ量）を説明する。第１領域は、イオン種はボロンで、注入量は約６．０×１０¹²ｃｍ^-2である。第２領域は、イオン種はリンで、注入量は約４．８×１０¹²ｃｍ^-2である。耐圧構造の幅は約１００μｍである。深さ方向の拡散プロファイルは図２に示す。
【００２５】
このような諸元のダブルリサーフにすると、耐圧構造内に形成したＭＯＳＦＥＴのドリフト領域の抵抗率は約０．２Ωｃｍ²（不純物濃度は約２．０×１０¹⁶ｃｍ^-3）と極めて小さな値となる。この値は、通常の６００ＶＭＯＳＦＥＴのドリフト領域の抵抗率６０Ωｃｍ（不純物濃度は約７．８×１０¹³ｃｍ^-3）の約１／３００となる。
【００２６】
前記の５００μｍ厚さの半導体基板１００を１００μｍ厚程度まで研削した後、半導体基板１００の他方の主面（研削した面）の表面層にｎ形のバッファ層１３を形成し、このバッファ層１３の表面層にコレクタ層１４を形成し、このコレクタ層１４上にコレクタ電極１５を形成する。
前記のようにして形成した半導体チップ２００の裏面側のコレクタ電極１５を図示しない回路パターン付き絶縁基板にはんだで固着し、このコレクタ電極１５が固着された回路パターンと補助コレクタ電極１２をアルミニウムワイヤでボンディング接続する。また、表面電極パッド（エミッタ電極パッドやゲート電極パッド）と図示しない外部導出端子をアルミニウムワイヤでボンディング接続する。
【００２７】
図１（ｂ）に点線で囲んで示すように、耐圧構造内に横型のＭＯＳＦＥＴを形成することで、ＩＧＢＴのオン時に、主電流がＩＧＢＴセル部（活性領域）以外にこの横型のＭＯＳＦＥＴを介しても流れるために、主電流通電面積を増大できて、オン電圧を低減することができる。
また、ＩＧＢＴでは０．６Ｖのえん層電圧を超えるまでは、主電流が殆ど流れないが、この半導体装置では、横型のＭＯＳＦＥＴを介して０Ｖから主電流が流れるために、通常のＩＧＢＴに比べてオン特性が向上する。
【００２８】
また、主電流が増大し、ＩＧＢＴのオン電圧が大きくなると、コレクタ層１４、バッファ層１３、ドリフト層１、第１領域３、第２領域４で構成されるｐｎｐｎのサイリスタ部（図１（ｂ）に一点鎖線で示す）にも主電流が伝導度変調状態して流れるようになり、さらにオン電圧は低下する。
以上説明した実施例では、絶縁ゲート構造を有する縦型半導体装置の活性領域の外周に形成される耐圧構造に横型の絶縁ゲート構造を有する素子を形成し、両者のゲート端子同士を接続し、エミッタ端子同士、コレクタ端子同士をそれぞれ接続している。かかる構成により主電流通電領域を増大し、オン電圧の低減を図っている。
【００２９】
上記の構成の他に、各端子同士を接続するのではなく個別に引き出してもよい。各素子のゲートしきい値電圧が異なる場合など、各素子にそれぞれ異なる電圧の供給が可能となる。
また、各素子へのゲート信号を同相とすれば、上述のようにオン電圧を低減することができるし、個々にゲート信号を供給すれば両者を独立して駆動することもできる。
【００３０】
図３は、この発明の第２実施例の半導体装置の構成図で、同図（ａ）は要部平面図、同図（ｂ）は要部断面図である。要部平面図は、最上層から半導体基板面までの層が分かるように描いた。
図１との違いは、（ａ）の平面図に示すように、エミッタ領域５から補助コレクタ電極１２方向を長手とするｎ形領域２１とｐ形領域２２をそれぞれ交互に形成し、第１図の第２領域４に相当する箇所を平面的に領域２１、２２が互いに交互に接するように配置された点である。補助コレクタ電極１２とｎ形領域２１はコンタクトホール２３で接続する。このｎ形領域２１とｐ形領域２２で構成される領域は、ストライプで交互に配置されているのであるが、半導体チップの外周に沿ってリング状をしている第１領域３の表面層に形成され、第１領域３の長手方向に交互にこのストライプが接してリング状に配置される。
【００３１】
各領域２１、２２の不純物濃度を最適化することで、図１よりさらにオン電圧を低減できる。
尚、図３では第１領域３とウエル領域２が接しているが、それぞれを分離していても構わない。
図４は、この発明の第３実施例の半導体装置の要部断面図である。平面図は図１（ａ）の要部平面図と同じである。
【００３２】
図１との違いは、第１領域３内の第２領域４に相当する箇所にｎ形領域３１とｐ形領域３２を交互に形成した点である。補助コレクタ電極１２とｎ形領域３１はコンタクトホール３３で接続する。
各領域３１、３２の不純物濃度を最適化することで、図１よりさらにオン電圧を低減できる。尚、図４では第１領域３とウエル領域２が接しているが、それぞれを分離していても構わない。
【００３３】
また、前記の図３と図４は、図１の第２領域４に相当する箇所に、超接合構造（ｓｕｐｅｒｊｕｎｃｔｉｏｎ構造）と言われる構造を適用したものである。
図５は、この発明の第４実施例の半導体装置の構成図で、 (a) は要部平面図であり、（ｂ）は要部断面図である。図１との違いは、第２領域の表面層にｐ形の補助コレクタ領域４１を形成して、横型のＩＧＢＴとした点である。横型のＭＯＳＦＥＴを横型のＩＧＢＴとすることで、オン状態において、補助コレクタ電極１２からホールの注入が生じ、耐圧構造内に形成する横型素子のオン抵抗を大幅に小さくできる。その結果、図１に比べてオン電圧を小さくできる。尚、図５では第１領域３とウエル領域２が接しているが、それぞれを分離していても構わない。
【００３４】
第１から第４実施例に相当する縦型半導体装置（ＩＧＢＴ）を縦型のＭＯＳＦＥＴとしても構わない。
【００３５】
【発明の効果】
この発明によれば、縦型半導体装置の耐圧構造部に多重リサーフ構造を採用して、この耐圧構造内に横型素子を形成することで、主電流導通領域を拡大し、オン電圧を低減することができる。
【図面の簡単な説明】
【図１】この発明の第１実施例の半導体装置の構成図で、（ａ）は要部平面図、（ｂ）は要部断面図
【図２】第１領域と第２領域の拡散プロフィル図
【図３】この発明の第２実施例の半導体装置の構成図で、（ａ）は要部平面図、（ｂ）は要部断面図
【図４】この発明の第３実施例の半導体装置の要部断面図
【図５】この発明の第４実施例の半導体装置の構成図で、（ａ）は要部平面図、（ｂ）は要部断面図
【図６】半導体装置の要部平面図
【図７】耐圧構造としてフィールドリミティングリングを適用した縦型のＩＧＢＴの要部断面図である。
【図８】耐圧構造としてダブリリサーフを適用した縦型のＩＧＢＴの要部断面図
【符号の説明】
１ドリフト層
２ウエル領域
３第１領域
４第２領域
５、５１エミッタ領域
６絶縁膜（ゲート絶縁膜を含む）
８、８１ゲート電極
９、６３導電膜
１０絶縁膜（層間絶縁膜）
１１エミッタ電極
１２補助コレクタ電極
１３バッファ層
１４コレクタ層
１５コレクタ電極
２１、３１ｎ形領域
２２、３２ｐ形領域
２３、３３コンタクトホール
６１フィールドリミッティングリング
６２ストッパ領域
１００半導体基板
２００半導体チップ
２０１耐圧構造
２０２活性領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device mounted on a power conversion device or the like.
[0002]
[Prior art]
In a power semiconductor device having a large current capacity, a vertical semiconductor device in which main electrodes are arranged on the front and back surfaces of a semiconductor substrate and a main current is passed in a vertical direction with respect to the semiconductor substrate is the mainstream.
FIG. 6 is a plan view of a principal part of the semiconductor device. The semiconductor chip 200 is an IGBT chip. A breakdown voltage structure 201 is formed around the chip, and an active region 202 is formed inside thereof. In the active region 202, an emitter electrode and a gate pad are formed.
[0003]
In a vertical semiconductor device, a withstand voltage structure is arranged around an active region through which a main current flows in order to ensure the blocking withstand voltage of the semiconductor device. This breakdown voltage structure is typically a field limiting ring or a field plate, and is formed on the surface of the semiconductor substrate.
On the other hand, structures such as single resurf and double resurf are often used as the breakdown voltage structure of the horizontal semiconductor device.
[0004]
With this double resurf, it is possible to increase the degree of freedom in designing the concentration of the drift layer (base layer) of the lateral semiconductor device, and the area occupied by the breakdown voltage structure is smaller than that of the field limiting ring or field plate. Can be reduced.
FIG. 7 is a vertical cross-sectional view taken along line XX in FIG. 6, which is a vertical IGBT to which a field limiting ring is applied as the breakdown voltage structure 201.
[0005]
In the figure, 1 is an n-type drift layer, 2 is a p-type well region, 5 is an n-type emitter region, 6 is an insulating film (a gate insulating film below the gate electrode), 8 is a gate electrode, and 10 is an insulating film. , 11 is an emitter electrode, 13 is an n-type buffer layer, 14 is a p-type collector layer, 15 is a collector electrode, 61 is a floating ring, 62 is a p-type or n-type stopper region, and 9 and 63 are conductive films. is there. For the sake of convenience, the outer side of the center of the well region 2 arranged on the outermost periphery is defined as a pressure resistant structure 201 and the inner side is defined as an active region 202 .
[0006]
FIG. 8 shows a structure in which a RESURF structure frequently used in a horizontal semiconductor device is applied as a breakdown voltage structure 201 of a vertical IGBT. Here, a double resurf structure is taken as an example. When the double resurf structure is adopted as the breakdown voltage structure 201, the area required for the breakdown voltage structure can be reduced, although the concentration control at the time of ion implantation is required in the manufacturing process as compared with the field limiting structure.
[0007]
In FIG. 8, the same components as those in FIG. Reference numeral 3 denotes a first region, and 10 denotes an insulating film.
7 and 8 extends the depletion layer extending from the well region 2 constituting the active region toward the outer periphery of the semiconductor chip 200 (in a direction away from the active region 202) when the semiconductor device is in the off state. Thus, the electric field concentration is relaxed in the vicinity of the well region 2.
[0008]
[Problems to be solved by the invention]
However, the region occupied by the withstand voltage structure 201 (withstand voltage structure region) is an effective region for securing a blocking withstand voltage when the semiconductor device is in an off state, but this withstand voltage when the semiconductor device is in an on state. Since the main current does not flow in the structure region, it becomes a useless region.
[0009]
For this reason, the vertical semiconductor device having a smaller current capacity (smaller semiconductor chip) has an area of the breakdown voltage structure region that occupies the element area (the area of the active region + the area of the breakdown voltage structure region is approximately the area of the semiconductor chip 200). The ratio increases, and as a result, the area ratio of the active region decreases. As a result, the area of the main current supply region decreases and the on-voltage increases.
[0010]
An object of the present invention is to provide a semiconductor device capable of solving the above-described problems, increasing a main current conduction region, and reducing an on-voltage.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, in a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type and a plurality of second conductivity types formed on a surface layer of the first semiconductor region. The second semiconductor region is connected to the second semiconductor region arranged on the outermost periphery, and is formed in an annular shape surrounding the second semiconductor region in the surface layer of the first semiconductor region outside the second semiconductor region. A third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, and a first semiconductor layer formed in the surface layer of the third semiconductor region. A first conductivity type formed between a fifth semiconductor region of one conductivity type, a fourth semiconductor region formed in a surface layer of the second semiconductor region disposed on the outermost periphery, and the fifth semiconductor region; A sixth semiconductor region and the fourth semiconductor in all the second semiconductor regions; A main gate electrode formed in a region sandwiched between the first semiconductor region and a region sandwiched between the first semiconductor region and a region sandwiched between the fifth semiconductor region and the sixth semiconductor region via a gate insulating film and a sub-gate electrode to be formed, a first main electrode formed on said fourth semiconductor region, a second main electrode of the back electrode prior Kitate type semiconductor device, formed on the fifth semiconductor region And a second sub-electrode for connecting to the second main electrode.
[0012]
2. A vertical semiconductor device having an insulated gate structure, wherein a first conductivity type first semiconductor region and a plurality of second conductivity type second semiconductors formed on a surface layer of the first semiconductor region are provided. A second conductive region formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region and separated from the second semiconductor region disposed on the outermost periphery A third semiconductor region having a shape, a fourth semiconductor region having a first conductivity type formed in a surface layer of all the second semiconductor regions, and a first conductivity type formed in a surface layer of the third semiconductor region. A fifth semiconductor region, a sixth semiconductor region of a first conductivity type formed in a surface layer of the third semiconductor region so as to face the second semiconductor region disposed on the outermost periphery, and all the second semiconductors In a region between the fourth semiconductor region and the first semiconductor region, A main gate electrode formed through a gate insulating film, a sub-gate electrode formed through a gate insulating film on a region sandwiched between the fifth semiconductor region and the sixth semiconductor region, and the fourth semiconductor a first main electrode formed on a region, a second main electrode of the back electrode of the vertical semiconductor device is formed in the fifth semiconductor region, for connection to the second main electrode the It is set as the structure which comprises 2 subelectrodes.
[0013]
In the vertical semiconductor device having an insulated gate structure, a first semiconductor region of the first conductivity type, and a plurality of second semiconductor regions of the second conductivity type formed on the surface layer of the first semiconductor region, A second conductivity type second electrode connected to the second semiconductor region disposed on the outermost periphery and formed in an annular shape surrounding the second semiconductor region on the surface layer of the first semiconductor region outside the second semiconductor region. 3 semiconductor regions, fourth semiconductor regions of the first conductivity type formed in the surface layer of all the second semiconductor regions, and fifth semiconductors of the first conductivity type formed in the surface layer of the third semiconductor region A sixth semiconductor region of the first conductivity type formed between the region and the fourth semiconductor region and the fifth semiconductor region formed in the surface layer of the second semiconductor region disposed on the outermost periphery, The fourth semiconductor region and the first semiconductor region of the second semiconductor region A main gate electrode formed through a gate insulating film in a region sandwiched between them, a sub-gate electrode formed through a gate insulating film over a region sandwiched between the fifth semiconductor region and the sixth semiconductor region, The first main electrode formed on the fourth semiconductor region, the second main electrode as the back electrode of the vertical semiconductor device, and the second main electrode formed on the fifth semiconductor region and connected to the second main electrode And a second sub-electrode for connecting the second sub-electrode to the second sub-electrode and having a second conductivity type seventh semiconductor region formed in a surface layer of the fifth semiconductor region .
Furthermore, may the fifth semiconductor region via an insulating film wherein the first main electrodes second sub electrodes are formed to face.
In the vertical semiconductor device having an insulated gate structure, a first semiconductor region of the first conductivity type, and a plurality of second semiconductor regions of the second conductivity type formed on the surface layer of the first semiconductor region, A second conductivity type second electrode connected to the second semiconductor region disposed on the outermost periphery and formed in an annular shape surrounding the second semiconductor region on the surface layer of the first semiconductor region outside the second semiconductor region . Three semiconductor regions, a fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eighth semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, A sixth semiconductor region of a first conductivity type formed between a fourth semiconductor region and an eighth semiconductor region formed in a surface layer of the second semiconductor region disposed on the outermost periphery; Two semiconductor regions sandwiched between the fourth semiconductor region and the first semiconductor region. A main gate electrode formed through a gate insulating film in the region, a sub-gate electrode formed through a gate insulating film on a region sandwiched between the eighth semiconductor region and the sixth semiconductor region; comprising a first main electrode formed on said fourth semiconductor region, and a second main electrode of the back electrode prior Kitate type semiconductor device,
The eighth semiconductor region includes a first conductivity type annular ninth semiconductor region and a second conductivity type annular tenth semiconductor region which are alternately formed on the surface layer of each semiconductor region, and the uppermost stage. And a second sub-electrode connected to the second main electrode. The second sub-electrode is formed on the ninth semiconductor region.
[0014]
In the vertical semiconductor device having an insulated gate structure, a first semiconductor region of the first conductivity type, and a plurality of second semiconductor regions of the second conductivity type formed on the surface layer of the first semiconductor region, A second conductivity type second ring formed in an annular shape surrounding the second semiconductor region in the surface layer of the first semiconductor region outside the second semiconductor region, separated from the second semiconductor region disposed on the outermost periphery. Three semiconductor regions, a fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eighth semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, a sixth semiconductor region of the first conductivity type formed on the surface layer of the third semiconductor region so as to face the second semiconductor regions disposed on the outermost circumference, the fourth semiconductor of all of the second semiconductor region A gate insulating film in a region sandwiched between the region and the first semiconductor region A main gate electrode formed on the fourth semiconductor region, a sub-gate electrode formed on a region sandwiched between the eighth semiconductor region and the sixth semiconductor region via a gate insulating film, and formed on the fourth semiconductor region comprising a first main electrode that is, a second main electrode of the back electrode prior Kitate type semiconductor device,
The eighth semiconductor region is composed of an annular first semiconductor region of the first conductivity type and an annular tenth semiconductor region of the second conductivity type that are alternately formed on the surface layer of each semiconductor region, and is exposed. The second sub-electrode is formed on the ninth semiconductor region and is connected to the second main electrode.
[0015]
In the vertical semiconductor device having an insulated gate structure, a first semiconductor region of the first conductivity type, and a plurality of second semiconductor regions of the second conductivity type formed on the surface layer of the first semiconductor region, A second conductivity type second electrode connected to the second semiconductor region disposed on the outermost periphery and formed in an annular shape surrounding the second semiconductor region on the surface layer of the first semiconductor region outside the second semiconductor region . Three semiconductor regions, a fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eleventh semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, A sixth semiconductor region of the first conductivity type formed between the fourth semiconductor region and the eleventh semiconductor region formed in the surface layer of the second semiconductor region disposed on the outermost periphery; and all the second semiconductor regions In the fourth semiconductor region and the first semiconductor region of the semiconductor region A main gate electrode formed in a region sandwiched between the eleventh semiconductor region and a sixth semiconductor region, and a sub-gate electrode formed in a region sandwiched between the eleventh semiconductor region and the sixth semiconductor region; A first main electrode formed on the fourth semiconductor region; and a second main electrode as a back electrode of the vertical semiconductor device;
The eleventh semiconductor region is alternately formed in the annular longitudinal direction in contact with each other in the annular longitudinal direction of the third semiconductor region, and the 12th semiconductor region of the first conductivity type and the 13th semiconductor of the second conductivity type. And a second sub-electrode formed on the twelfth semiconductor region and connected to the second main electrode.
[0016]
In the vertical semiconductor device having an insulated gate structure, a first semiconductor region of the first conductivity type, and a plurality of second semiconductor regions of the second conductivity type formed on the surface layer of the first semiconductor region, A second conductivity type second ring formed in an annular shape surrounding the second semiconductor region in the surface layer of the first semiconductor region outside the second semiconductor region, separated from the second semiconductor region disposed on the outermost periphery. Three semiconductor regions, a fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eleventh semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, A sixth semiconductor region of a first conductivity type formed in a surface layer of the third semiconductor region so as to face the second semiconductor region disposed on the outermost periphery, and the fourth semiconductors of all the second semiconductor regions Gate insulation in a region sandwiched between the region and the first semiconductor region A main electrode formed via a gate electrode; a sub-gate electrode formed via a gate insulating film on a region sandwiched between the eleventh semiconductor region and the sixth semiconductor region; and formed on the fourth semiconductor region. A first main electrode, and a second main electrode as a back electrode of the vertical semiconductor device,
The eleventh semiconductor region is alternately formed in the annular longitudinal direction in contact with each other in the annular longitudinal direction of the third semiconductor region, and the 12th semiconductor region of the first conductivity type and the 13th semiconductor of the second conductivity type. And a second sub-electrode formed on the twelfth semiconductor region and connected to the second main electrode.
[0017]
Moreover, not good when the eleventh the said first main electrode through an insulating film on a semiconductor region second sub electrode are formed opposite.
[0018]
[0019]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view of an essential part and FIG. The main part plan view was drawn so that the layers from the uppermost layer of FIG. 1B to the semiconductor substrate surface could be seen. Moreover, the same code | symbol was described in the same location as FIG.
[0020]
The vertical semiconductor device is an IGBT having a withstand voltage class of 600 V and a double withstand voltage structure, and a MOSFET is formed in the withstand voltage structure. This semiconductor device is a case where the size of the semiconductor chip is 2.5 mm and the current capacity is 5A. An n-type semiconductor substrate 100 having a thickness of 500 μm and a specific resistance of about 60 Ωcm was used. A plurality of p-type well regions 2 are formed in the surface layer of one main surface of the semiconductor substrate 100, and an n-type emitter region 5 is formed in the surface layer of the well region 2. A gate electrode 8 is formed on the well region 2 sandwiched between the emitter region 5 and the semiconductor substrate 100 (drift layer 1) via an insulating film 6 (gate insulating film). An emitter electrode 11 is formed in contact with the emitter region 5 and the well region 2.
[0021]
As will be described later, a buffer layer 13, a collector layer 14, and a collector electrode 15 are formed on the back surface of the substrate to constitute an IGBT cell portion. The vertical semiconductor device cell formed in the active region 202 is not limited to an IGBT cell having a planar gate structure. For example, an IGBT cell having a trench gate structure in which a trench is formed in the well region 2 and a gate electrode is formed in the trench via an insulating film may be used. Further, the structure of the back surface of the substrate may be changed to constitute a vertical MOSFET cell. Further, 9 in the figure is a conductive film, which may be deleted.
[0022]
Next, the breakdown voltage structure will be described. The breakdown voltage structure 201 forms a p-type first region 3 on the outer peripheral portion of the semiconductor substrate 100 and forms an n-type second region 4 on the surface layer of the first region 3 to form a double RESURF. FIG. 1 shows a case where the outermost well region 2 of the active region 202 and the first region 3 are in contact with each other.
The n-type emitter region 51 is formed at a position apart from the second region 4 in the first region 3 of the insulating film (gate insulating on the first region 3 sandwiched between the second region 4 and the emitter region 51 A gate electrode 81 is formed through the film. The emitter region 51 and the gate electrode 81 are connected to the emitter region 5 and the gate electrode 8 of the vertical IGBT cell, respectively. As shown in FIG. 1, when the first region 3 is in contact with the well region 2, if the emitter region 51 is provided near the active region 202 in the first region, wiring with the common emitter electrode 11 is performed at once. Can do. Further, the gate electrode 8 and the gate electrode 81 can be easily connected.
[0023]
An auxiliary collector 12 is formed on the outer peripheral portion of the second region 4, and the emitter electrode 11 and the auxiliary collector electrode 12 are formed so as to face each other through the insulating film 10 formed on the second region.
The first region 3 and the well region 2 are usually different in impurity concentration and diffusion depth, but may be formed under the same conditions.
[0024]
The ion species and implantation amount (dose amount) for forming the double RESURF will be described. In the first region, the ion species is boron, and the implantation amount is about 6.0 × 10 ¹² cm ⁻² . In the second region, the ion species is phosphorus, and the implantation amount is about 4.8 × 10 ¹² cm ⁻² . The width of the breakdown voltage structure is about 100 μm. The diffusion profile in the depth direction is shown in FIG.
[0025]
When the double resurf having such specifications is used, the resistivity of the drift region of the MOSFET formed in the breakdown voltage structure is about 0.2 Ωcm ² (impurity concentration is about 2.0 × 10 ¹⁶ cm ^-3 ), which is an extremely small value. It becomes. This value is about 1/300 of the resistivity 60Ωcm (impurity concentration is about 7.8 × 10 ¹³ cm ⁻³ ) of the drift region of a normal 600V MOSFET.
[0026]
After the 500 μm-thick semiconductor substrate 100 is ground to a thickness of about 100 μm, an n-type buffer layer 13 is formed on the surface layer of the other main surface (ground surface) of the semiconductor substrate 100. A collector layer 14 is formed on the surface layer, and a collector electrode 15 is formed on the collector layer 14.
The collector electrode 15 on the back side of the semiconductor chip 200 formed as described above is fixed to an insulating substrate with a circuit pattern (not shown) by soldering, and the circuit pattern to which the collector electrode 15 is fixed and the auxiliary collector electrode 12 are made of aluminum wire. Connect by bonding. Further, the surface electrode pads (emitter electrode pads and gate electrode pads) and external lead-out terminals (not shown) are connected by bonding with aluminum wires.
[0027]
As shown by a dotted line in FIG. 1 (b), by forming a lateral MOSFET in the breakdown voltage structure, when the IGBT is turned on, the main current passes through the lateral MOSFET in addition to the IGBT cell portion (active region). However, since it flows, the main current supply area can be increased and the on-voltage can be reduced.
Also, to more than ene layer voltage of 0.6V at IGBT, but the main current hardly flows in the semiconductor device, since the main current flows from 0V through the lateral MOSFET, as compared to a normal IGBT ON characteristics are improved.
[0028]
Further, when the main current increases and the on-voltage of the IGBT increases, a pnpn thyristor portion (FIG. 1 (b)) composed of the collector layer 14, the buffer layer 13, the drift layer 1, the first region 3, and the second region 4. The main current also flows in a conductivity-modulated state, and the on-voltage decreases.
In the embodiment described above, an element having a horizontal insulated gate structure is formed in a breakdown voltage structure formed on the outer periphery of an active region of a vertical semiconductor device having an insulated gate structure, both gate terminals are connected to each other, and an emitter is formed. The terminals and collector terminals are connected to each other. With such a configuration, the main current energization region is increased and the on-voltage is reduced.
[0029]
In addition to the above-described configuration, each terminal may be pulled out individually instead of being connected. When the gate threshold voltage of each element is different, a different voltage can be supplied to each element.
Further, if the gate signals to the respective elements are in phase, the on-voltage can be reduced as described above, and if the gate signals are individually supplied, both can be driven independently.
[0030]
FIGS. 3A and 3B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 3A is a plan view of the main part and FIG . 3B is a cross-sectional view of the main part. The main part plan view was drawn so that the layers from the uppermost layer to the semiconductor substrate surface could be seen.
The difference from FIG. 1, formed in as shown in the plan view, the n-type region 21 and the p-type region 22 to the auxiliary collector electrode 12 direction is the longitudinal from the emitter region 5, respectively alternating (a), Figure 1 The points corresponding to the second region 4 are arranged such that the regions 21 and 22 are alternately in contact with each other in a plane . The auxiliary collector electrode 12 and the n-type region 21 are connected by a contact hole 23. The regions composed of the n-type region 21 and the p-type region 22 are alternately arranged in stripes , but on the surface layer of the first region 3 that is ring-shaped along the outer periphery of the semiconductor chip. The stripes are alternately formed in the longitudinal direction of the first region 3 and arranged in a ring shape.
[0031]
By optimizing the impurity concentration in each of the regions 21 and 22, the on-voltage can be further reduced as compared with FIG.
In FIG. 3, the first region 3 and the well region 2 are in contact with each other, but they may be separated from each other.
FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. The plan view is the same as the plan view of the main part of FIG.
[0032]
The difference from FIG. 1 is that n-type regions 31 and p-type regions 32 are alternately formed at locations corresponding to the second region 4 in the first region 3. The auxiliary collector electrode 12 and the n-type region 31 are connected by a contact hole 33.
By optimizing the impurity concentration in each of the regions 31 and 32, the on-voltage can be further reduced as compared with FIG. In FIG. 4, the first region 3 and the well region 2 are in contact with each other, but they may be separated from each other.
[0033]
3 and 4 are obtained by applying a structure called a super junction structure to a portion corresponding to the second region 4 in FIG.
Figure 5 is a block diagram of a semiconductor device of the fourth embodiment of the present invention, (a) is a main portion plan view, (b) is a fragmentary cross-sectional view. A difference from FIG. 1 is that a p-type auxiliary collector region 41 is formed in the surface layer of the second region to form a lateral IGBT. By using the lateral MOSFET as the lateral MOSFET, holes are injected from the auxiliary collector electrode 12 in the on state, and the on-resistance of the lateral element formed in the breakdown voltage structure can be significantly reduced. As a result, the on-voltage can be reduced as compared with FIG. In FIG. 5, the first region 3 and the well region 2 are in contact with each other, but they may be separated from each other.
[0034]
The vertical semiconductor device (IGBT) corresponding to the first to fourth embodiments may be a vertical MOSFET.
[0035]
【The invention's effect】
According to the present invention, by adopting a multiple RESURF structure in the breakdown voltage structure of the vertical semiconductor device and forming a horizontal element in the breakdown voltage structure, the main current conduction region is expanded and the ON voltage is reduced. Can do.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor device according to a first embodiment of the present invention, where FIG. 1 (a) is a plan view of an essential part and FIG. 2 (b) is a cross-sectional view of the essential part; FIGS. 3A and 3B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, where FIG. 4A is a plan view of the main part and FIG. 4B is a cross-sectional view of the main part. FIG. 5 is a block diagram of a semiconductor device according to a fourth embodiment of the present invention, in which (a) is a plan view of the relevant part and (b) is a cross-sectional view of the relevant part. FIG. 7 is a fragmentary cross-sectional view of a vertical IGBT to which a field limiting ring is applied as a breakdown voltage structure.
FIG. 8 is a cross-sectional view of the main part of a vertical IGBT using double surf as a pressure-resistant structure.
1 Drift layer
2 well region
3 First area
4 Second area
5, 51 Emitter area
6 Insulating film (including gate insulating film)
8, 81 Gate electrode
9, 63 Conductive film 10 Insulating film (interlayer insulating film)
11 Emitter electrode 12 Auxiliary collector electrode 13 Buffer layer 14 Collector layer 15 Collector electrode 21, 31 n-type region 22, 32 p-type region 23, 33 Contact hole 61 Field limiting ring 62 Stopper region 100 Semiconductor substrate 200 Semiconductor chip 201 Withstand voltage structure 202 Active region

Claims

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type connected to the second semiconductor region disposed in the ring and formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region A first conductivity type fourth semiconductor region formed in the surface layer of all the second semiconductor regions, and a first conductivity type fifth semiconductor region formed in the surface layer of the third semiconductor region; The sixth semiconductor region of the first conductivity type formed between the fourth semiconductor region and the fifth semiconductor region formed in the surface layer of the second semiconductor region disposed on the outermost periphery, and all the above The second semiconductor region is sandwiched between the fourth semiconductor region and the first semiconductor region. A main gate electrode formed through a gate insulating film in the region, a sub-gate electrode formed through a gate insulating film on a region sandwiched between the fifth semiconductor region and the sixth semiconductor region; a first main electrode formed on the fourth semiconductor region, a second main electrode of the back electrode prior Kitate type semiconductor device, formed on the fifth semiconductor region is connected to the second main electrode And a second sub-electrode for the semiconductor device.

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type that is formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region, separated from the second semiconductor region disposed in A first conductivity type fourth semiconductor region formed in the surface layer of all the second semiconductor regions, and a first conductivity type fifth semiconductor region formed in the surface layer of the third semiconductor region; The sixth semiconductor region of the first conductivity type formed in the surface layer of the third semiconductor region so as to face the second semiconductor region disposed on the outermost periphery, and the fourth of all the second semiconductor regions A gate insulating film in a region sandwiched between the semiconductor region and the first semiconductor region A main gate electrode formed through the gate electrode, a sub-gate electrode formed through a gate insulating film on a region sandwiched between the fifth semiconductor region and the sixth semiconductor region, and formed on the fourth semiconductor region. a first main electrode that is, a second main electrode of the back electrode of the vertical semiconductor device is formed in the fifth semiconductor region, and the second sub-electrode for connection to the second main electrode A semiconductor device comprising:

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type connected to the second semiconductor region disposed in the ring and formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region A first conductivity type fourth semiconductor region formed in the surface layer of all the second semiconductor regions, and a first conductivity type fifth semiconductor region formed in the surface layer of the third semiconductor region; The sixth semiconductor region of the first conductivity type formed between the fourth semiconductor region and the fifth semiconductor region formed in the surface layer of the second semiconductor region disposed on the outermost periphery, and all the above A second semiconductor region sandwiched between the fourth semiconductor region and the first semiconductor region. A main gate electrode formed through a gate insulating film in the region, a sub-gate electrode formed through a gate insulating film on a region sandwiched between the fifth semiconductor region and the sixth semiconductor region; A first main electrode formed on the fourth semiconductor region, a second main electrode as a back electrode of the vertical semiconductor device, and formed on the fifth semiconductor region and connected to the second main electrode And a second sub-electrode, and a seventh semiconductor region of a second conductivity type connected to the second sub-electrode and formed in a surface layer of the fifth semiconductor region.

According to any one of claims 1 to 3, characterized in that said fifth semiconductor region via an insulating film wherein the first main electrodes second sub electrodes are formed opposite Semiconductor device.

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type connected to the second semiconductor region disposed in the ring and formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region A fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eighth semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, and an outermost periphery A sixth semiconductor region of a first conductivity type formed between a fourth semiconductor region and an eighth semiconductor region formed in a surface layer of the second semiconductor region disposed in the second semiconductor region, and all the second semiconductors A region sandwiched between the fourth semiconductor region and the first semiconductor region A main gate electrode formed in a region through a gate insulating film; a sub-gate electrode formed through a gate insulating film on a region sandwiched between the eighth semiconductor region and the sixth semiconductor region; 4 comprises a first main electrode formed on the semiconductor region, and a second main electrode of the back electrode prior Kitate type semiconductor device,
The eighth semiconductor region includes a first conductivity type annular ninth semiconductor region and a second conductivity type annular tenth semiconductor region which are alternately formed on the surface layer of each semiconductor region, and the uppermost stage. A semiconductor device comprising: a second sub-electrode formed on a ninth semiconductor region formed on the substrate and connected to the second main electrode.

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type that is formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region, separated from the second semiconductor region disposed in A fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eighth semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, and an outermost periphery a sixth semiconductor region of a first conductivity type opposite to is formed on the surface layer of the third semiconductor region to said second semiconductor region disposed in a fourth semiconductor region of all of the second semiconductor region A region sandwiched between the first semiconductor regions via a gate insulating film A main gate electrode formed; a sub-gate electrode formed on a region sandwiched between the eighth semiconductor region and the sixth semiconductor region through a gate insulating film; and formed on the fourth semiconductor region. comprising a first main electrode, a second main electrode of the back electrode prior Kitate type semiconductor device,
The eighth semiconductor region is composed of an annular first semiconductor region of the first conductivity type and an annular tenth semiconductor region of the second conductivity type that are alternately formed on the surface layer of each semiconductor region, and is exposed. A semiconductor device comprising a second sub-electrode formed on a ninth semiconductor region and connected to the second main electrode.

The semiconductor device according to claim 5, wherein the first main electrode and the second sub electrode are formed on the ninth semiconductor region so as to face each other with an insulating film interposed therebetween.

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type connected to the second semiconductor region disposed in the ring and formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region A fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eleventh semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, and an outermost periphery A sixth semiconductor region of the first conductivity type formed between the fourth semiconductor region formed in the surface layer of the second semiconductor region and the eleventh semiconductor region disposed in the second semiconductor region, and all the second semiconductor regions Sandwiched between the fourth semiconductor region and the first semiconductor region A main gate electrode formed in a region through a gate insulating film; a sub-gate electrode formed through a gate insulating film on a region sandwiched between the eleventh semiconductor region and the sixth semiconductor region; 4 comprising a first main electrode formed on the semiconductor region and a second main electrode as a back electrode of the vertical semiconductor device;
The eleventh semiconductor region is alternately formed in the annular longitudinal direction in contact with each other in the annular longitudinal direction of the third semiconductor region, and the 12th semiconductor region of the first conductivity type and the 13th semiconductor of the second conductivity type. And a second sub-electrode formed on the twelfth semiconductor region and connected to the second main electrode.

In a vertical semiconductor device having an insulated gate structure, a first semiconductor region of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type formed on a surface layer of the first semiconductor region, and an outermost periphery A third semiconductor of a second conductivity type that is formed in an annular shape surrounding the second semiconductor region in a surface layer of the first semiconductor region outside the second semiconductor region, separated from the second semiconductor region disposed in A fourth semiconductor region of the first conductivity type formed in the surface layer of all the second semiconductor regions, an eleventh semiconductor region formed in an annular shape in the surface layer of the third semiconductor region, and an outermost periphery A sixth semiconductor region of a first conductivity type formed in a surface layer of the third semiconductor region so as to face the second semiconductor region disposed on the fourth semiconductor region; and the fourth semiconductor regions of all the second semiconductor regions; A gate insulating film is interposed in the region sandwiched between the first semiconductor regions. A main electrode formed on the fourth semiconductor region, a sub-gate electrode formed on a region sandwiched between the eleventh semiconductor region and the sixth semiconductor region via a gate insulating film, and a fourth electrode formed on the fourth semiconductor region. 1 main electrode and a second main electrode as a back electrode of the vertical semiconductor device,
The eleventh semiconductor region is alternately formed in the annular longitudinal direction in contact with each other in the annular longitudinal direction of the third semiconductor region, and the 12th semiconductor region of the first conductivity type and the 13th semiconductor of the second conductivity type. And a second sub-electrode formed on the twelfth semiconductor region and connected to the second main electrode.

10. The semiconductor device according to claim 8, wherein the first main electrode and the second sub-electrode are formed on the eleventh semiconductor region so as to face each other with an insulating film interposed therebetween.