JPS6115365A - Transistor - Google Patents
TransistorInfo
- Publication number
- JPS6115365A JPS6115365A JP13696284A JP13696284A JPS6115365A JP S6115365 A JPS6115365 A JP S6115365A JP 13696284 A JP13696284 A JP 13696284A JP 13696284 A JP13696284 A JP 13696284A JP S6115365 A JPS6115365 A JP S6115365A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- region
- electrode
- base
- emitter electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はトランジスタ、特に高電流容量化を図ったトラ
ンジスタの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in transistors, particularly transistors with increased current capacity.
（ロ）従来の技術
従来よりトランジスタの電流容量の増大を図る構造とし
てはエミッタの有効面積を増大させることが知られてい
る。この構造としては第２図に示 ′スメッシュベー
ス構造あるいは島状エミッタ構造がある。第２図におい
て、（１）は半導体基板より成るコレクタ領域、（２）
はベース領域、（３）は島状エミッタ領域であり、点線
で示す（４）はベース領域（２）にオーミック接触した
ベース電極、（５１は各島状エミッタ領域（３）・・・
（３）にオーミック接触したエミッタ電極である。(b) Prior Art Conventionally, it has been known that a structure for increasing the current capacity of a transistor is to increase the effective area of the emitter. This structure includes a smesh base structure or an island emitter structure as shown in FIG. In Figure 2, (1) is a collector region made of a semiconductor substrate, (2)
(3) is the base region, (3) is the island-shaped emitter region, (4) indicated by a dotted line is the base electrode in ohmic contact with the base region (2), (51 is each island-shaped emitter region (3)...
(3) is an emitter electrode in ohmic contact with.
斯上の構造では多数の島状エミッタ領域（３）・・・（
３）によりベースエミッタ接合の周辺長を増大でき高電
流容量化を容易に達成できる。しかしながら第２図から
も明らかな様に島状エミッタ領域（３）・・・（３）の
面積の増加とともにメツシュ状のベース領域（２）の面
積も増加して、チップ面積の増加となる。ところがベー
ス電極にはコレクタ電流の１／ｈ、いの電流しか流れな
いので、ベース領域（２）の増加はトランジスタの高電
流容量化にほとんど寄与しない。In the above structure, a large number of island-like emitter regions (3)...(
By 3), the peripheral length of the base-emitter junction can be increased and a high current capacity can be easily achieved. However, as is clear from FIG. 2, as the area of the island-shaped emitter regions (3)...(3) increases, the area of the mesh-shaped base region (2) also increases, resulting in an increase in the chip area. However, since only 1/h of the collector current flows through the base electrode, increasing the base region (2) hardly contributes to increasing the current capacity of the transistor.
そこで第３図に示す様にメツシュエミッタ構造のトラン
ジスタが考えられた。第３図に於いて、Ｏｏｌは半導体
基板より成るコレクタ領域、ａｌｌはベース領域、０２
はメツシュ状のエミッタ領域であり、点線で示す０はエ
ミッタ領域ａカにオーミック接触したエミッタ電極、■
は点在するベース領域（１１）にオーミック接触したベ
ース電極である。Therefore, a transistor with a mesh emitter structure as shown in FIG. 3 was considered. In FIG. 3, Ool is a collector region made of a semiconductor substrate, all is a base region, and 02
is a mesh-like emitter region, 0 shown by a dotted line is an emitter electrode in ohmic contact with the emitter region a,
is a base electrode in ohmic contact with the scattered base regions (11).
斯上の構造ではメツシュ状エミッタ領域（１２によりエ
ミッタ面積の増大のみを図ることができるので、チップ
面積の増大防止にはかなり有効である。In the above structure, only the emitter area can be increased by the mesh-like emitter region (12), which is quite effective in preventing an increase in the chip area.
しかしながら第３図からも明らかな様にエミッタ電極（
１３１とベース電極ａ１１１を櫛歯状に形成するために
エミッタ電極（１阻マメツシユ状エミッタ領域ａ２の約
半分の面積としかオーミック接触を行なＬず、エミッタ
領域（１２１の面積の増大は実現されるがエミッタ電極
（２）の面積の増大は図れないのである。従ってメツシ
ュ状エミッタ領域Ｃ１２１を十分に活用できず結局メツ
シュ状エミッタ領域ａ２１は電流容量の増加の上では十
分に働いていないのである。However, as is clear from Figure 3, the emitter electrode (
In order to form the emitter electrode (131) and the base electrode (a111) in a comb-like shape, ohmic contact is made with only about half the area of the emitter region (a2), and an increase in the area of the emitter region (121) is not achieved. However, the area of the emitter electrode (2) cannot be increased.Therefore, the mesh-like emitter region C121 cannot be fully utilized, and in the end, the mesh-like emitter region A21 does not work sufficiently to increase the current capacity. .
そこで更に改良を重ね、第４１何）（ロ）に示す様に多
層電極構造のメツシュエミッタを有するトランジスタを
考えた。斯るトランジスタはシリコン半導体基板より成
るコレクタ領域■と、ベース領域（２１＋と、メツシュ
状のエミッタ領域（２ｚとを備え、エミッタ領域のはベ
ース領域ＣＤのほぼ全表面に配置され、ベース領域（２
１１のコンタクト領域（２）・・・（ハ）は多数島状に
エミッタ領域（２２内にエミッタ領域（２２に完全に囲
まれて配置されている。基板■表面のシリコン酸化膜（
２４）上には点線で示す一層目の第１ベース電極□□□
と第１エミッタ雷極■が形成され、第１ベース電極（ハ
）はベース領域（２１１の各コンタクト領域（ハ）・・
・（ハ）にオーミックコンタクトし多数の島状ケなし、
第１エミッタ電極（財）はエミッタ領域（２２１のほぼ
全表面とオーミックコンタクトしてメツシュ状をなして
いる。第１ベース電極（ハ）および第１エミッタ電極＠
はポリイミド等の層間絶縁膜（ロ）で被覆され、層間絶
縁膜０７）上には一点破線で示す二層目の第２ベース電
極（ハ）および第２エミッタ電極翰が形成される。第２
ベース電極（至）は島状に散在した多 −数の第１ベー
ス電極（ハ）・・・（ハ）に夫々オーミックコンタクト
し、櫛歯状に一方向に延在されて形成される。第２エミ
ッタ電極翰はメツシュ状の第１エミッタ電極（財）の斜
線で示す外周部でオーミックコンタクトし、ポンプイン
グツくラドまで延在されて−する。Therefore, further improvements were made, and a transistor having a mesh emitter with a multilayer electrode structure was devised as shown in No. 41 (b). Such a transistor has a collector region (2) made of a silicon semiconductor substrate, a base region (21+), and a mesh-like emitter region (2z).
The contact regions (2)...(c) of 11 are arranged in the form of multiple islands, completely surrounded by emitter regions (22).
24) Above is the first base electrode of the first layer indicated by the dotted line □□□
and a first emitter electrode (C) are formed, and the first base electrode (C) is connected to the base region (each contact region (C) of 211).
・No ohmic contact with (c) and many islands,
The first emitter electrode (F) is in ohmic contact with almost the entire surface of the emitter region (221) to form a mesh shape.The first base electrode (C) and the first emitter electrode @
is covered with an interlayer insulating film (b) made of polyimide or the like, and a second base electrode (c) and a second emitter electrode of the second layer shown by dotted lines are formed on the interlayer insulating film (07). Second
The base electrodes (1) are formed in ohmic contact with a large number of first base electrodes (3), . The second emitter electrode is in ohmic contact with the mesh-shaped first emitter electrode at its outer periphery shown by diagonal lines, and is extended to the pumping hole.
０４ 発明が解決しようとする問題点斯上の構造に依
ればメツシュ状エミッタ領域（２２のほぼ全面に第１エ
ミッタ電極轍を配置できるので、メツシュ状エミッタ領
域（２２を効率よく動作させることができ電流容量の増
大を図れる。しかし多層電極構造を採る場合、第１エミ
ッタ電極（２６）の厚みを厚く形成すると第１層目電極
の段差が大きくなり第２層目電極の形成上好ましくない
。そのため第１エミッタ電極（ハ）の厚みを一定以上厚
くできず、大電流を流すと第１エミッタ電極（財）の外
周部に設けた第２エミッタ電極翰とのコンタクト部分で
電流集中により破壊される欠点があった。04 Problems to be Solved by the Invention According to the above structure, it is possible to arrange the first emitter electrode track on almost the entire surface of the mesh-like emitter region (22), so that it is possible to efficiently operate the mesh-like emitter region (22). However, when adopting a multilayer electrode structure, forming the first emitter electrode (26) thickly increases the step difference in the first layer electrode, which is not preferable in terms of forming the second layer electrode. For this reason, the thickness of the first emitter electrode (c) cannot be made thicker than a certain level, and when a large current is applied, the contact area with the second emitter electrode provided on the outer periphery of the first emitter electrode (c) is destroyed due to current concentration. There were some drawbacks.
に）問題点を解決するための手段
本発明は上記した欠点に鑑みてなされ、第２エミッタ電
極翰を第１エミッタ電極（ハ）と外周部だけでなく内部
でもコンタクトさせることにより従来の欠点を大巾に改
善するものである。B) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and it overcomes the drawbacks of the conventional art by bringing the second emitter electrode into contact with the first emitter electrode (c) not only on the outer periphery but also on the inside. This is a major improvement.
（ホ）作用
本発明では第２エミッタ電極翰の第１エミッタ電極■ど
のオーミックコンタクトを帯状に多数設けて電流の分散
を図り、電流集中による破壊を防止するものである。(E) Function In the present invention, a large number of ohmic contacts are provided in a band shape between the first emitter electrode and the second emitter electrode to distribute the current and prevent damage caused by current concentration.
（へ）実施例
本発明によるメツシュエミッタ構造のトランジスタを第
１図（イ）（ロ）に示す。なお図番は第４図（イ）（ロ
）と共通とした。(F) Embodiment A transistor having a mesh emitter structure according to the present invention is shown in FIGS. The drawing numbers are the same as those in Figure 4 (a) and (b).
本発明に依るトランジスタはシリコン半導体基板より成
るコレクタ領域■と、ベース領域ＣＬｌと、メツシュ状
のエミッタ領域（２′；Ａとを備え、エミッタ領域（２
ｚはベース領域ｅ９のほぼ全表面に配置され、ベース領
域（２１）のコンタクト領域（ハ）・・・（ハ）は多数
島状にエミッタ領域器内にエミッタ領域Ｑ２に完全に囲
まれて配置されている。基板艶表面のシリコン酸化膜（
財）上には点線で示す一層目の第１ベース電極（ハ）と
第１エミッタ電極罷が形成され、第１ベース電極（２（
ト）はベース領域（２１１の各コンタクト領域（２＋・
・・０３１にオーミックコンタクトし多数の島状をなし
、第１エミッタ電極ｅ０はエミッタ領域（２２）のほぼ
全表面とオーミックコンタクトしてメツシュ状をなして
いる。第１ベース電極（２９および第１エミッタ電極（
２６）はポリイミド等の層間絶縁膜（５）で被覆され、
層間絶縁膜（５）上には一点破線で示す二層目の第２ベ
ース電極□□□および第２エミッタ電極翰が形成される
。第２ベース電極ｅ印は島状に散在した多数の第１ベー
ス電極（２９・・・（至）に夫々オーミックコンタクト
して櫛歯状に一方向に延在・されて形成されている。The transistor according to the present invention includes a collector region (2) made of a silicon semiconductor substrate, a base region (CLl), and a mesh-like emitter region (2'; A).
z is arranged on almost the entire surface of the base region e9, and the contact regions (c)...(c) of the base region (21) are arranged in the form of multiple islands in the emitter region completely surrounded by the emitter region Q2. has been done. Silicon oxide film on the glossy surface of the substrate (
A first base electrode (c) and a first emitter electrode strip of the first layer shown by dotted lines are formed on the first base electrode (2 (
) is the base region (each contact region (2+) of 211
The first emitter electrode e0 is in ohmic contact with substantially the entire surface of the emitter region (22) to form a mesh shape. The first base electrode (29) and the first emitter electrode (
26) is covered with an interlayer insulating film (5) such as polyimide,
On the interlayer insulating film (5), a second base electrode □□□ and a second emitter electrode of the second layer are formed, which are indicated by dotted lines. The second base electrodes marked e are formed in ohmic contact with a large number of first base electrodes (29...) scattered in the form of islands, extending in one direction in a comb-like shape.
本発明の特徴は第２エミッタ電極（ハ）の形状にある。The feature of the present invention lies in the shape of the second emitter electrode (c).
第２エミッタ電極翰は第１エミ多夕電極（２６）と斜線
で示す様に櫛歯状に延在された第２ベース電極□□□間
で帯状にオーミックコンタクトしており、第２エミッタ
電極翰は第２ベース電極（至）と入り組んで櫛歯状に形
成されポンディングパッドまで延在されている。斯る第
２エミッタ電極翰は従来のものに比較して第１エミッタ
電極（イ）とコンタクト面積を大巾に増大でき、第１エ
ミッタ電極翰の電流を分散させて第２エミッタ電極（２
特に取り出すことができる。この結果第２エミッタ電極
（２！１の電流集中を抑制でき、破壊に強い構造となる
。The second emitter electrode wire is in ohmic contact with the first emitter electrode (26) in a band shape between the second base electrode □□□ extending in a comb-like shape as shown by diagonal lines, and the second emitter electrode The wire is intricately formed into a comb-teeth shape with the second base electrode (toward), and extends to the bonding pad. Such a second emitter electrode can greatly increase the contact area with the first emitter electrode (A) compared to the conventional one, and can spread the current of the first emitter electrode (A) to the second emitter electrode (2).
Especially if you can take it out. As a result, current concentration on the second emitter electrode (2!1) can be suppressed, resulting in a structure that is resistant to destruction.
第５図に２５Ｖ系１．２朋角チツプの安全動作領域を示
す。実線は従来の第４図（イ）（ロ）の構造の特性であ
り、点線は本発明の構造の特性である。本発明では熱抵
抗領域でＡＳＯ特性の大巾な拡大を図ることができる。FIG. 5 shows the safe operating area of a 25V 1.2 mm square chip. The solid line is the characteristic of the conventional structure shown in FIGS. 4(a) and 4(b), and the dotted line is the characteristic of the structure of the present invention. In the present invention, the ASO characteristics can be greatly expanded in the thermal resistance region.
（ト）発明の効果
本発明に依れば、第２エミッタ電極（２特と第１エミッ
タ電極（２６）とのコンタク、ト面積の増大を図ること
により、電流容量の増加を更に実現できる。この結果小
さいチップ面積で高電流容量化を図れるので極めて生産
効率のよいトランジスタを提供できる。(G) Effects of the Invention According to the present invention, it is possible to further increase the current capacity by increasing the contact area between the second emitter electrode (26) and the first emitter electrode (26). As a result, a high current capacity can be achieved with a small chip area, making it possible to provide a transistor with extremely high production efficiency.
第１図（イ）は本発明に依るトランジスタを説明する上
面図、第１図（ロ）は第１図（イ）のＩ−Ｉ線断面図、
第２図は従来のメッシュベース構造のトランジスタを説
明する上面図、第３図は従来のメツシュエミッタ構造の
トランジスタを説明する上面図、第、４図（イ）は従来
の更に改良したメツシーエミッタ構造のトランジスタを
説明する上面図、第４図Ｃ口）は第４図（イ）のＩＶ−
ＩＶ線断面図、第５図は従来と本発明の安全動作領域を
説明する特性図である。
主な図番の説明
（２０１は半導体基板、（２１１はベース領域、（２２
はメツシュ状エミッタ領域、（２つは第１ベース電極、
（イ）は第１エミッタ電極、（２暗主第２ベース電極、
（２９）は第２エミッタ電極である。
出願人 三洋電機株式会社 外１名
代理人 弁理士 佐 野 静 夫
第１図（イ）
ｒ−−’−−−’、−−ｍ
第１図Ｃ口）
第３図
第 ４ 図（ロ）FIG. 1(a) is a top view illustrating a transistor according to the present invention, FIG. 1(b) is a cross-sectional view taken along the line II in FIG. 1(a),
Fig. 2 is a top view illustrating a conventional mesh base structure transistor, Fig. 3 is a top view illustrating a conventional mesh emitter structure transistor, and Figs. A top view explaining a transistor with an emitter structure, Figure 4 (C) is IV- in Figure 4 (A).
FIG. 5, a sectional view taken along the line IV, is a characteristic diagram illustrating the safe operation area of the conventional device and the present invention. Explanation of main figure numbers (201 is the semiconductor substrate, (211 is the base region, (22
are mesh-like emitter regions, (two are the first base electrodes,
(a) is the first emitter electrode, (2 dark main second base electrode,
(29) is the second emitter electrode. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano Figure 1 (a) r--'----', --m Figure 1 C) Figure 3 Figure 4 (b)
Claims (1)
備え、該エミッタ領域を前記ベース領域表面にメッシュ
状に設け、前記ベース領域のコンタクト領域を前記エミ
ッタ領域内に多数島状に配置し、前記エミッタ領域およ
び前記ベース領域のコンタクト領域にオーミック接触す
る第１層目より成る第１エミッタ電極と第１ベース電極
を設け、該第１エミッタ電極および第１ベース電極を被
覆する層間絶縁膜上に前記第１ベース電極を連結する櫛
歯状の第２ベース電極と該第２ベース電極の櫛歯間に設
け前記第１エミッタ電極に帯状にコンタクトする第２エ
ミッタ電極とを設けたことを特徴とするトランジスタ。(1) A collector region, a base region, and an emitter region are provided, the emitter region is provided in a mesh shape on the surface of the base region, the contact regions of the base region are arranged in a plurality of islands in the emitter region, and the emitter region and a first emitter electrode and a first base electrode made of a first layer in ohmic contact with the contact region of the base region, and the first emitter electrode and the first base electrode are provided on an interlayer insulating film covering the first emitter electrode and the first base electrode. A transistor comprising: a comb-shaped second base electrode that connects base electrodes; and a second emitter electrode that is provided between the comb-teeth of the second base electrode and contacts the first emitter electrode in a strip shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13696284A JPS6115365A (en) | 1984-07-02 | 1984-07-02 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13696284A JPS6115365A (en) | 1984-07-02 | 1984-07-02 | Transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6115365A true JPS6115365A (en) | 1986-01-23 |
Family
ID=15187556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13696284A Pending JPS6115365A (en) | 1984-07-02 | 1984-07-02 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6115365A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62244172A (en) * | 1986-04-17 | 1987-10-24 | Sanyo Electric Co Ltd | Transistor |
| JPS62244171A (en) * | 1986-04-17 | 1987-10-24 | Sanyo Electric Co Ltd | Transistor |
| US5554880A (en) * | 1994-08-08 | 1996-09-10 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
| US5932922A (en) * | 1994-08-08 | 1999-08-03 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056177A (en) * | 1973-09-14 | 1975-05-16 | ||
| JPS57181160A (en) * | 1981-04-30 | 1982-11-08 | Sanyo Electric Co Ltd | Transistor |
-
1984
- 1984-07-02 JP JP13696284A patent/JPS6115365A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5056177A (en) * | 1973-09-14 | 1975-05-16 | ||
| JPS57181160A (en) * | 1981-04-30 | 1982-11-08 | Sanyo Electric Co Ltd | Transistor |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62244172A (en) * | 1986-04-17 | 1987-10-24 | Sanyo Electric Co Ltd | Transistor |
| JPS62244171A (en) * | 1986-04-17 | 1987-10-24 | Sanyo Electric Co Ltd | Transistor |
| US5554880A (en) * | 1994-08-08 | 1996-09-10 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
| US5932922A (en) * | 1994-08-08 | 1999-08-03 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
| US6103584A (en) * | 1994-08-08 | 2000-08-15 | Semicoa Semiconductors | Uniform current density and high current gain bipolar transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2919257B2 (en) | Multilayer wiring semiconductor device | |
| JPH0414511B2 (en) | ||
| US5633525A (en) | Lateral field effect transistor | |
| JP2003174169A (en) | Semiconductor device | |
| US8004008B2 (en) | Semiconductor device | |
| JP4230681B2 (en) | High voltage semiconductor device | |
| JPH03211771A (en) | Conductivity-modulation mosfet | |
| JPS6115365A (en) | Transistor | |
| JP4577480B2 (en) | Insulated gate semiconductor device | |
| KR100333107B1 (en) | Semiconductor device | |
| JP3510797B2 (en) | Transistor electrode structure | |
| JPH07263665A (en) | Semiconductor device | |
| JP5341435B2 (en) | Semiconductor device | |
| JPH0150115B2 (en) | ||
| JPH0427711B2 (en) | ||
| JP3213507B2 (en) | Semiconductor device | |
| JPH01262654A (en) | Semiconductor device | |
| JP2525558Y2 (en) | Semiconductor device | |
| JPH0611052B2 (en) | Transistor | |
| JP2523966B2 (en) | Semiconductor device | |
| JPS6313352B2 (en) | ||
| JPS62244169A (en) | Transistor | |
| JPH0438520Y2 (en) | ||
| JP2892673B2 (en) | Semiconductor device | |
| JP2802940B2 (en) | Semiconductor device |