KR100299885B1 - Semiconductor device and method for producing the same - Google Patents

Semiconductor device and method for producing the same Download PDF

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KR100299885B1
KR100299885B1 KR19980013880A KR19980013880A KR100299885B1 KR 100299885 B1 KR100299885 B1 KR 100299885B1 KR 19980013880 A KR19980013880 A KR 19980013880A KR 19980013880 A KR19980013880 A KR 19980013880A KR 100299885 B1 KR100299885 B1 KR 100299885B1
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substrate
semiconductor chip
substrates
chip
semiconductor device
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KR19980081522A (en
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노부아끼 다까하시
요시따까 교우고꾸
가쓰마사 하시모또
신이찌 미야자끼
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가네꼬 히사시
닛뽕덴끼 가부시끼가이샤
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Abstract

반도체 칩 (2) 이 플립칩으로 탑재된 복수의 기판 (1) 을 적층을 위하여 제공된 솔더 범프 (7) 에 의해 적층한다. 칩의 상부면 (9) 과 기판 (1) 사이의 공간을 유연성 수지로 충전하여, 완충재층 (8) 을 형성한다. 이러한 유형의 3 차원 반도체 모듈 구조를 채택함으로서, 외부에서 가해지는 충격과 진동을 완충재층 (8) 이 흡수하여, 내충격성과 내진동성을 향상시킨다.The plurality of substrates 1 on which the semiconductor chips 2 are mounted with flip chips are laminated by solder bumps 7 provided for lamination. The space between the upper surface 9 of the chip and the substrate 1 is filled with a flexible resin to form the buffer layer 8. By adopting this type of three-dimensional semiconductor module structure, the shock absorbing material layer 8 absorbs external shocks and vibrations, thereby improving impact resistance and vibration resistance.

Description

반도체 장치 및 그의 제조방법{SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME}Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME}

본 발명은 반도체 장치에 관한 것으로, 보다 상세하게는 베어칩 (bare chip)을 탑재한 기판의 3 차원 적층구조를 갖는 반도체 장치에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a three-dimensional stacked structure of a substrate on which a bare chip is mounted.

반도체 칩, 특히 반도체 메모리 장치의 패키지에 있어서, 보다 더 높은 고밀도화, 소형화(compactness) 및 대용량화을 달성하기 위해, 3 차원으로 칩을 적층하는 방법이 널리 사용되고 있다. 이러한 구조를 사용함으로서, 실장면적을 크게 줄일 수 있다.In the packaging of semiconductor chips, especially semiconductor memory devices, a method of stacking chips in three dimensions is widely used to achieve higher density, compactness, and large capacity. By using such a structure, the mounting area can be greatly reduced.

그러나, 3 차원으로 칩을 적층하면, 열팽창 계수의 차이 때문에, 열이력에 의해 발생하는 응력 (stress), 변형 (strain) 및 후속 불량 접속이 발생할 수 있다. 따라서, 이러한 방법을 우주선에 적용하는 경우, 내충격성 (耐衝擊性) 및 내진동성 (耐振動性) 을 고려해야 하므로, 이에 대한 몇 가지 방법이 제안되었다.However, stacking chips in three dimensions can cause stresses, strains and subsequent poor connections caused by thermal history due to differences in thermal expansion coefficients. Therefore, when such a method is applied to a spacecraft, it is necessary to consider impact resistance and vibration resistance, so several methods have been proposed.

예를 들어, 일본 특개평 6-275775 호에 개시되고, 도 3 에 도시된 바와 같이, TAB (tape automated bonding) 테이프에 칩 (2) 을 탑재하여, TAB 장치를 형성한 구조가 3 단 적층구조 (17A 내지 17C) 로 되어 있다.For example, disclosed in Japanese Patent Laid-Open No. 6-275775, and as shown in Fig. 3, a structure in which a chip 2 is mounted on a tape automated bonding (TAB) tape to form a TAB device is a three-stage laminated structure. (17A to 17C).

도 3 에서, 칩 (2) 은 범프 (13) 또는 플립칩 방법에 의해 리드 (lead; 11)에 접속되어 있고, 칩 (2) 의 TAB 테이프측의 부분은 보호수지 (12) 로 피복되어 있다. TAB 장치는 모듈 플레이트 (14) 에 탑재되어 있다. 모듈 플레이트 (14) 는 내열성이 높고 가급적 열전도성이 양호한 재료로 이루어진다.In Fig. 3, the chip 2 is connected to the lead 11 by the bump 13 or flip chip method, and the portion on the TAB tape side of the chip 2 is covered with the protective resin 12. . The TAB apparatus is mounted on the module plate 14. The module plate 14 is made of a material having high heat resistance and preferably good thermal conductivity.

TAB 장치를 모듈 플레이트 (14) 에 탑재하는 경우, 모듈 프레이트 (14) 의 요부 (凹部; depresssin) (15) 내에 열전도성이 양호한 접착재 (6) 를 사용하여 TAB 장치를 탑재함으로써, 칩 (2) 의 배면을 요부 (15) 의 내면과 접촉시킨다. TAB 장치 중 리드 (11) 의 외측 (outer) 리드부를 모듈 플레이트 (14) 의 외측면에 있는 접속 패턴에 접속시켜, TAB 장치와 모듈 플레이트 (14) 로 구성된 모듈 유니트 (17A∼17C) 를 형성한다.When the TAB device is mounted on the module plate 14, the chip 2 is mounted by mounting the TAB device using the adhesive material 6 having good thermal conductivity in the depresssin 15 of the module plate 14. The back side of the contact with the inner surface of the recess (15). The outer lead portion of the lead 11 of the TAB apparatus is connected to the connection pattern on the outer surface of the module plate 14 to form module units 17A to 17C composed of the TAB apparatus and the module plate 14. .

복수의 모듈 유니트 (17A∼17C) 사이에 완충부재 (18) 를 개재하여 서로 적층시킨다. 완충부재 (18) 는 이방성 도전수지 또는 이방성 도전고무로 이루어지고, 상하 방향으로만 도전성이 있기 때문에, 적층된 모듈 유니트들을 전기적으로 접속시킨다. 상술된 구조에 의해, 완충부재 (18) 가 외부에서 인가된 충격과 진동을 흡수하여, 장치의 내진동성을 향상시킬 수 있다.The plurality of module units 17A to 17C are laminated to each other with a buffer member 18 interposed therebetween. Since the shock absorbing member 18 is made of an anisotropic conductive resin or an anisotropic conductive rubber and is conductive only in the up and down direction, the laminated module units are electrically connected. By the above-described structure, the shock absorbing member 18 can absorb the shock and vibration applied from the outside, thereby improving the vibration resistance of the apparatus.

일본 특개평 2-42739 호에 다른 종래의 기술이 개시되어 있다. 도 4a 에 도시된 바와 같이, 절연기판 (1) 상에 유연성 접착제층 (20) 을 형성하고, 유연성 접착제층 (20) 상에 패드 (21) 와 배선패턴을 형성한다. 다음으로, 범프 (22) 에 의해 패드 (21) 상에 칩 (2) 을 접속시킨다.Japanese Patent Laid-Open No. 2-42739 discloses another conventional technique. As shown in FIG. 4A, the flexible adhesive layer 20 is formed on the insulating substrate 1, and the pad 21 and the wiring pattern are formed on the flexible adhesive layer 20. Next, the chip 2 is connected to the pad 21 by the bumps 22.

도 4b 에 도시된 바와 같이, 절연기판 (1) 상에 유연성 접착제층 (20) 을 형성한 후, 패드 (21) 와 배선패턴을 제외한 부분들을 에칭에 의해 제거한다. 그 다음에, 범프 (22) 에 의해 남아있는 패드 (21) 상에 칩 (2) 을 접속시킨다.As shown in FIG. 4B, after the flexible adhesive layer 20 is formed on the insulating substrate 1, portions other than the pad 21 and the wiring pattern are removed by etching. Then, the chip 2 is connected on the pad 21 remaining by the bumps 22.

상술한 바와 같은 구조를 채택함으로서, 칩 (2) 과 기판 (1) 사이에 개재된 유연성 접착제층 (20) 이 완충층으로서 작용하여, 그들간의 접속 신뢰성을 향상시킨다.By adopting the structure as described above, the flexible adhesive layer 20 interposed between the chip 2 and the substrate 1 acts as a buffer layer, thereby improving connection reliability therebetween.

일본 특개평 6-275775 호에 개시된 종래 기술에서, 모듈 유니트들을 적층시켜 그들간의 전기적 접속을 위한 물질로서 이방성 도전수지 또는 이방성 도전고무를 사용한다. 일반적으로, 이방성 도전수지 또는 이방성 도전고무는 금속에 비해 전기저항이 커서, 특히 메모리 칩들에 저전압 용도로 적용하기 어려운 문제점을 갖는다.In the prior art disclosed in Japanese Patent Laid-Open No. 6-275775, anisotropic conductive resin or anisotropic conductive rubber is used as a material for stacking module units and making an electrical connection therebetween. In general, anisotropic conductive resins or anisotropic conductive rubbers have a large electrical resistance compared to metals, and thus have difficulty in applying low voltage applications to memory chips.

일본 특개평 2-42739 호에 개시된 종래 기술에서는, 기판과 칩 사이를 접속하는데 솔더 (solder) 를 사용하지만, 실제로 그들간의 확실한 접속을 위하여 플럭스 (flux) 를 사용한다. 그러나, 플럭스내에 함유되어 있는 할로겐 이온이 잔류하면, 베어칩에 악영향을 미치는 문제가 있다.In the prior art disclosed in Japanese Patent Laid-Open No. 2-42739, solder is used for connecting between the substrate and the chip, but in practice, flux is used for reliable connection between them. However, if halogen ions contained in the flux remain, there is a problem of adversely affecting the bare chip.

이 때문에, 우주선에서 사용되는 정밀기기에서는 솔더의 사용을 피하고, 플럭스를 필요로 하지 않는 금 등의 재료를 사용하는 것이 바람직하다. 금으로 만들어진 범프들을 사용하여 플립칩 접속을 행하는 경우, 가열 뿐만 아니라 힘과 진동을 가하는 것은 필수이다. 이것이 행해질 때, 확실한 접속을 달성하기 위하여, 어느 정도의 경도 (hardness) 를 갖는 랜드 (land) 가 요구된다.For this reason, it is desirable to avoid the use of solder in precision instruments used in spacecraft and to use materials such as gold that do not require flux. In the case of flip chip connection using bumps made of gold, it is necessary to apply force and vibration as well as heating. When this is done, lands with some degree of hardness are required to achieve reliable connection.

그러나, 상술한 종래 기술에서는, 랜드 바로 하부에 있는 유연성 접착제로 인하여, 기판 상의 랜드와 금 등으로 만들어진 범프를 접속시키기 어렵다. 또한, 제조공정이 복잡하고 비용도 높다.However, in the above-described prior art, due to the flexible adhesive directly under the land, it is difficult to connect the bump on the substrate with the bump made of gold or the like. In addition, the manufacturing process is complicated and the cost is high.

상술한 종래기술의 결점을 고려하여, 본 발명의 목적은 내충격성과 내진동성을 향상시킬 수 있는 극히 간단한 구조를 갖는 반도체 장치를 제공하는 것이다.In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor device having an extremely simple structure capable of improving impact resistance and vibration resistance.

따라서, 본 발명의 목적은, 복수의 기판을 적층하는 경우, 접속부를 비교적 낮은 레벨의 저항값으로 형성하여 비교적 낮은 전압레벨로 구동할 수 있는 반도체 장치를 제공하는 것이다.It is therefore an object of the present invention to provide a semiconductor device capable of driving at a relatively low voltage level by forming a connection portion with a relatively low level of resistance value when laminating a plurality of substrates.

도 1 은 본 발명의 일 실시예에 따른 반도체 장치의 실장구조의 단면도;1 is a cross-sectional view of a mounting structure of a semiconductor device according to an embodiment of the present invention;

도 2 는 본 발명의 다른 실시예에 따른 반도체 장치의 실장구조의 단면도;2 is a cross-sectional view of a mounting structure of a semiconductor device according to another embodiment of the present invention;

도 3 은 종래 기술에서의 반도체 장치의 실장구조의 단면도;3 is a cross-sectional view of a mounting structure of a semiconductor device in the prior art;

도 4 는 종래 기술에서의 반도체 장치의 실장구조의 단면도.4 is a cross-sectional view of a mounting structure of a semiconductor device in the prior art.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1 : 기판 2 : 칩1: substrate 2: chip

3 : 금범프 4 : 내부 패드3: gold bump 4: inner pad

5 : 외부패드 6 : 밀봉수지5: outer pad 6: sealing resin

7 : 범프 8 : 완충재층7: bump 8: buffer layer

상술한 본 발명의 목적을 달성하기 위하여, 본 발명은 복수개의 기판이 적층되고 서로 전기적으로 상호 접속되어 있는 적층구조를 구비하는 반도체 장치로서, 기판의 표면 중 일 표면 상에 반도체 칩이 탑재되어 있으며, 이 적층구조는 반도체 칩의 상부면과 이 면에 대향하는 기판의 다른 표면 사이에 배치되어 충격과 진동을 흡수할 수 있는 완충재를 구비한다.In order to achieve the object of the present invention described above, the present invention is a semiconductor device having a laminated structure in which a plurality of substrates are stacked and electrically interconnected with each other, the semiconductor chip is mounted on one surface of the substrate The laminated structure is provided with a buffer material which is disposed between the upper surface of the semiconductor chip and another surface of the substrate opposite the surface to absorb shocks and vibrations.

그리고, 본 발명의 방법은 기판의 표면 중 일 표면 상에 반도체 칩이 탑재되어 있는 복수개의 기판이 적층되고 서로 전기적으로 상호 접속되어 있는 적층구조를 구비하는 반도체 장치를 제조하는 방법으로서, 반도체 칩의 표면상에 금속 범프를 형성하는 제 1 단계; 반도체 칩과 기판을 조립하도록 기판의 패드부를 금속으로 도포하는 제 2 단계; 플립칩 방법을 사용하여 반도체칩을 기판에 접속시키는 제 3 단계; 접속된 부분의 접속부를 밀봉수지로 밀봉하는 제 4 단계; 제 3 단계에서 각각 만들어지고 기판 사이에 솔더범프를 배치하여 복수개의 기판을 서로 적층하는 제 5 단계; 적층된 기판들을 서로 전기적으로 접속시키는 제 6 단계; 및 반도체 칩의 상부면과 기판의 다른 표면 사이에 충격과 진동을 흡수할 수 있는 완충재를 충전하는 제 7 단계를 구비한다.In addition, the method of the present invention is a method of manufacturing a semiconductor device having a laminated structure in which a plurality of substrates on which a semiconductor chip is mounted is laminated on one surface of the substrate and electrically connected to each other. Forming a metal bump on the surface; Applying a pad portion of the substrate with a metal to assemble the semiconductor chip and the substrate; A third step of connecting the semiconductor chip to the substrate using a flip chip method; A fourth step of sealing the connecting portion of the connected portion with a sealing resin; A fifth step of laminating a plurality of substrates by placing solder bumps between the substrates, each of which is made in a third step; A sixth step of electrically connecting the stacked substrates to each other; And a seventh step of filling a buffer material capable of absorbing shock and vibration between the upper surface of the semiconductor chip and the other surface of the substrate.

본 발명에 따른 반도체 장치는 적층구조로서, 칩들이 탑재되어 있는 제 1 기판과 제 2 기판을 구비하고, 제 2 기판은 제 1 기판상에 배치되며, 완충재는 제 1 기판 상에 있는 반도체 칩의 정면 (front surface) 과 제 2 기판의 이면 (rear surface) 사이에 제공된다.The semiconductor device according to the present invention has a stacked structure, comprising a first substrate and a second substrate on which chips are mounted, the second substrate is disposed on the first substrate, and the buffer material of the semiconductor chip is on the first substrate. It is provided between the front surface and the rear surface of the second substrate.

또한, 제 1 및 제 2 기판은 금속 전극인 범프들에 의해 상호 접속되고, 적층된 기판들 사이의 공간이 완충재로 충전된다.In addition, the first and second substrates are interconnected by bumps, which are metal electrodes, and the space between the stacked substrates is filled with a buffer material.

본 발명에 의하면, 칩이 적층되어 탑재된 기판들 사이에 유연성 완충재를 제공함으로써, 외부에서 가해지는 충격 및 진동을 흡수함으로써, 내충격성과 내진동성을 향상시킬 수 있는 효과가 있다.According to the present invention, by providing a flexible buffer between the substrate on which the chip is stacked, by absorbing the impact and vibration applied from the outside, there is an effect that can improve the impact resistance and vibration resistance.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1 은 본 발명의 일 실시예에 따른 반도체 장치의 실장구조를 나타낸 단면도이다. 이하, 도 1 을 참조하여 제조방법을 설명한다. 예를 들어, 알루미나 또는 세라믹 등으로 이루어진 내부 패드 (4) 와 배선 패턴이 형성되어 있는 기판 (1) 과, 금범프 (3) 가 형성되어 있는 칩 (2) 을 플립칩 접속한다. 금범프 (3) 는, 예를 들어 금와이어를 이용한 볼 (ball) 방법에 의해 제조한다.1 is a cross-sectional view illustrating a mounting structure of a semiconductor device in accordance with an embodiment of the present invention. Hereinafter, a manufacturing method will be described with reference to FIG. 1. For example, flip chip connection is performed between the internal pad 4 made of alumina or ceramic, the substrate 1 on which the wiring pattern is formed, and the chip 2 on which the gold bumps 3 are formed. Gold bump 3 is manufactured by the ball method using a gold wire, for example.

기판 (1) 측의 내부 패드 (4) 상에는, 금범프 (3) 에 의한 접속을 확실히 하기 위하여, 플레이팅 (plating) 또는 스퍼터링 중 하나의 방법으로 미리 1 내지 5 ㎛ 의 두께로 금을 형성한다. 플립칩 접속을 행하는 경우, 가열과 가압 또는 진동 등을 병용하여 열압착 (hot-press bond) 을 행한다. 그 다음에, 칩 (2) 과 기판 (1) 사이에 밀봉수지 (6) 를 주입하여, 금범프 (3) 의 접속부 (C) 를 수지 (6) 로 피복하고, 이 수지 (6) 를 경화하여 밀봉을 형성한다.On the inner pad 4 on the side of the substrate 1, gold is formed to a thickness of 1 to 5 mu m in advance by either plating or sputtering in order to ensure connection by the gold bumps 3. . When flip chip connection is performed, hot-press bond is performed using heating, pressurization, or vibration in combination. Then, the sealing resin 6 is injected between the chip 2 and the substrate 1, the connection portion C of the gold bump 3 is covered with a resin 6, and the resin 6 is cured. To form a seal.

그 다음에, 유연성을 갖는 완충재층 (8) 을 칩 상부면 (9) 상에 형성하고, 반경화(semi-cured)시킨다. 본 발명에서는 완충재로서 유연성을 갖는 실리콘 수지 또는 에폭시 수지 등을 사용한다. 칩 (2) 이 탑재된 기판 (1) 의 외부패드 (5) 상에, 적층용 범프 (7) 를 형성한다. 적층용 범프 (7) 는, 예를 들어 플럭스 등의 점성을 이용하여 외부패드 (5) 상에 납주석 솔더볼들을 배치하고, 그들을 가열, 융해시켜 형성한다. 범프 (7) 의 높이는 솔더볼 크기를 선택함으로써, 기판 (1) 표면에서부터 완충재층 (8) 표면까지의 높이 이상으로 형성한다.Next, a flexible buffer layer 8 is formed on the chip upper surface 9 and semi-cured. In the present invention, a silicone resin or epoxy resin having flexibility is used as the cushioning material. On the outer pad 5 of the substrate 1 on which the chip 2 is mounted, the bumps for lamination 7 are formed. The stacking bumps 7 are formed by arranging lead tin solder balls on the outer pad 5 using, for example, viscosity such as flux, and heating and melting them. By selecting the solder ball size, the height of the bump 7 is formed above the height from the surface of the substrate 1 to the surface of the buffer layer 8.

다음으로, 칩 (2) 이 탑재되어 있는 기판 (1) 을 복수개 적층시키고, 리플로우 (reflow) 에 의해 솔더를 융해시켜 일괄적으로 접속시킨다. 동시에, 완충재층 (8) 을 완전히 경화시켜, 도 1 에 도시된 바와 같은 반도체용 실장구조를 형성한다. 또한, 적층 공정 이후에 수지를 주입하여 완충재층 (8) 을 형성할 수도 있다.Next, the board | substrate 1 in which the chip 2 is mounted is laminated | stacked, and solder is melted by reflow, and it connects collectively. At the same time, the buffer material layer 8 is completely cured to form a semiconductor mounting structure as shown in FIG. The buffer material layer 8 may be formed by injecting a resin after the lamination step.

상술한 반도체 실장구조를 채택함으로서, 칩 상부면 (9) 과 기판 (1) 사이에 수지로 이루어진 유연성 완충재층 (8) 이 있기 때문에, 외부에서 가해지는 충격과 진동을 흡수하여, 내충격성과 내진동성을 향상시킨다. 또한, 기판 (1) 들을 금속 (솔더) 범프 (7) 에 의해 접속하기 때문에, 전기 저항도 낮다. 또한, 기판의 내부 패드 (4) 하부에 유연성층이 없기 때문에, 금 등으로 이루어진 범프들에 의해 칩 (2) 과 기판 (1) 을 양호하게 접속시킬 수 있다.By adopting the semiconductor mounting structure described above, since there is a flexible buffer layer 8 made of resin between the chip upper surface 9 and the substrate 1, it absorbs shocks and vibrations applied from the outside, and thus impact resistance and vibration resistance To improve. In addition, since the substrates 1 are connected by the metal (solder) bumps 7, the electrical resistance is also low. In addition, since there is no flexible layer under the inner pad 4 of the substrate, the chip 2 and the substrate 1 can be satisfactorily connected by bumps made of gold or the like.

이 실시예에서는 칩 (2) 을 기판 (1) 에 접속하는데 금범프를 사용하였지만, 솔더 범프 등도 사용할 수 있다.In this embodiment, although gold bumps were used to connect the chip 2 to the substrate 1, solder bumps and the like can also be used.

도 2 는 본 발명의 다른 실시예에 따른 반도체 장치의 실장구조를 나타낸 단면도이다. 내부 패드 (4) 와 배선패턴이 형성되어 있는 기판 (1) 과 칩 (2) 을 플립칩 접속한다. 금범프 (3) 에 의한 접속을 확실히 하기 위하여, 기판 (1) 의 내부 패드상에 플레이팅 또는 스퍼터링 중 하나의 방법으로 금층을 미리 1 내지 5 ㎛ 의 두께로 형성한다. 플립칩 접속을 행하는 경우에는, 가열과 가압 또는진동 등을 병합하여 열압착 본딩을 행한다.2 is a cross-sectional view illustrating a mounting structure of a semiconductor device in accordance with another embodiment of the present invention. The chip | tip 2 and the board | substrate 1 in which the internal pad 4 and the wiring pattern are formed are flip-chip connected. In order to ensure the connection by the gold bumps 3, the gold layer is formed to a thickness of 1 to 5 탆 in advance by either plating or sputtering on the inner pad of the substrate 1. In the case of flip chip connection, thermocompression bonding is performed by combining heating, pressurization or vibration.

그 다음에, 밀봉용 수지 (6) 를 칩 (2) 과 기판 (1) 사이에 주입하고, 경화시킨다. 그 다음에, 칩 (2) 이 탑재되어 있는 기판의 외부 패드 (5) 상에, 적층범프 (7) 를 형성한다. 적층범프 (7) 는 예를 들어, 납주석 솔더로 이루어진다. 다음으로, 칩 (2) 이 탑재되어 있는 기판 (1) 을 복수개 적층시키고, 리플로우에 의해 솔더를 융해시켜 일괄적으로 접속시킨다. 다음으로, 유연성 수지를 주입하여 각 기판 (1) 사이의 공간을 충전하고, 이것을 경화시켜, 완충재층 (8) 을 형성하여, 도 2 에 도시된 반도체 실장구조를 얻는다.Next, the sealing resin 6 is injected between the chip 2 and the substrate 1 and cured. Next, the laminated bumps 7 are formed on the outer pads 5 of the substrate on which the chips 2 are mounted. The laminated bumps 7 are made of, for example, lead tin solder. Next, the board | substrate 1 with which the chip | tip 2 is mounted is laminated | stacked, and solder is fuse | melted by reflow, and it connects collectively. Next, the flexible resin is injected to fill the space between the respective substrates 1, and this is cured to form the buffer layer 8, thereby obtaining the semiconductor mounting structure shown in FIG.

기판 (1) 의 저면과 칩의 상면 (9) 사이의 공간이 너무 협소하여 수지를 충분히 주입할 수 없는 경우에는, 제 1 실시예에서와 동일한 방식으로 칩 (2) 을 구비하는 기판 (1) 을 형성한 후에, 유연성 수지를 기판 (1) 들 사이의 공간내에 주입하여, 이것을 완충재층 (8) 으로서 사용하여, 도 2 에 도시된 반도체 실장구조를 얻는다.When the space between the bottom face of the substrate 1 and the top surface 9 of the chip is too narrow to sufficiently inject the resin, the substrate 1 having the chip 2 in the same manner as in the first embodiment After the formation, the flexible resin is injected into the space between the substrates 1 and used as the buffer material layer 8 to obtain the semiconductor mounting structure shown in FIG.

상술된 반도체 실장구조를 채택함으로서, 적층된 각 기판 사이에 유연성 완충재층 (8) 이 존재하기 때문에, 외부에서 인가된 충격과 진동을 흡수하여, 내충격성과 내진동성을 향상시킨다. 또한, 기판 (1) 들을 금속 (솔더) 으로 접속시키기 때문에, 전기저항도 낮다. 또한, 기판 (1) 의 내부 패드 (4) 하부에 유연성층이 없기 때문에, 금 등으로 이루어진 범프들에 의해 칩 (2) 과 기판 (1) 간에 양호한 접속을 형성할 수 있다.By adopting the semiconductor mounting structure described above, since the flexible buffer layer 8 exists between each stacked substrate, the shock and vibration applied from the outside are absorbed to improve impact resistance and vibration resistance. Moreover, since the board | substrate 1 is connected with a metal (solder), electrical resistance is also low. In addition, since there is no flexible layer under the inner pad 4 of the substrate 1, it is possible to form a good connection between the chip 2 and the substrate 1 by bumps made of gold or the like.

이 실시예에서는 기판 (1) 에 칩 (2) 을 접속하는데 금범프를 사용하였지만,솔더 범프 등도 사용할 수 있다.Although gold bumps were used to connect the chip 2 to the substrate 1 in this embodiment, solder bumps and the like can also be used.

상술된 본 발명에 따르면, 솔더 범프에 의해 적층, 접속된 칩탑재가 완료된 기판들 사이에, 유연성 완충재를 제공함으로써, 외부에서 가해지는 충격과 진동을 흡수하여, 내충격성과 내진동성을 향상시킨다. 이에 따라, 우주선과 차량 등의 충격과 진동을 받는 것에 3 차원 적층 모듈을 적용할 수 있다.According to the present invention described above, by providing a flexible cushioning material between the chip-mounted substrates stacked and connected by solder bumps, shocks and vibrations applied from the outside are absorbed, thereby improving impact resistance and vibration resistance. Accordingly, the three-dimensional stacked module can be applied to the shock and vibration of the spacecraft and the vehicle.

Claims (5)

기판의 표면 중 일 표면 상에 반도체 칩이 탑재되어 있는 복수개의 상기 기판이 적층되고 서로 전기적으로 상호 접속되어 있는 적층구조를 포함하며,A laminated structure in which a plurality of the substrates on which a semiconductor chip is mounted on one of the surfaces of the substrates are stacked and electrically connected to each other; 상기 적층구조는The laminated structure 상기 반도체칩의 하부면 상에 배치되어 상기 반도체칩과 상기 기판을 서로 접속시키는 금속범프;A metal bump disposed on a lower surface of the semiconductor chip to connect the semiconductor chip and the substrate to each other; 상기 기판과 상기 반도체칩의 접속부를 봉지하는 밀봉수지; 및A sealing resin encapsulating a connection portion between the substrate and the semiconductor chip; And 상기 반도체 칩의 상부면과 상기 상부면에 대향하는 상기 기판의 다른 표면 사이에 배치되어, 충격과 진동을 흡수할 수 있는 완충재층을 포함하는 것을 특징으로 하는 반도체 장치.And a buffer layer disposed between an upper surface of the semiconductor chip and another surface of the substrate opposite the upper surface, the buffer layer capable of absorbing shock and vibration. 제 1 항에 있어서, 상기 금속범프는 금으로 이루어진 것을 특징으로 하는 반도체 장치.The semiconductor device of claim 1, wherein the metal bumps are made of gold. 기판의 표면 중 일 표면상에 반도체 칩이 탑재되어 있는 복수개의 기판이 적층되고 서로 전기적으로 상호 접속되어 있는 적층 구조를 구비하는 반도체 장치의 제조방법으로서,A method of manufacturing a semiconductor device having a laminated structure in which a plurality of substrates on which a semiconductor chip is mounted is stacked on one surface of the substrate and electrically connected to each other. 상기 반도체 칩의 하부면 상에 금속 범프를 형성하는 제 1 단계;Forming a metal bump on a lower surface of the semiconductor chip; 상기 반도체 칩과 상기 기판을 조립하도록 상기 기판의 패드부를 금속으로도포하는 제 2 단계;A second step of coating the pad portion of the substrate with a metal to assemble the semiconductor chip and the substrate; 상기 반도체칩을 플립칩 방법을 사용하여 상기 기판에 접속시키는 제 3 단계;Connecting the semiconductor chip to the substrate using a flip chip method; 상기 반도체칩과 상기 기판의 접속부를 밀봉수지로 밀봉하는 제 4 단계;A fourth step of sealing a connection portion between the semiconductor chip and the substrate with a sealing resin; 상기 제 3 단계에서 각각 만들어진 상기 기판 사이에 솔더 범프를 배치하고 복수개의 상기 기판을 서로 적층하는 제 5 단계;A fifth step of arranging solder bumps between the substrates formed in the third step and stacking a plurality of the substrates together; 상기 적층된 기판들을 서로 전기적으로 접속시키는 제 6 단계; 및A sixth step of electrically connecting the stacked substrates to each other; And 상기 반도체 칩의 상부면과 상기 기판의 다른 표면 사이에 충격과 진동을 흡수할 수 있는 완충재를 충전하는 제 7 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.And a seventh step of filling a shock absorbing material capable of absorbing shock and vibration between an upper surface of the semiconductor chip and another surface of the substrate. 제 3 항에 있어서, 상기 금속 범프 및 상기 금속 패드는 금으로 형성하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 3, wherein the metal bump and the metal pad are formed of gold. 기판의 표면 중 일 표면 상에 반도체 칩이 탑재되어 있는 복수개의 상기 기판이 적층되고 서로 전기적으로 상호 접속되어 있는 적층구조를 구비하는 반도체 장치의 제조방법으로서,A manufacturing method of a semiconductor device having a laminated structure in which a plurality of the substrates on which a semiconductor chip is mounted on one of the surfaces of the substrate is laminated and electrically connected to each other. 상기 반도체 칩의 하부면 상에 금속 범프를 형성하는 제 1 단계;Forming a metal bump on a lower surface of the semiconductor chip; 상기 반도체 칩과 상기 기판을 조립하도록 상기 기판의 패드부를 금속으로 도포하는 제 2 단계;Applying a pad portion of the substrate with a metal to assemble the semiconductor chip and the substrate; 상기 반도체 칩을 플립칩 방법을 사용하여 상기 기판에 접속시키는 제 3 단계;Connecting the semiconductor chip to the substrate using a flip chip method; 상기 반도체 칩과 상기 기판의 접속부를 밀봉수지로 밀봉하는 제 4 단계;A fourth step of sealing a connection portion between the semiconductor chip and the substrate with a sealing resin; 상기 제 3 단계에서 각각 만들어진 상기 기판 사이에 솔더 범프를 배치하고 복수개의 상기 기판을 서로 적층하고, 상기 반도체 칩의 상부면과 상기 기판 사이에 충격과 진동을 흡수할 수 있는 완충재를 추가로 충전하는 제 5 단계; 및Arranging solder bumps between the substrates formed in the third step, stacking the plurality of substrates with each other, and further filling a buffer material capable of absorbing shock and vibration between the upper surface of the semiconductor chip and the substrate; A fifth step; And 상기 적층된 기판들을 서로 전기적으로 접속시키고 상기 완충재를 경화시키는 제 6 단계를 구비하는 것을 특징으로 하는 반도체 장치의 제조방법.And a sixth step of electrically connecting the stacked substrates to each other and curing the buffer material.
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