JP4935163B2 - Semiconductor chip mounting substrate - Google Patents

Description

  The present invention relates to a substrate on which a semiconductor chip is mounted, a semiconductor package in which the semiconductor chip is mounted on the substrate, and more particularly to a substrate and a semiconductor package in which the semiconductor chip is mounted by a flip chip method. The present invention also relates to a method for manufacturing a semiconductor package.

  With the downsizing and thinning of portable electronic devices, there is a demand for downsizing and thinning of components built into portable electronic devices, particularly semiconductor packages. As a semiconductor package that can be reduced in size and thickness, there is an increasing need for a semiconductor package that uses a flip chip connection in which terminals provided on a circuit surface of a semiconductor chip are directly connected to a pad of a substrate using a solder ball. Yes. In addition, in order to reduce the thickness of a semiconductor package, it is desired to reduce the thickness of a substrate on which a semiconductor chip is mounted.

With such thinning of the semiconductor package, in particular, the thinning of the substrate, the warpage of the semiconductor package has become a problem. The cause of the warp is that various thermal loads are applied in the manufacturing process of the semiconductor package, but the thermal expansion coefficients of the components constituting the semiconductor package are different from each other. The thermal load is generated, for example, during solder reflow when the semiconductor chip is flip-chip connected to the substrate or when the semiconductor package is mounted on another substrate. Thermal expansion coefficient of each component constituting the semiconductor package, for example, 3 × 10 ^-6 / K about the semiconductor chip, for substrate, a large glass cloth most influential in the substrate of the component 15 × 10 ^- It is about ⁶ / K.

  The warp occurring in the conventional semiconductor package will be described below.

  FIG. 17A is a plan view of a conventional semiconductor package, and FIG. 17B is a cross-sectional view taken along line AA in the semiconductor package shown in FIG. 17A after the semiconductor chip and the substrate are flip-chip connected and returned to room temperature. FIG.

  The substrate 102 has a chip mounting area in the center, and in the chip mounting area, the semiconductor chip 101 and the substrate 102 are flip-chip connected by a bump (not shown) of the semiconductor chip 101 and a pad (not shown) of the substrate. Has been. An underfill resin 104 is filled in a gap between the base semiconductor chip 101 and the substrate 102. A thermosetting resin is used for the underfill resin 104, and its curing temperature is about 180 ° C to 250 ° C. On the surface of the substrate 102 on which the semiconductor chip 101 is mounted, a plurality of external terminals 103 are arranged surrounding the semiconductor chip 101. External terminal 103 is formed of a solder ball.

  When manufacturing a semiconductor package, after filling the chip mounting area of the substrate 101 with the underfill resin 104, the semiconductor chip 101 is held by a chip mounting tool, and the semiconductor chip 101 is pressed against the substrate 102. As a result, the bumps of the semiconductor chip 101 and the pads of the substrate 102 are in close contact, and the semiconductor chip 101 and the substrate 102 are electrically connected.

  The chip mounting tool is heated. By pressing the semiconductor chip 101 against the substrate 102 with this tool, the heat of the tool is transmitted to the underfill resin 104 via the semiconductor chip 101, and the underfill resin 104 is cured. At this time, the substrate 102 is also heated to about 150 ° C. to 220 ° C. Thus, the mounting of the semiconductor chip 101 on the substrate 102 is performed in a state where both are heated. As described above, the thermal expansion coefficients of the semiconductor chip 101 and the substrate 102 are greatly different. Therefore, when the semiconductor chip 101 is mounted, the substrate 102 is greatly expanded as compared with the semiconductor chip 101.

  When the substrate 102 on which the semiconductor chip 101 is mounted is returned to room temperature after the underfill resin 104 is cured, the semiconductor chip 101 and the substrate 102 contract, but the substrate 102 contracts more than the semiconductor chip 101. In the chip mounting area, since the semiconductor chip 101 and the substrate 102 are integrated via the underfill resin 104, the semiconductor chip 101 is formed on the substrate 102 as shown in FIG. 17B due to the shrinkage of the semiconductor chip 101 and the substrate 102. Warpage occurs such that the mounted surface becomes convex.

  Thereafter, external terminals 103 are formed on the surface of the substrate 102 on which the semiconductor chip 101 is mounted, and the substrate 102 is connected to another substrate through a solder reflow process. The solder reflow is performed at a temperature higher than the melting point of the solder, for example, 240 ° C to 260 ° C. Therefore, during solder reflow, the semiconductor chip 101 and the substrate 102 expand, but due to the difference in thermal expansion coefficient between them, the surface on which the semiconductor chip 101 is mounted is concave in the semiconductor package as shown in FIGS. 17C and 17D. Warping occurs. Due to the occurrence of the warp, the external terminal 103 is lifted from the other substrate 105 at the center in the side of the semiconductor package. The floating amount of the external terminal 103 is larger as it is closer to the center of the semiconductor package.

  When the distance between the other substrate 105 and the external terminal 103 exceeds the range that can be absorbed by melting the cream solder supplied in the solder reflow process, the connection between the semiconductor package and the other substrate 105 becomes poor.

  Such a connection failure due to the warpage of the semiconductor package similarly occurs when the external terminal 103 is provided on the surface of the substrate 102 opposite to the surface on which the semiconductor chip 101 is mounted. In this case, the floating of the external terminal 103 occurs at the end of the semiconductor package.

  As the semiconductor package becomes thinner, the rigidity becomes lower. As described above, in a situation where the semiconductor package is required to be thin, the semiconductor chip 101 having a thickness of 0.3 mm or less and the substrate 102 having a thickness of 0.8 mm or less may be used. In such a case, the warpage of the semiconductor package becomes significant. Furthermore, the external terminals tend to be arranged at a high density in order to cope with the increase in the number of external terminals accompanying the higher functionality of the semiconductor package. Therefore, the diameter of the solder ball as the external terminal is also smaller. When the diameter of the solder ball is small, the tolerance for warping of the semiconductor package is small. In addition, due to the RoHS Directive (Restriction on the use of certain Hazardous Substances) aimed at reducing environmental impact, lead-free solder that has a high melting point and therefore requires a high temperature during reflow must be applied. This also contributes to the warpage of the semiconductor package. For this reason, the connection failure due to the warpage of the semiconductor package becomes more and more remarkable.

  In order to suppress the warpage of the semiconductor package, conventionally, means for securing rigidity by providing a reinforcing member in the semiconductor package has been taken.

  For example, Patent Document 1 discloses a semiconductor package in which an entire semiconductor chip mounting surface of a substrate on which a semiconductor chip is mounted is covered with a resin so as to seal the semiconductor chip. By covering the entire semiconductor chip mounting surface of the substrate with the resin in this way, the resin acts as a reinforcing member, and the rigidity of the semiconductor package is increased. As a result, warpage of the semiconductor package is suppressed.

  Patent Document 2 discloses a semiconductor package using a metal reinforcing member instead of a resin. Similarly to the reinforcing member disclosed in Patent Document 1, this reinforcing member is also attached to the substrate so as to cover the entire semiconductor chip mounting surface of the substrate, thereby sealing the semiconductor chip. The reinforcing member has a recess for accommodating the semiconductor chip on the surface to be attached to the substrate. Since the metal reinforcing member has higher rigidity than the resin, it is more effective for suppressing warpage.

  Patent Document 3 discloses that a reinforcing layer is provided in the periphery of a region of a substrate where a semiconductor chip is mounted, thereby increasing the rigidity of the substrate itself and suppressing the warpage of the substrate. A metal material or the like can be used for the reinforcing layer.

As described above, in the conventional semiconductor package, the warpage is suppressed by increasing the rigidity of the whole package or the substrate.
JP 2002-170901 A Japanese Patent No. 3395164 JP 2004-319779 A

  However, the semiconductor package provided with the above-described reinforcing member has a substantially same planar size as the substrate and is provided so as to cover the semiconductor chip, so that it is difficult to reduce the thickness of the semiconductor package. It was.

  Further, in recent years, a system-in-package (SiP) in which a plurality of semiconductor packages are accommodated in one larger semiconductor package has been actively developed as a high-performance semiconductor package suitable for portable electronic devices. In the semiconductor package provided with the reinforcing member or the semiconductor package provided with the reinforcing layer on the substrate as described above, the region where the reinforcing member and the reinforcing layer are disposed is a dead area (an area where other electronic components cannot be mounted). It becomes.

  Therefore, the conventional semiconductor package having a reinforcing member or a reinforcing layer has a limited number of electronic components that can be mounted when another electronic component or another semiconductor package is further mounted, or the size of the semiconductor package is limited. There was a problem of increasing the size. Therefore, it has been difficult to realize a small, thin and highly functional semiconductor package applicable to portable electronic devices.

  An object of the present invention is to suppress a warp that may be caused by heating while minimizing a dead area, and a semiconductor package suitable for downsizing, thinning, and high functionality, a substrate used in the semiconductor package, and a semiconductor package It is to provide a manufacturing method and the like.

In order to achieve the above object, a substrate of the present invention is located on a chip mounting area on which a semiconductor chip is mounted, and an external connection provided on a portion outside the chip mounting area and provided with a terminal for electrical connection with the outside. And a local deformation member provided integrally with the substrate in a portion outside the chip mounting region. The local deformation essential member has a coefficient of thermal expansion so as to locally deform the substrate in the direction opposite to the direction of warpage occurring in the chip mounting area when the substrate is heated with the semiconductor chip mounted in the chip mounting area. Is different from the thermal expansion coefficient of the substrate. Further, the local deformation member is provided in a portion between the chip mounting region and the external connection region so as to surround the outer peripheral portion of the chip mounting region over the entire periphery.

  More specifically, the thermal expansion coefficient of the local deformation member is larger than the thermal expansion coefficient of the substrate when the local deformation member is located on the chip mounting surface side of the substrate. When located on the chip non-mounting surface side which is the opposite surface, it is smaller than the thermal expansion coefficient of the substrate.

  By providing the member for local deformation on the substrate as described above, when the semiconductor package using this substrate is mounted on another substrate, the warp generated in the substrate by applying heat to the semiconductor package is corrected.

  More specifically, when heat is applied to the substrate on which the semiconductor chip is mounted, the surface on which the semiconductor chip is mounted becomes concave in the chip mounting area of the substrate due to the difference in thermal expansion coefficient between the semiconductor chip and the substrate. Warp occurs. Since the local deformation member as described above is provided on the substrate on the outer side of the chip mounting area, the warp generated in the chip mounting area is corrected by the local deformation member. As a result, the external connection region located outside the chip mounting region approaches a plane, so that the terminals provided in the external connection region are well connected to other substrates and the like.

  Moreover, in the present invention, the flatness of the external connection region is ensured by intentionally deforming the substrate by utilizing the thermal expansion of the local deformation member, instead of suppressing the deformation of the substrate as in the prior art. . The member for local deformation exhibits a sufficient effect with a small volume by appropriately selecting the material and the installation location. Therefore, according to the present invention, the increase in the thickness and volume of the substrate and the semiconductor package due to the provision of the member for local deformation is suppressed, and the dead area is minimized.

  As described above, according to the present invention, the warpage caused by heating the substrate can be corrected and the flatness of the external connection region can be ensured. Therefore, when the semiconductor package is mounted on another substrate, Connection failure can be suppressed. In addition, since the warpage of the substrate can be corrected with the minimum occupied volume of the member for local deformation, the substrate and the semiconductor package can be reduced in size and thickness, the dead space is small, and other components are dense. Can be installed.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
Referring to FIG. 1A, a plan view of a semiconductor package according to the first embodiment of the present invention, which has a substrate 2 and a semiconductor chip 1 mounted on the substrate 2, as viewed from the surface side where the external terminals 3 are provided. The figure is shown. 1B shows a cross-sectional view of the semiconductor package shown in FIG. 1A in a heated state, taken along the line 1B-1B, and FIG. 1C also shows a cross-sectional view taken along the line 1C-1C.

  The semiconductor chip 1 is obtained by forming elements such as a logic circuit and a memory on a silicon wafer by using a semiconductor manufacturing process, and a plurality of bumps (not formed) are formed on the surface on which the element is formed (element formation surface). (Shown) is provided.

  The substrate 2 mounts the semiconductor chip 1 on one side, and the chip mounting surface, which is the surface on which the semiconductor chip 1 is mounted, includes a chip mounting area on which the semiconductor chip 1 is mounted, and this semiconductor package. And an external connection region for connecting to the substrate.

  The chip mounting area is located at the center of the substrate 2, and a plurality of pads (not shown) corresponding to the bumps of the semiconductor chip 1 are provided in the chip mounting area. The semiconductor chip 1 is mounted on the chip mounting area of the substrate 2 with its bumps in contact with the pads of the substrate 2. The external connection area is located so as to surround the chip mounting area. A plurality of external connection terminals 3 are provided in the external connection region. The external connection terminal 3 is formed of a solder ball and is connected to a plurality of pads (not shown) formed in the external connection region of the substrate 2. As described above, a plurality of pads connected to the semiconductor chip 1 and a plurality of pads connected to the external connection terminals 3 are formed on the substrate 2. Due to the presence of these pads, even the substrate 2 alone is mounted on the chip. The area can be distinguished from the external connection area.

  The gap between the semiconductor chip 1 and the substrate 2 is filled with an underfill resin 4. The underfill resin 4 serves to reinforce the electrical connection state between the semiconductor chip 1 and the substrate 2. As the underfill resin 4, for example, a thermosetting epoxy resin can be used. When a thermosetting epoxy resin is used as the underfill resin 4, after filling the gap between the semiconductor chip 1 and the substrate 2 with the epoxy resin, the epoxy resin is heated to 180 to 250 ° C., for example. Harden.

  Each pad and each external connection terminal 3 are electrically connected through a wiring layer (not shown) and a via hole (not shown) provided in the inner layer of the substrate 2. As the substrate 2, for example, a very high rigidity FR-4 substrate using a glass cloth material as a base material can be used. The semiconductor package is connected to another substrate (not shown) via the external connection terminal 3. Thereby, a new semiconductor package including this semiconductor package is formed.

  Between the chip mounting region and the external connection region of the substrate 2, a local deformation member 7 is provided in close contact with the substrate 2 over the entire outer periphery of the semiconductor chip 1. The local deformation member 7 is embedded on the chip mounting surface side of the substrate 2 with one end surface exposed to the chip mounting surface. The position of one end surface of the local deformation member 7 may be the same as the chip mounting surface, may be a position deeper in the substrate 2 than the chip mounting surface, or a position protruding from the chip mounting surface. It may be.

  In the present invention, “the chip mounting surface side of the substrate 2” when referring to the position of the member 7 for local deformation means that when the substrate is divided into two equal parts in the thickness direction, the chip is based on the bisector. When the volume of the local deformation member 7 is compared between the mounting surface side and the opposite surface side (chip non-mounting surface side), the chip mounting surface side is larger than the chip non-mounting surface side. It means that the member 7 exists.

The local deformation member 7 is for correcting the warp generated in the substrate 2 by locally deforming the substrate 2 when heat is applied to the substrate 2, and is larger than the thermal expansion coefficient of the substrate 2. It is made of a material having a thermal expansion coefficient. When the FR-4 substrate is used as the substrate, the thermal expansion coefficient of the substrate 2 is about 15 × 10 ⁻⁶ / K, which is close to the glass cloth material that is the base material of the substrate 2. Therefore, as the local deformation member 7 having a thermal expansion coefficient larger than this value, for example, an epoxy resin can be used as the resin material.

  Next, an example of a method for manufacturing the semiconductor package described above will be described.

  First, the substrate 2 on which the local deformation member 7 is formed and the semiconductor chip 1 are prepared. The method for forming the local deformation member 7 on the substrate 2 is not particularly limited. As a method for forming the local deformation member 7, for example, a groove for the local deformation member 7 is formed in the substrate 2, a liquid resin is filled in the groove, and the groove is cured. For example, the local deformation member 7 may be fitted into the groove of the substrate 2 and bonded. In the case of using a liquid resin, the liquid resin can be supplied to the groove formed in the substrate 2 by using a dispenser (not shown) or by using a printing method using a mask such as a metal mask or a screen mask. Can also be done.

  Next, the semiconductor chip 1 is connected to the substrate 2 by flip chip connection. Examples of the flip chip connection method include a pressure welding method, a thermocompression bonding method, a solder fusion bonding method, and an ultrasonic pressure bonding method. In any method, when the semiconductor chip 1 and the substrate 2 are connected, the connecting portions of both are heated. This heating is performed by heating a chip mounting tool for handling the semiconductor chip 1 on the substrate 2 when the semiconductor chip 1 is mounted on the substrate 2 and heating the semiconductor chip 1 via the chip mounting tool.

For example, when connecting by the pressure welding method, since the curing temperature of the underfill resin 4 is generally 180 to 250 ° C., the temperature of the substrate 2 at this time is 150 to 220 ° C. The thermal expansion coefficient of the semiconductor chip 1 is about 3 × 10 ⁻⁶ / K, whereas the thermal expansion coefficient of the substrate 2 is about 15 × 10 ⁻⁶ / K, which is compared with the thermal expansion coefficient of the semiconductor chip 1. Very large. Therefore, the semiconductor chip 1 and the substrate 2 are connected in a state where the substrate 2 is expanded more than the semiconductor chip 1. Therefore, after the connection between the semiconductor chip 1 and the substrate 2, the substrate 2 contracts more than the semiconductor chip 1 as shown in FIG. As a result, the substrate 2 is warped in a direction in which the surface on which the semiconductor chip 1 is mounted is convex.

  The amount of warpage becomes more conspicuous as the thickness of the semiconductor chip 1 and the substrate 2 is thinner and as the area of the semiconductor chip 1 is larger. On the other hand, the degree of warpage of the substrate 2 in the vicinity of the local deformation member 7 varies depending on the method of forming the local deformation member 7. For example, when the material constituting the inflection point forming member 7 is bonded or formed on the substrate 2 at a temperature close to normal temperature, the substrate 2 is formed with the chip mounting region and the local deformation member 7 at normal temperature. A region (external connection region in the present embodiment) excluding the formed region is substantially flat.

  Here, the case where the semiconductor chip 1 is mounted on the substrate 2 on which the local deformation member 7 is formed in advance is taken as an example. However, before the local deformation member 7 is formed on the substrate 2, the semiconductor is formed on the substrate 2. The chip 1 may be mounted, and then the local deformation member 7 may be formed on the substrate 2.

  Next, a semiconductor package having the semiconductor chip 1 mounted on the substrate 2 is mounted on another substrate (not shown). The semiconductor package is mounted on another substrate by electrically connecting the external connection terminals 3 provided on the semiconductor package to pads (not shown) provided on the other substrate. The electrical connection between the external connection terminal 3 and another substrate can be performed by solder reflow. When Sn-3.5Ag-0.5Cu alloy, which is a lead-free solder, is used as the solder used during solder reflow, the melting point is about 225 ° C., so the temperature during reflow soldering (reflow temperature) is 240-260 ° C. It is said to be about.

  Therefore, the semiconductor package expands again by solder reflow. At this time, as shown in FIG. 1B, during the solder reflow, the semiconductor package is heated, so that the substrate 2 has a thermal expansion amount difference between the semiconductor chip 1 and the substrate 2 in the chip mounting region. Further, warpage occurs such that the chip mounting surface side becomes concave. On the other hand, on the outside of the chip mounting area, a local deformation member 7 having a thermal expansion coefficient larger than that of the substrate 2 is provided in close contact with the substrate 2. Therefore, in the region where the local deformation member 7 is provided, the local deformation member 7 expands more greatly in the thickness direction of the substrate 2 than the portion of the substrate 2 at the same position as the local deformation member 7. Therefore, it is locally deformed so that the chip mounting surface side is convex.

  As a result, as shown in FIGS. 1B and 1C, in the external connection region, which is a region further outside the region where the local deformation member 7 is provided, the warpage generated in the chip mounting region is corrected. The plane P is almost parallel. As a result, the external connection terminals 3 are hardly lifted from other substrates. Even if the external connection terminal 3 is lifted, the cream solder supplied in the solder reflow process can be suppressed to the extent that it can be absorbed by melting. Therefore, connection failure between the semiconductor package and another substrate can be greatly reduced.

  On the other hand, in the structure in which the rigidity of the substrate is increased with a reinforcing material or a reinforcing layer as in the past, the occupied area or occupied volume of the reinforcing material or the reinforcing layer in the semiconductor package is increased, and the area on which the components of the board can be mounted Limited. In the present embodiment, a new method of correcting the warp of the substrate 2 instead of increasing the rigidity of the substrate 2 is adopted, and therefore the size of the local deformation member 7 which is a structure for correcting the warp of the substrate. Does not need to be large. Therefore, the area occupied by the local deformation member 7 can be reduced, and a region where other parts can be mounted can be ensured to the maximum.

  In particular, in the present embodiment, since the local deformation member 7 is formed by being embedded in the substrate 2, the action of the local deformation member 7 can be effectively exhibited. That is, in this embodiment, since the side surface of the local deformation member 7 is provided in close contact with the substrate 2, the local deformation member 7 expands so that the substrate 2 becomes the side surface of the local deformation member 7. Is pushed in the in-plane direction of the substrate 2. Therefore, the expansion of the local deformation member 7 can be effectively used for local deformation of the substrate 2. In order to more effectively exert the action of pressing the substrate 2 in the in-plane direction by the local deformation member 7, a groove formed in the substrate 2 for embedding the local deformation member 7 is formed on the side wall. It is preferably formed so as to be perpendicular to the in-plane direction of the substrate 2.

  The amount of warpage generated in the substrate 2 by the expansion of the local deformation member 7 can be adjusted by the physical properties, thickness, width, and the like of the local deformation member 7.

  Further, in order to effectively warp the substrate 2 in the direction opposite to the chip mounting area, the local deformation member 7 has high rigidity enough to warp the substrate 2 when the semiconductor package is connected to another substrate. It is also important. The connection between the semiconductor package and another substrate is performed in a state where the solder balls as the external connection terminals 3 are melted. Therefore, in order for the local deformation member 7 to have high rigidity when the semiconductor package is connected to another substrate, the local deformation member 7 has an elastic modulus at the melting point of the solder used for the external connection terminal 3. It is preferable that the elastic modulus of the substrate 2 is higher. Alternatively, when the connection between the semiconductor package and another substrate is performed by solder reflow, since the solder reflow is performed at a temperature higher than the melting point of the solder, the local deformation member 7 is actually in the solder reflow temperature range. It is preferable that the elastic modulus is higher than the elastic modulus of the substrate 2.

When the local deformation member 7 is made of a resin material, a filler can be added to the local deformation member 7. In this case, it is preferable that the filler added to the local deformation member 7 has a higher thermal expansion coefficient. For example, the thermal expansion coefficients of silica, alumina, and Cu (copper), which are commonly used as fillers, are 5 × 10 ⁻⁶ / K, 7 to 8 × 10 ⁻⁶ / K, and 17 × 10 ^{−, respectively. 6} / K. Therefore, from the viewpoint of the thermal expansion coefficient, the filler added to the local deformation member 7 is more preferably a metal filler such as Cu. Furthermore, a silicone filler having a low modulus of elasticity but a remarkably large thermal expansion coefficient is also used when a high glass transition point (Tg) and high rigidity resin such as silica hybrid is used as the local deformation member 7. By combining, the effect of increasing the thermal expansion coefficient of the local deformation member 7 can be obtained. On the other hand, from the viewpoint of improving the elastic modulus of the local deformation member 7, as a filler added to the local deformation member 7, any of metal fillers such as silica, alumina, and Cu can be preferably used.

  As described above, various members can be selected as the local deformation member 7. However, since the warpage of the substrate 2 is a problem in the solder reflow process, the value of the elastic modulus of the substrate 2 and the local deformation member 7 is particularly important in the solder reflow temperature range.

  FIG. 2 is a graph showing the temperature dependence of the elastic modulus of a substrate based on a glass cloth material called FR-4, which is a general material of the substrate 2. The substrate 2 exhibits a high elastic property of about 10 GPa at room temperature. However, for example, the elastic modulus between 220 ° C. and 230 ° C., which is the melting point of Sn-Ag—Cu ternary solder common as lead-free solder, decreases to about 2GPa, which is about 1/5 of the normal temperature. . Therefore, in this case, the elastic modulus of the local deformation member 7 only needs to have an elastic modulus exceeding 2 GPa in this temperature range. Therefore, as the local deformation member 7, for example, a material (thermosetting amine epoxy resin) having elastic modulus characteristics as shown in FIG. 3 is applicable. This material has an elastic modulus of 4 GPa exceeding the elastic modulus of 2 GPa of the substrate 2 at 225 ° C., and can be preferably used as the local deformation member 7. In addition, it is known that the elastic modulus of the resin material rapidly decreases at a glass transition temperature (Tg) or higher. For this reason, when using a resin material as the member 7 for local deformation, it is preferable that it is a material with high Tg. Furthermore, it is more preferable if the Tg of the local deformation member 7 exceeds the melting point of the solder.

  On the other hand, by optimizing the material of the substrate 2, the effect of the local deformation member 7 can be increased. If a material having a low modulus of elasticity in the solder reflow temperature region is used as the material of the substrate 2, a material having a low modulus of elasticity can be applied as the material of the local deformation member 7, and the selection range of the material of the local deformation member 7 can be expanded. Can do. Similarly, it is preferable that the thermal expansion coefficient of the substrate 2 is low, and it is preferable that the thermal expansion coefficient of the semiconductor chip 1 is closer.

  Most of the materials of the substrate 2, not limited to FR-4, show a sudden decrease in elastic modulus when exceeding Tg. The amount of decrease in the elastic modulus and the temperature at which the elastic modulus rapidly decreases vary depending on the material.

As the substrate 2, in addition to FR-4, for example, a material obtained by impregnating aramid nonwoven fabric with a resin may be selected. The thermal expansion coefficient of the substrate based on the aramid nonwoven fabric is lower than that of FR-4, about 10 × 10 ⁻⁶ / K, and the elastic modulus in the solder reflow temperature region is also lower than that of FR-4. For this reason, when a substrate made of an aramid nonwoven fabric is used as the substrate 2, the effect of the member 7 for local deformation is increased. Moreover, in the board | substrate which used this aramid nonwoven fabric as the base material, since the thermal expansion coefficient is low, the difference of a thermal expansion coefficient with metal materials, such as Cu, becomes large. Therefore, an inorganic material such as a metal plate can be applied as the local deformation member 7. At this time, it is important that the substrate 2 and the local deformation member 7 are in close contact with each other in the solder reflow temperature range.

(Second Embodiment)
A semiconductor package according to a second embodiment of the present invention will be described with reference to FIGS. 4A, 4B, and 4C. The semiconductor package according to the present embodiment is different from the first embodiment in that the external connection terminals 3 are provided on the surface of the substrate 2 opposite to the chip mounting surface. That is, in the substrate 2, the chip mounting area and the external connection area are located on opposite surfaces. Other configurations, for example, that the semiconductor chip 1 is mounted in the center of the substrate 2, the gap between the semiconductor chip 1 and the substrate 2 is filled with the underfill resin 4, and the chip mounting surface of the substrate 2 The local deformation member 7 is formed so as to surround the chip mounting region on the side, as in the first embodiment.

  In FIGS. 4A to 4C, the same reference numerals as those used in the description of the first embodiment are assigned to the same constituent members as those in the first embodiment. The same applies to the following embodiments.

  As described above, in the present embodiment, the external connection terminals 3 are provided on the surface of the substrate 2 opposite to the chip mounting surface, but the other configurations are the same as those in the first embodiment. Therefore, the behavior of the semiconductor package when heat is applied is the same as that of the first embodiment. That is, when the semiconductor package is heated when the semiconductor package is mounted on another substrate, as shown in FIG. 4B, the substrate 2 is warped such that the chip mounting surface side becomes concave in the chip mounting region. Will occur. On the other hand, outside the chip mounting area, the substrate 2 is locally deformed so that the portion on which the local deformation member 7 is provided is convex on the chip mounting surface side.

  As a result, as shown in FIGS. 4B and 4C, in the external connection region located outside the region where the local deformation member 7 is provided, the warpage generated in the chip mounting region is corrected. , Almost parallel to the plane P. Therefore, also in the present embodiment, the connection failure between the semiconductor package and another substrate can be greatly reduced as in the above-described embodiment.

(Third embodiment)
A semiconductor package according to a third embodiment of the present invention will be described with reference to FIGS. 5A, 5B, and 5C.

  In the first and second embodiments, the example in which the local deformation member 7 is provided on the chip mounting surface side of the substrate 2 has been described. However, in the present embodiment, the local formation member 7 is used as the semiconductor chip 1 of the substrate 2. Is provided on the side opposite to the surface on which the chip is mounted (chip non-mounting surface) side. In other words, in this embodiment, the semiconductor chip 1 is placed on the substrate 2 in a state where the substrate 2 on which the local deformation member 7 is formed is reversed from the first embodiment, as in the first embodiment. An external connection terminal 3 is provided.

  In the present invention, “the chip non-mounting surface side of the substrate 2” when referring to the position of the local deformation member 7 is based on the same concept as the “chip mounting surface side”. That is, “the chip non-mounting surface side of the substrate 2” means that when the substrate is bisected in the thickness direction, the chip mounting surface side and the chip non-mounting surface side are locally divided with reference to the bisector. When comparing the volume of the deformation member 7, it means that the local deformation member 7 exists so that the chip non-mounting surface side is larger than the chip mounting surface side.

  A material having a smaller thermal expansion coefficient than that of the substrate 2 is used for the local deformation member 7. Examples of the material having a smaller thermal expansion coefficient than the substrate 2 include a resin material to which an inorganic filler such as silica is added, a liquid crystal polymer whose thermal expansion coefficient can be adjusted by crystal orientation, and an inorganic material having a low expansion coefficient. More specifically, examples of the inorganic material that can be preferably used for the local deformation member 7 include ceramics typified by alumina and silicon nitride, and metals such as 42 alloy and Kovar.

  In the present embodiment, when the semiconductor package is heated in order to mount the semiconductor package on another substrate (not shown), as shown in FIG. The warp which becomes becomes occurs. On the other hand, in the part where the member 7 for local deformation outside the chip mounting area is provided, the substrate 2 is used for local deformation as compared with the portion of the substrate 2 at the same position as the member for local deformation 7 in the thickness direction of the substrate 2. The expansion amount of the member 7 is small. As a result, the substrate 2 is locally deformed so that the chip mounting surface side is convex in the portion where the local deformation member 7 is provided.

  As a result, in the external connection region located outside the region where the local deformation member 7 is provided, the substrate 2 is corrected in the chip mounting region, and becomes substantially parallel to the plane P. Therefore, also in this embodiment, as in the above-described embodiments, connection failures between the semiconductor package and other substrates can be greatly reduced.

  The effect according to the present embodiment is not limited to the case where the external connection terminal 3 is provided on the chip mounting surface of the substrate 2, but is the same even when it is provided on the chip non-mounting surface.

(Fourth embodiment)
A semiconductor package according to a fourth embodiment of the present invention will be described with reference to FIGS. 6A, 6B and 6C. The semiconductor package of this embodiment is different from the above-described embodiments in the shape of the substrate 2. That is, the substrate 2 has a recess formed on the chip mounting surface, and the semiconductor chip 1 is mounted on the substrate 2 while being positioned in the recess. An underfill resin 4 is filled in a gap between the substrate 2 and the semiconductor chip 1. The external connection terminal 3 is provided on the chip mounting surface of the substrate 2.

  The planar size of the recess formed in the substrate 2 is larger than the planar size of the semiconductor chip 1, and the outer periphery of the semiconductor chip 1 mounted on the substrate 2 in the recess has a space due to the recess over the entire periphery of the semiconductor chip 1. There is. The local deformation member 7 is provided on the substrate 2 so as to fill this space. Therefore, the local deformation member 7 is provided integrally with the substrate 2 so as to surround the outer periphery of the semiconductor chip 1 over the entire periphery. As the local deformation member 7, a material having a thermal expansion coefficient larger than that of the substrate 2 is used.

  Also in this embodiment, when the semiconductor package is heated to mount the semiconductor package on another substrate (not shown), the substrate 2 has a chip mounting surface side in the chip mounting area as shown in FIG. 6B. Warping that becomes concave occurs. On the other hand, at the site where the local deformation member 7 is provided, the substrate 2 is locally deformed so that the chip mounting surface side is convex. As a result, as shown in FIGS. 6B and 6C, in the external connection region located outside the region where the local deformation member 7 is provided, the warpage generated in the chip mounting region is corrected. , Almost parallel to the plane P. Therefore, this embodiment can also significantly reduce the connection failure between the semiconductor package and another substrate, as in the above-described embodiment.

  The configuration in which the semiconductor chip 1 and the local deformation member 7 are arranged in the recess formed in the substrate 2 as in the present embodiment is such that after mounting the semiconductor chip 1 on the substrate 2, for example, liquid resin is applied to the recess of the substrate 2. It can be formed by filling and curing. Of course, also in the present embodiment, the local deformation member 7 is prepared in advance, and after mounting the semiconductor chip 1 on the substrate 2, the local deformation member 7 can be fixed in the recess of the substrate 2 by bonding or the like. .

(Fifth embodiment)
A semiconductor package according to a fifth embodiment of the present invention will be described with reference to FIGS. 7A, 7B and 7C.

  The semiconductor package of this embodiment is different from the above-described fourth embodiment in that the external connection terminals 3 are provided on the chip non-mounting surface of the substrate 2. Other configurations are the same as those of the fourth embodiment. Even when the external connection terminals 3 are provided on the chip non-mounting surface of the substrate 2 as in the present embodiment, the semiconductor package is mounted on another substrate (not shown) as in the fourth embodiment. In addition, it is possible to correct the warp generated in the substrate 2 when the semiconductor package is heated. As a result, also in the present embodiment, the connection failure between the semiconductor package and another substrate can be greatly reduced.

  In the fourth embodiment and the fifth embodiment described above, the example in which the local deformation member 7 is provided on the chip mounting surface side of the substrate 2 has been described. However, as in the third embodiment, the chip of the substrate 2 is provided. The local deformation member 7 may be provided on the non-mounting surface side. In that case, the local deformation member 7 having a thermal expansion coefficient smaller than that of the substrate 2 is used.

(Sixth embodiment)
A semiconductor package according to a sixth embodiment of the present invention will be described with reference to FIGS. 8A, 8B and 8C. The basic structure of the semiconductor package of this embodiment is the same as that of the fourth embodiment, but differs from the fourth embodiment in that a local deformation member 7 is provided so as to cover the semiconductor chip 1. Yes. Such a member 7 for local deformation is mounted after the semiconductor chip 1 is mounted in the recess of the substrate 2, for example, by supplying a liquid resin onto the substrate 2 so as to fill the recess and cover the semiconductor chip 1. Can be formed.

  Even when the local deformation member 7 is formed so as to cover the semiconductor chip 1, the local deformation member 7 is locally deformed by the local deformation member 7 when the substrate 2 is heated. Occurs where it touches. Therefore, when the semiconductor package is heated to mount the semiconductor package on another substrate (not shown), the substrate 2 is externally connected as shown in FIGS. 8B and 8C, as in the fourth embodiment. In the external connection area where the terminals 3 are provided, the warp generated in the chip mounting area is corrected and becomes almost parallel to the plane P. As a result, this embodiment can also significantly reduce the connection failure between the semiconductor package and another substrate.

  In the present embodiment, since the local deformation member 7 is provided so as to cover the semiconductor chip 1, in addition to the above-described effects, the following effects can be obtained.

  The first effect is that the semiconductor chip 1 can be protected. Since the local deformation member 7 covers the semiconductor chip 1, the semiconductor chip 1 is sealed by the local deformation member 7. As a result, the semiconductor chip 1 is protected by the local deformation member 7.

  The second effect is that the warpage of the substrate 2 in the chip mounting area when the substrate 2 is heated can be alleviated. The thermal expansion coefficient of the local deformation member 7 is larger than the thermal expansion coefficient of the substrate 2. The thermal expansion coefficient of the substrate 2 is larger than the thermal expansion coefficient of the semiconductor chip 1. Therefore, the thermal expansion coefficient of the locally deformed waist member is larger than the thermal expansion coefficient of the semiconductor chip 1. Since the local deformation member 7 is integrally provided in close contact with the surface of the semiconductor chip 1 opposite to the connection surface with the substrate 2, when the semiconductor package is heated, the local deformation member 7 is In the portion covering the semiconductor chip 1, the locally deformed waist member 7 tends to expand more than the semiconductor chip 1. As a result, the warpage in which the chip mounting surface side becomes concave in the chip mounting area of the substrate 2 is alleviated.

(Seventh embodiment)
A semiconductor package according to a seventh embodiment of the present invention will be described with reference to FIGS. 9A, 9B and 9C.

  The semiconductor package of this embodiment is different from the above-described sixth embodiment in that the external connection terminal 3 is provided on the chip non-mounting surface of the substrate 2. Other configurations are the same as those of the sixth embodiment. Even when the external connection terminals 3 are provided on the chip non-mounting surface of the substrate 2 as in the present embodiment, the semiconductor package is mounted on another substrate (not shown) as in the sixth embodiment. In addition, it is possible to correct the warp generated in the substrate 2 when the semiconductor package is heated. As a result, also in the present embodiment, the connection failure between the semiconductor package and another substrate can be greatly reduced.

(Eighth embodiment)
In each of the above-described embodiments, the local deformation member is described as being embedded in the substrate. However, the local deformation member may be provided on the surface of the substrate.

  A semiconductor package according to the eighth embodiment of the present invention will be described below with reference to FIGS. 10A and 10B.

  The chip mounting surface of the substrate 2 has a chip mounting area at the center and an external connection area outside the chip mounting area. That is, on the chip mounting surface of the substrate 2, the semiconductor chip 1 is mounted at the center, and a plurality of external connection terminals 3 are provided so as to surround the semiconductor chip 1 outside the semiconductor chip 1.

  On the chip mounting surface of the substrate 2, a local deformation member 7 is provided between the chip mounting area and the external connection terminal. The local deformation member 7 is integrally provided in close contact with the substrate 2 on the chip mounting surface of the substrate 2 and surrounds the outer periphery of the semiconductor chip 1 over the entire periphery. As the local deformation member 7, a material whose thermal expansion coefficient is larger than the thermal expansion coefficient of the substrate 2 is used.

  Even when the local deformation member 7 is provided as it is on the chip mounting surface of the substrate 2 as in the present embodiment, when the semiconductor package is heated at the portion where the substrate 2 and the local deformation member 7 are in close contact with each other. Due to the difference in thermal expansion between the substrate 2 and the local deformation member 7, the substrate 2 can be locally deformed so that the chip mounting surface side is convex. Therefore, as in the first embodiment, the warp generated in the semiconductor package by heating the semiconductor package can be corrected in the external connection region.

  In some cases, the thickness of the substrate 2 is extremely thin, and it is difficult to form a groove on the surface of the substrate 2. In such a case, the configuration of the present embodiment is effective. Further, as shown in FIG. 10B, the thickness of the semiconductor package is increased by providing the local deformation member 7 by setting the height of the local deformation member 7 to be equal to or less than the height of the semiconductor chip 1. Absent.

  10A and 10B show an example in which the member 7 for local deformation is provided on the outer peripheral portion of the semiconductor chip 1, but the member for local deformation covering the semiconductor chip 1 as shown in FIGS. 11A and 11B. 7 may be provided. In this case, the same effects as those of the sixth and seventh embodiments are obtained. 10A and 10B show an example in which the external connection terminals 3 are provided on the chip mounting surface of the substrate 2, but the external connection terminals 3 may be provided on the chip non-mounting surface of the substrate 2. 10A and 10B, the local deformation member 7 is provided on the chip mounting surface of the substrate 2, but the same effect can be obtained even if the local deformation member 7 is provided on the chip non-mounting surface of the substrate 2. it can. However, in this case, as the local deformation member 7, a material having a thermal expansion coefficient smaller than that of the substrate 2 is used. The local deformation member 7 is provided outside the area corresponding to the chip mounting area on the chip non-mounting surface of the substrate 2.

  10A and 11B show an example in which the member for local deformation 7 is provided on the surface of the substrate 2, but the local deformation member 7 is not exposed from the substrate 2 as shown in FIGS. 12A and 12B. Alternatively, the local deformation member 7 can be completely embedded in the substrate 2. In this case, the thermal expansion coefficient of the local deformation member 7 is selected depending on whether the local deformation member 7 is located on the chip mounting surface side or the chip non-mounting surface side. That is, as the local deformation member 7, when the local deformation member 7 is located on the chip mounting surface side, a member having a thermal expansion coefficient larger than the thermal expansion coefficient of the substrate 2 is used. In the case of being positioned, the one having a thermal expansion coefficient smaller than that of the substrate 2 is used.

  For example, the substrate 2 in which the local deformation member 7 is completely embedded includes, for example, a film-like resin or a thin metal plate processed into the shape of the local deformation member 7 in the layering process of the substrate 2. 2 can be formed by being sandwiched between desired layers constituting 2.

  The present invention has been described with reference to some typical embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the technical idea of the present invention.

  For example, the size, shape, and arrangement of the local deformation member 7 can be changed as appropriate in accordance with the degree of warpage generated in the semiconductor package and the flatness required for the external connection region of the substrate 2.

  The local deformation member 7 is more likely to generate a stress that corrects the substrate 2 as its volume increases. Therefore, as the volume of the local deformation member 7 increases, the range of physical properties required for the material characteristics required for the local deformation member 7 such as a thermal expansion coefficient, a glass transition point, an elastic modulus at the time of heating, and the like increases. There is an advantage that the degree of freedom of selection is improved. However, if the area of the semiconductor package in the planar direction is increased, the area for mounting other components is reduced. Therefore, it is necessary to set the optimum shape of the local deformation member 7 based on these balances. In that case, it is preferable that the region in which the local deformation member 7 is disposed is as close as possible to the semiconductor chip 1. As a result, the region in which the warp is corrected by the local deformation member 7 can be made larger, so that the range in which the flatness of the external connection region can be ensured can be expanded.

  It is also possible to increase the stress for correcting the substrate 2 by increasing the thickness of the local deformation member 7 in the thickness direction of the semiconductor package. In this case, the height of the local deformation member 7 from the surface of the substrate 2 is mounted on the same surface as the surface on which the local deformation member 7 is provided so that the merit of thinning the semiconductor package is not reduced. It is desirable to be equal to or less than the parts to be manufactured.

  As for the planar shape and arrangement of the local deformation member 7, in each of the above-described embodiments, the example in which the semiconductor chip 1 is surrounded over the entire circumference is shown. Various other examples can be considered as long as the shape and the arrangement can ensure the flatness.

  For example, the semiconductor package shown in FIG. 13 has four local deformations located on the substrate 2 between the chip mounting area on which the semiconductor chip 1 is mounted and the external connection area on which the external connection terminals 3 are provided. A working member 7 is provided. The local deformation member 7 has an L shape and is arranged at the four corners of the semiconductor chip 1 mounted on the substrate 2.

  Similarly to FIG. 13, the semiconductor package shown in FIG. 14 also has four local deformations located on the substrate 2 between the chip mounting area where the semiconductor chip 1 is mounted and the external connection area where the external connection terminals 3 are provided. A working member 7 is provided. However, in the example shown in FIG. 14, the local deformation member 7 is linear and is disposed along the four side surfaces of the semiconductor chip 1.

  In other words, the example shown in FIGS. 13 and 14 includes a plurality of local deformation members 7 along the outer periphery of the semiconductor chip 1 in a portion between the chip mounting area and the external connection area of the substrate 2. It can be said that it is divided and provided. The division number and division position of the local deformation member 7 are arbitrary.

  In the semiconductor package shown in FIG. 15, the four local deformation members 7 are arranged radially on the diagonal line of the substrate 2 or in other words, in the external connection region located outside the chip mounting region.

  13 to 15, the semiconductor chip 1 and the external connection terminal 3 may be provided on the same surface of the substrate 2 or may be provided on surfaces opposite to each other. The local deformation member 7 may also be provided on the chip mounting surface side of the substrate 2 or may be provided on the chip non-mounting surface side. However, the local deformation member 7 is made of a material having a thermal expansion coefficient larger than that of the substrate 2 when provided on the chip mounting surface side, and has a thermal expansion coefficient when provided on the non-chip mounting surface side. A material smaller than the thermal expansion coefficient of the substrate 2 is used.

  Further, in each of the embodiments described above, solder balls are used as the external connection terminals 3 for connecting the semiconductor package and another substrate. However, even when other connection methods are used, the warpage of the substrate 2 is particularly problematic. In this case, the present invention is effective.

  Furthermore, in the semiconductor package of the present invention, the warpage caused when the substrate 2 on which the semiconductor chip 1 is mounted is corrected by the local deformation member 7 having a thermal expansion coefficient different from the thermal expansion coefficient of the substrate 2. ing. This method of correcting the warp using the local deformation member 7 is described above in order to correct the warp in the substrate where the warp occurs due to the difference in thermal expansion coefficient between the mounted member and the substrate. Obviously, the present invention can be widely applied to other embodiments.

  Thus, by applying the present invention, a small and thin semiconductor package can be realized. Electronic devices having a substrate on which the semiconductor package is mounted can be reduced in size and thickness, and the electrical connection between the semiconductor package and the substrate can be performed at a high yield, and an attractive product can be provided at a low price. It becomes possible.

  The semiconductor package to which the present invention is applied can be suitably used particularly for a system-in-package (SiP) in which a plurality of semiconductor chips are mixed and packaged into one package. A cross-sectional view of an example thereof is shown in FIG. The system-in-package shown in FIG. 16 is configured by mounting another semiconductor package 6 on the semiconductor package of the present invention having the semiconductor chip 1, the substrate 2, the external terminals 3, the underfill resin 4, and the local deformation member 7. Has been. Such a system-in-package is realized only by the feature that the warpage of the substrate 2 is corrected while the dead space is reduced by the semiconductor package of the present invention. As described above, the present invention can be applied to all semiconductor packages, for example, semiconductor packages on which a semiconductor chip such as a CPU, logic, or memory is mounted regardless of the type of device. By mounting individual semiconductor chips in a semiconductor package configured with the structure of the present invention, as described above, a smaller, thinner, higher density, higher reliability, and lower cost semiconductor package than conventional semiconductor packages can be realized. it can. By applying these semiconductor packages of the present invention to electronic devices, portable devices such as mobile phones, digital still cameras, PDAs (Personal Digital Assistants), notebook personal computers and the like that are particularly required to be small and thin are further reduced.・ Thinners can be made thin and the added value of products can be increased.

  Specific examples of the semiconductor package of the present invention are shown below.

  In this example, a semiconductor package having the structure shown in FIGS. 6A to 6C was manufactured. As the substrate 2, FR-4, which is a four-layer build-up substrate based on a glass cloth base, having a planar size of 14 mm × 14 mm and a thickness of 0.5 mm, was used. The semiconductor chip 1 mounted on the substrate 2 had a planar size of 7 mm × 7 mm and a thickness of 0.1 mm. As the local deformation member 7, a thermosetting amine epoxy resin having a temperature-elastic modulus characteristic (having an elastic modulus of 1.2 GPa at 230 ° C.) shown in FIG. It was formed by filling in a liquid state and curing it. Further, this resin has a thermal expansion coefficient of 150 ppm / ° C. above the glass transition point Tg. As the external connection terminal 7, a solder ball made of Sn-3.5Ag-0.5Cu alloy was used.

  The manufactured semiconductor package was solder reflowed at 250 ° C. and mounted on another substrate. As a result, the yield of the connection portion between the semiconductor package and another substrate was 100%.

  For comparison, a semiconductor package exactly the same as described above was prepared except that the member for local deformation was not provided, and was mounted on another substrate under the same conditions as described above. As a result, the yield of the connection portion was 23%. Thereby, the effectiveness of the present invention was confirmed.

It is the top view seen from the surface side in which the external terminal of the semiconductor package by the 1st Embodiment of this invention was provided. FIG. 1B is a cross-sectional view taken along line 1B-1B during heating of the semiconductor package shown in FIG. 1A. FIG. 1B is a cross-sectional view taken along line 1C-1C during heating of the semiconductor package shown in FIG. 1A. It is a graph which shows the relationship between the temperature of a FR-4 board | substrate, and an elasticity modulus. It is a graph which shows the relationship between temperature and an elasticity modulus of a thermosetting amine epoxy resin. It is the top view seen from the surface side in which the external terminal of the semiconductor package by the 2nd Embodiment of this invention was provided. FIG. 4B is a cross-sectional view taken along the line 4B-4B during heating of the semiconductor package shown in FIG. 4A. FIG. 4B is a sectional view taken along line 4C-4C during heating of the semiconductor package shown in FIG. 4A. It is the top view seen from the surface side in which the external terminal of the semiconductor package by the 3rd Embodiment of this invention was provided. FIG. 5B is a sectional view taken along line 5B-5B during heating of the semiconductor package shown in FIG. 5A. FIG. 5C is a sectional view taken along line 5C-5C during heating of the semiconductor package shown in FIG. 5A. It is the top view seen from the surface side in which the external terminal was provided of the semiconductor package by the 4th Embodiment of this invention. FIG. 6B is a cross-sectional view taken along line 6B-6B during heating of the semiconductor package shown in FIG. 6A. FIG. 6B is a sectional view taken along line 6C-6C during heating of the semiconductor package shown in FIG. 6A. It is the top view seen from the surface side in which the external terminal was provided of the semiconductor package by the 5th Embodiment of this invention. FIG. 7B is a cross-sectional view taken along line 7B-7B when the semiconductor package shown in FIG. 7A is heated. FIG. 7B is a cross-sectional view taken along line 7C-7C during heating of the semiconductor package shown in FIG. 7A. It is the top view seen from the surface side in which the external terminal was provided of the semiconductor package by the 6th Embodiment of this invention. FIG. 8B is a cross-sectional view taken along the line 8B-8B when the semiconductor package shown in FIG. 8A is heated. FIG. 8C is a cross-sectional view taken along line 8C-8C during heating of the semiconductor package shown in FIG. 8A. It is the top view seen from the surface side in which the external terminal was provided of the semiconductor package by the 7th Embodiment of this invention. FIG. 9B is a sectional view taken along line 9B-9B during heating of the semiconductor package shown in FIG. 9A. FIG. 9B is a sectional view taken along line 9C-9C during heating of the semiconductor package shown in FIG. 9A. It is the top view seen from the surface side in which the external terminal was provided of the semiconductor package by the 8th Embodiment of this invention. FIG. 10B is a cross-sectional view of the semiconductor package shown in FIG. 10A taken along line 10B-10B. It is the top view seen from the surface side in which the external terminal was provided of the modification of the semiconductor package shown to FIG. 10A. FIG. 11B is a cross-sectional view of the semiconductor package shown in FIG. 11A taken along the line 11B-11B. It is the top view seen from the surface side in which the external terminal of the semiconductor package which embedded the member for local deformation | transformation completely in the board | substrate was provided. FIG. 12B is a cross-sectional view of the semiconductor package shown in FIG. 12A taken along the line 12B-12B. It is a top view of the semiconductor package which shows the other example of the shape and arrangement | positioning of the member for local deformation | transformation. It is a top view of the semiconductor package which shows the other example of the shape and arrangement | positioning of the member for local deformation | transformation. It is a top view of the semiconductor package which shows the other example of the shape and arrangement | positioning of the member for local deformation | transformation. It is sectional drawing of an example of the system in package by this invention. It is a top view of the conventional semiconductor package. FIG. 17B is a cross-sectional view of the semiconductor package shown in FIG. 17A when the semiconductor chip and the substrate are flip-flop connected and then returned to room temperature. FIG. 17C is a cross-sectional view taken along line 17C-17C during heating of the semiconductor package illustrated in FIG. 17A. FIG. 17D is a cross-sectional view taken along line 17D-17D during heating of the semiconductor package illustrated in FIG. 17A.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Board | substrate 3 External connection terminal 4 Underfill resin 7 Local deformation member

Claims (6)

A substrate on which a semiconductor chip is mounted,
A chip mounting area in which a semiconductor chip is mounted;
An external connection region located outside the chip mounting region and provided with terminals for electrical connection with the outside;
The warpage generated in the chip mounting area when the substrate is heated in a state where the semiconductor chip is mounted in the chip mounting area provided integrally with the substrate in a portion outside the chip mounting area. A member for local deformation having a thermal expansion coefficient different from that of the substrate so as to locally deform the substrate in a direction opposite to the direction;
Have
The local deformation member is provided on a portion between the chip mounting region and the external connection region so as to surround the outer peripheral portion of the chip mounting region over the entire circumference. The substrate according to claim 1, wherein the local deformation member is located on a chip mounting surface side on which the semiconductor chip is mounted, and a thermal expansion coefficient is larger than a thermal expansion coefficient of the substrate. The local deformation member is located on a chip non-mounting surface side opposite to a chip mounting surface on which the semiconductor chip is mounted, and a thermal expansion coefficient is smaller than a thermal expansion coefficient of the substrate. Item 4. The substrate according to Item 1 . The semiconductor chip groove is formed on the surface of the chip mounting surface or opposite side is mounted, the local deformation member is provided in the groove, the substrate according to any one of claims 1 3 . The substrate according to any one of claims 1 to 3 , wherein the local deformation member is provided on a chip mounting surface on which the semiconductor chip is mounted or on the opposite surface. A recess is formed having a larger planar size than the planar size of the semiconductor chip on one side of the front Stories substrate, wherein the semiconductor chip is mounted on the substrate in said recess, said local deformation member fills the recess The board | substrate of Claim 1 or 2 provided .

Images