JP4536291B2 - Semiconductor chip mounting structure and manufacturing method thereof - Google Patents

Semiconductor chip mounting structure and manufacturing method thereof Download PDF

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Publication number
JP4536291B2
JP4536291B2 JP2001178525A JP2001178525A JP4536291B2 JP 4536291 B2 JP4536291 B2 JP 4536291B2 JP 2001178525 A JP2001178525 A JP 2001178525A JP 2001178525 A JP2001178525 A JP 2001178525A JP 4536291 B2 JP4536291 B2 JP 4536291B2
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Prior art keywords
semiconductor chip
circuit board
input
mounting structure
stacked
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JP2002373966A (en
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豊 熊野
豊 田口
善広 戸村
峰広 板垣
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting structure for a semiconductor chip and a method for manufacturing the same that can achieve high-density packaging and are applicable in the coming high-speed signal age. SOLUTION: The mounting structure for the semiconductor chip is constituted of a circuit board, the semiconductor chip of two or more layers which are overlaid vertically on the circuit board and have flip chips mounted thereon, and a conductive connecting member for connecting an input/output electrode placed at the edge of the semiconductor chip on each layer to a wiring electrode on the circuit board. The conductive connecting member of the semiconductor chip on an upper layer is arranged outside the outer edge of the semiconductor chip on a lower layer. The semiconductor chip on the lower layer is close to the connecting member under the semiconductor chip on the upper layer.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップの実装構造体及びその製造方法に関する。
【０００２】
【従来の技術】
電子機器の高性能化、小型化の進展に伴い、高密度に実装された半導体パッケージの需要が増している。その高密度パッケージ形態として、一つの半導体チップをほぼそのチップサイズでパッケージ化したＣＳＰ（Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）や複数個の半導体チップを平面方向に配列実装したＭＣＭ（Ｍｕｌｔｉｃｈｉｐ Ｍｏｄｕｌｅ）などが使用されている。
【０００３】
近年、さらなる実装面積の低減のために、複数の半導体チップを高さ方向に積層して実装することにより、実装密度を高めたスタックドＣＳＰと呼ばれる構造が提案されている。例えば、特開平１１−２０４７２０号には、複数の半導体チップを、一つの回路基板上に、高さ方向に積層して実装し、ワイヤーボンディング法により半導体チップと回路基板間との電気的接続を行ったスタックドＣＳＰが開示されている。
【０００４】
しかしながら、ワイヤボンディング法は、高速信号に対する配線損失が大きい。そのため、今後の高速信号時代には、ワイヤボンディング法に代わる新しい接続方式が望まれている。
【０００５】
そこで、本発明は、高密度実装が可能で、かつ、今後の高速信号時代に適用可能な、ワイヤボンディング法に代わる新しい接続方式を有する半導体チップの実装構造体及びその製造方法を提供することを目的とした。
【０００６】
【課題を解決するための手段】
上記課題を解決すべく、本発明の半導体チップの実装構造体は、回路基板と、該回路基板上に重積してフリップチップ搭載された２層以上の半導体チップと、各層の半導体チップの縁部に配置した入出力電極を回路基板上の配線電極上に接続する導電性接続部材とからなる半導体チップの実装構造体であって、表面に段差を有する前記回路基板上に、上層の半導体チップの入出力電極に対応する配線電極を、その位置が前記下層の半導体チップの入出力電極に対応する配線電極よりも高くなるように配置し、前記導電性接続部材を下層の半導体チップの外縁より外側に配列した前記上層の半導体チップを前記下層の半導体チップ上に重積して成り、さらに前記上層の半導体チップと前記下層の半導体チップの間に設けた補強用接着剤層と、前記回路基板と重積された半導体チップとの間隙を充填する封止部を有し、前記補強用接着剤層に前記封止部よりも弾性率の低い接着性樹脂を用いて成ることを特徴とする。
【０００７】
本発明の実装構造体は、上層の半導体チップを、その導電性接続部材が、上層の半導体チップの下方で近接する下層の半導体チップの外縁より外側に配列されるようにしたので、複数の半導体チップを重積して回路基板上にフリップチップ搭載することができる。これにより、複数の半導体チップと回路基板との間の配線長を短くすることができるので、配線損失を低減することが可能となる。
【０００８】
また、本発明の実装構造体には、上層の半導体チップが、下層の半導体チップを覆うように集積されたものを用いることができる。
【０００９】
また、本発明の実装構造体には、上層及び下層の半導体チップの平面が長方形状であって、上層及び下層の半導体チップの短辺側の縁部には入出力電極が形成され、下層の半導体チップの長辺に上層の半導体チップの長辺が交差するように上層の半導体チップが下層の半導体チップを跨って配置されたものを用いることができる。
【００１０】
また、本発明の半導体チップの実装構造体の製造方法は、回路基板と、該回路基板上に重積してフリップチップ搭載された２層以上の半導体チップと、各層の半導体チップの回路形成面の縁部に配置した入出力電極を回路基板上の配線電極上に接続する導電性接続部材とからなる半導体チップの実装構造体の製造方法であって、前記回路基板の表面に段差を設け、上層の半導体チップの入出力電極に対応する配線電極を、下層の半導体チップの入出力電極に対応する配線電極よりも高くなるように前記回路基板上に配置し、前記入出力電極を前記下層の半導体チップの外縁より外側に配列した前記上層側の半導体チップを、前記下層の半導体チップ上に重積し、前記上層の半導体チップの入出力電極と回路基板上の対応する配線電極とを別体の導電性接続部材を介して接続して、回路基板上に搭載する工程と、前記回路基板上に前記のすべての半導体チップを重積した後、前記回路基板と前記の半導体チップとの間隙に液状の封止樹脂を注入して封止部を形成する工程を含み、
前記下層の半導体チップの回路形成面の反対面に、前記封止部よりも弾性率の低い接着性樹脂からなる補強用接着性樹脂を塗布し、前記上層の半導体チップを前記下層の半導体チップに接合して重積することを特徴とする。
【００１１】
また、本発明の製造方法は、前記の回路基板上に搭載する工程を繰り返して半導体チップを重積することができる。
【００１２】
また、本発明の製造方法は、半導体チップを３層以上重積することが好ましい。
【００１３】
また、本発明の製造方法は、予め入出力電極に導電性接続部材が接合された半導体チップを用いることができる。
【００１４】
また、本発明の製造方法は、予め配線電極に導電性接続部材が接合された回路基板を用いることもできる。
【００１５】
【発明実施の形態】
以下、図面を用いて本発明をさらに詳細に説明する。
実施の形態１．
図１（ａ）〜図１（ｄ）は、本実施の形態に係る半導体チップの実装構造体の製造工程を示す模式断面図である。ここで、１は回路基板、２ａは第１の配線電極、２ｂは第２の配線電極、２ｃは第３の配線電極、３は第１の半導体チップ、３ａは第１の半導体チップの入出力電極、３ｂは第１の導電性接続部材、４は第２の半導体チップ、４ａは第２の半導体チップの入出力電極、４ｂは第２の導電性接続部材、５は第３の半導体チップ、５ａは第３の半導体チップの入出力電極、５ｂは第３の導電性接続部材、６は封止部である。
【００１６】
予め入出力電極上に導電性接続部材を形成した半導体チップ３，４，５を用意する。次に、入出力電極３ａと対応する第１の配線電極２ａとを位置合せし、入出力電極３ａと第１の配線電極２とを第１の導電性接続部材３ｂを介して接続して、第１の半導体チップ３を回路基板１にフリップチップ搭載する（図１（ａ））。
【００１７】
次いで、下層側の第１の半導体チップ３の外縁より外側に入出力電極４ａを配列した上層側の第２の半導体チップ４を、第１の半導体チップ３を覆って重積し、第２の半導体チップの入出力電極４ａと回路基板1上の対応する配線電極２ｂとを第２の導電性接続部材４ｂを介して接続し、第２の半導体チップ４を回路基板１にフリップチップ搭載する（図１（ｂ））。ここで、第２の導電性接続部材４ｂを、上層にある第２の半導体チップ４の下方で近接する下層にある第１の半導体チップ３の外縁よりも外側に配列させる。
【００１８】
次いで、下層側の第２の半導体チップ４の外縁より外側に入出力電極５ａを配列した上層側の第３の半導体チップ５を、第２の半導体チップ４を覆って重積し、第３の半導体チップの入出力電極５ａと回路基板1上の対応する配線電極２ｃとを第３の導電性接続部材５ｂを介して接続し、第３の半導体チップ５を回路基板１にフリップチップ搭載する。（図１（ｃ））。ここで、第３の導電性接続部材５ｂを、上層にある第３の半導体チップ５の下方で近接する下層にある第２の半導体チップ４の外縁よりも外側に配列させる。
【００１９】
次いで、重積された第１から第３の半導体チップ３，４，５と回路基板１との間隙に封止樹脂を1回で注入して硬化させ、封止部６を形成する（図１（ｄ））。これにより、３層の半導体チップからなる実装構造体を作製することができる。
【００２０】
本実施の形態に係る実装構造体は、導電性接続部材を上層の半導体チップの下方で近接する下層の半導体チップの外縁よりも外側に配列させ、複数の半導体チップをフリップチップ搭載により回路基板上に積層実装したので、ワイヤボンディング法を用いた実装構造体に比べ、回路基板との間の配線長を短くすることができるので、配線損失を低減することが可能となり、また、ワイヤボンディングが不要となり実装構造体の高さを低くできるので、より高密度の実装が可能となる。
【００２１】
ここで、入出力電極と配線電極の接続に用いる導電性接続部材には、例えば、金属バンプを用いることができる。金属バンプは、従来公知の方法を用いて形成することができる。例えば、金属ワイヤの一端に金属ボールを形成し、この金属ボールを入出力電極上に搭載した後、ワイヤをひきちぎることにより形成することができる。これにより、金属バンプの形成と入出力電極への接合を同時に行うことができる。本実施の形態では、金属バンプを入出力電極に接合した場合を示したが、入出力電極に代えて配線電極を用いることにより、金属バンプを配線電極に接合することができる。
【００２２】
また、上層側の半導体チップの入出力電極は、下層側の半導体チップの入出力電極よりも外側に配置する必要がある。しかし、最下層の半導体チップの入出力電極は、半導体チップの回路形成面内であれば、その位置は限定されない。
【００２３】
また、上層の半導体チップの導電性接続部材の高さを、下層の半導体チップの導電性接続部材よりも、概ね上層の半導体チップの厚さの分だけ高くなるように形成することが好ましい。
【００２４】
また、本実施の形態では、すべての半導体チップを回路基板に搭載後、半導体チップと回路基板との間隙に封止樹脂を注入して封止部を形成する場合を示したが、予め封止樹脂を配線電極を除く回路基板の表面の全面に塗布し、あるいは、絶縁性シートを配線電極を除く回路基板の表面の全面に張り付けて、各半導体チップを回路基板に順に搭載する方法を用いることもできる。
【００２５】
ここで、上記の封止樹脂にはエポキシ樹脂等の熱硬化性樹脂を用いることが好ましい。
【００２６】
実施の形態２．
図２（ａ）〜図２（ｄ）は、本実施の形態に係る半導体チップの実装構造体の製造工程を示す模式断面図である。本実施の形態の実装構造体は、回路基板に、段差を設けた回路基板１０を用い、半導体チップの間に仮止め用の補強用接着剤層７を設けた以外は、実施の形態１と同様の構造を有する。
【００２７】
回路基板１０は、表面に凹部１１と、凹部１１の底面１１ａの外縁と段差を介して連続する中断面１２と、中断面１２の外縁と段差を介して連続する上断面１３とを有している。底面１１ａには第１の配線電極２ａ、中断面１２には第２の配線電極、そして上断面１３には第３の配線電極を設ける。
【００２８】
まず、入出力電極３ａと対応する第１の配線電極２ａとを位置合せし、入出力電極３ａと第１の配線電極２とを導電性接続部材３ｂを介して接続して、第１の半導体チップ３を回路基板１０にフリップチップ搭載する（図２（ａ））。
【００２９】
次いで、第１の半導体チップ３の回路形成面の反対面に接着性樹脂を塗布した後、下層側の第１の半導体チップ３の外縁より外側に入出力電極４ａを配列した上層側の第２の半導体チップ４を、第１の半導体チップ３を覆って補強用接着剤層７を介して重積し、第２の半導体チップ４の入出力電極４ａと回路基板１０上の対応する配線電極２ｂとを第２の導電性接続部材４ｂを介して接続し、第２の半導体チップ４を回路基板１０にフリップチップ搭載する（図２（ｂ））。
【００３０】
次いで、第２の半導体チップ４の回路形成面の反対面に接着性樹脂を塗布した後、下層側の第２の半導体チップ４の外縁より外側に入出力電極５ａを配列した上層側の第３の半導体チップ５を、第２の半導体チップ４を覆って補強用接着剤層７を介して重積し、第３の半導体チップの入出力電極５ａと回路基板１０上の対応する配線電極２ｃとを第２の導電性接続部材５ｂを介して接続し、第３の半導体チップ５を回路基板１０にフリップチップ搭載する（図２（ｃ））。次いで、重積された第１から第３の半導体チップ３，４，５と回路基板１０との間隙に封止樹脂を１回で注入して硬化させ、封止樹脂層６を形成する（図２（ｄ））。これにより、３層の半導体チップからなる実装構造体を作製することができる。
【００３１】
本実施の形態によれば、実施の形態１と同様の効果が得られるのみならず、集積する半導体チップの導電性接続部材の長さをすべて同一にすることができ、層毎に導電性接続部材の作製条件を変化させる必要がないので、製造プロセスの効率化が可能となる。また、下層側の半導体チップの回路形成面の反対面に補強用接着剤層を設けて上層側の半導体チップを重積することにより、半導体チップ同士を仮止めすることができる。これにより、実装時の半導体チップの操作性を向上させることができる。
【００３２】
ここで、接着性樹脂には、熱硬化性樹脂及び熱可塑性樹脂のいずれも用いることができるが、最後に一度に封止を行う場合には、封止樹脂よりも弾性率の低い接着性樹脂を用いることが好ましい。
【００３３】
本実施の形態では、半導体チップ間に仮止め用の補強用接着剤層を設けた例を示したが、この補強用接着剤層を実施の形態１に適用することもできる。
【００３４】
なお、実施の形態１及び２では、半導体チップを1個ずつ搭載した例を示したが、予め接着性樹脂を用いて複数の半導体チップを仮止めして一体化し、その一体化した複数の半導体チップを一度に回路基板に搭載する方法を用いることもできる。
【００３５】
また、実施の形態１及び２では、下層の半導体チップを覆うように上層の半導体チップを集積した例を示したが、上層及び下層の半導体チップとして、その平面が長方形状のものを用いて、以下のように集積することもできる。すなわち、上層及び下層の半導体チップの短辺側の縁部に入出力電極を形成し、下層の半導体チップの長辺に上層の半導体チップの長辺が交差、好ましくは直交するように、下層の半導体チップを跨って上層の半導体チップを配置することができる。
【００３６】
また、実施の形態1及び２では、３層の半導体チップからなる実装構造体の例を示したが、これに限定されるものではなく、２層以上の半導体チップからなる実装構造体にも適用できることは言うまでもない。
【００３７】
【発明の効果】
以上説明したように、本発明の半導体チップの実装構造体は、回路基板上に上下に重積してフリップチップ搭載された２層以上の半導体チップを有し、上層の半導体チップは、その導電性接続部材が、上層の半導体チップの下方で近接する下層の半導体チップの外縁より外側に配列されているので、回路基板との間の配線長を短くすることができるので、配線損失を低減することが可能となる。また、実装構造体の高さを低くできるので、より高密度の実装が可能となる。
【００３８】
また、本発明の実装構造体は、回路基板の表面に段差を設け、上層側の半導体チップ用の配線電極の位置を、下層側の半導体チップ用の配線電極の位置よりも高くしたので、導電性接続部材の厚さを一定にすることができ、製造プロセスの効率化が可能となる。
【００３９】
また、本発明の実装構造体は、上層の半導体チップが下層の半導体チップを覆うように集積されているので、上層の半導体チップの位置合せが容易となり、製造プロセスの効率化が可能となる。
【００４０】
また、本発明の実装構造体は、下層の半導体チップの長辺に上層の半導体チップの長辺が交差するように、下層の半導体チップを跨って上層の半導体チップが配置されており、上層の半導体チップが必ずしも下層の半導体チップを覆う必要がないので、半導体チップの面積を小さくすることができ、より高密度の実装が可能となる。
【００４１】
また、本発明の実装構造体は、下層の半導体チップと上層の半導体チップとを接合する補強用樹脂層を有しているので、実装時の半導体チップの取扱いが容易となり、製造プロセスの効率の向上が可能となる。
【００４２】
また、本発明の実装構造体は、回路基板と重積された複数の半導体チップとの間隙を充填する封止部を有しているので、半導体チップを外部環境から保護することができ、実装構造体の信頼性を向上させることが可能となる。
【００４３】
また、本発明の実装構造体の製造方法は、入出力電極を下層の半導体チップの外縁より外側に配列した上層側の半導体チップを、下層の半導体チップ上に集積し、上層側の半導体チップの入出力電極と回路基板上の対応する配線電極とを別体の導電性接続部材を介して接続して、回路基板上に搭載するようにしたので、半導体チップの積層実装が可能となる。さらに、この工程を繰り返すことにより、容易に複数の半導体チップをフリップチップ搭載することができる。
【００４４】
また、本発明の製造方法は、３層以上の半導体チップを積層実装する場合に好適に使用することができ、ワイヤボンディング法に比べ、配線損失を低減し、かつ、より高密度の実装が可能となる。
【００４５】
また、本発明の製造方法は、下層の半導体チップの回路形成面の反対面に接着性樹脂を塗布し、上層の半導体チップを下層の半導体チップに接合して重積するようにしたので、実装時の半導体チップの操作性を向上させ、製造プロセスの効率を向上させることが可能となる。
【００４６】
また、本発明の製造方法は、回路基板の表面に段差を設け、上層側の半導体チップの入出力電極に対応する配線電極を、その位置が下層側の半導体チップの入出力電極に対応する配線電極よりも高くなるように配置したので、導電性接続部材の厚さを一定にすることができ、製造プロセスの効率化が可能となる。
【００４７】
また、本発明の製造方法は、導電性接続部材が予め接合された半導体チップを用いるようにしたので、導電性接続部材を形成する工程を省くことができ、製造プロセスの効率化を図ることができる。
【００４８】
また、本発明の製造方法は、導電性接続部材が予め配線電極に接合された回路基板を用いるようにしたので、導電性接続部材を形成する工程を省くことができ、製造プロセスの効率化を図ることができる。
【００４９】
また、本発明の製造方法は、回路基板上に複数の半導体チップを重積した後、回路基板と半導体チップとの間隙に液状の封止樹脂を注入して封止部を形成するようにしたので、実装に要する時間を短縮することができ、製造プロセスの効率を向上させることが可能となる。
【００５０】
また、本発明の製造方法は、半導体チップを回路基板に搭載するに先立って、配線電極を除く回路基板表面の全面に、封止樹脂を塗布し、あるいは絶縁性シートを張り付けて封止部を形成するようにしたので、実装に要する時間を短縮することができ、製造プロセスの効率を向上させることが可能となる。
【図面の簡単な説明】
【図１】 本発明の実施の形態１に係る半導体チップの実装構造体の製造工程を示す模式断面図である。
【図２】 本発明の実施の形態２に係る半導体チップの実装構造体の製造工程を示す模式断面図である。
【符号の説明】
１,１０ 回路基板、２ａ 第１の配線電極、２ｂ 第２の配線電極、２ｃ 第３の配線電極、３ 第１の半導体チップ、３ａ 第１の半導体チップの入出力電極、３ｂ 第１の導電性接続部材、４ 第２の半導体チップ、４ａ 第２の半導体チップの入出力電極、４ｂ 第２の導電性接続部材、５ 第１の半導体チップ、５ａ 第１の半導体チップの入出力電極、５ｂ 第１の導電性接続部材、６ 封止部、７ 補強用接着剤層、１１ 回路基板の凹部、１１ａ 凹部の底面、１２ 中断面、１３ 上断面。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor chip mounting structure and a method for manufacturing the same.
[0002]
[Prior art]
With the progress of high performance and miniaturization of electronic devices, the demand for semiconductor packages mounted at high density is increasing. As the high-density package form, a CSP (Chip Scale Package) in which one semiconductor chip is packaged with almost the same chip size, or an MCM (Multichip Module) in which a plurality of semiconductor chips are arranged and mounted in a planar direction are used. .
[0003]
In recent years, in order to further reduce the mounting area, a structure called stacked CSP has been proposed in which a plurality of semiconductor chips are stacked and mounted in the height direction to increase the mounting density. For example, in Japanese Patent Laid-Open No. 11-204720, a plurality of semiconductor chips are stacked and mounted on a single circuit board in the height direction, and electrical connection between the semiconductor chip and the circuit board is performed by a wire bonding method. The stacked CSP performed is disclosed.
[0004]
However, the wire bonding method has a large wiring loss for high-speed signals. Therefore, in the future high-speed signal era, a new connection method that replaces the wire bonding method is desired.
[0005]
Accordingly, the present invention provides a semiconductor chip mounting structure having a new connection method instead of the wire bonding method and a manufacturing method thereof, which can be mounted at high density and can be applied in the future high-speed signal age. It was aimed.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor chip mounting structure according to the present invention includes a circuit board, two or more semiconductor chips stacked on the circuit board and mounted on a flip chip, and an edge of each layer of semiconductor chips. A semiconductor chip mounting structure comprising a conductive connecting member for connecting input / output electrodes arranged on a wiring electrode on a circuit board, wherein the upper semiconductor chip is formed on the circuit board having a step on the surface. The wiring electrodes corresponding to the input / output electrodes of the lower semiconductor chip are arranged so that the positions thereof are higher than the wiring electrodes corresponding to the input / output electrodes of the lower semiconductor chip, and the conductive connecting member is disposed from the outer edge of the lower semiconductor chip. The upper semiconductor chip arranged outside is stacked on the lower semiconductor chip, and further includes a reinforcing adhesive layer provided between the upper semiconductor chip and the lower semiconductor chip, And characterized by using the circuit board and has a seal filling the gap between the stacking semiconductor chips, the sealing portion less adhesive resin elastic modulus than the reinforcing adhesive layer To do.
[0007]
In the mounting structure according to the present invention, the upper semiconductor chip has the conductive connecting member arranged outside the outer edge of the lower semiconductor chip adjacent to the lower semiconductor chip. Chips can be stacked and flip-chip mounted on a circuit board. As a result, the wiring length between the plurality of semiconductor chips and the circuit board can be shortened, so that the wiring loss can be reduced.
[0008]
In the mounting structure of the present invention, an upper layer semiconductor chip integrated so as to cover the lower layer semiconductor chip can be used.
[0009]
In the mounting structure of the present invention, the planes of the upper and lower semiconductor chips are rectangular, and input / output electrodes are formed on the short side edges of the upper and lower semiconductor chips. It is possible to use a semiconductor chip in which the upper semiconductor chip is disposed across the lower semiconductor chip so that the long side of the upper semiconductor chip intersects the long side of the semiconductor chip.
[0010]
In addition, a method for manufacturing a semiconductor chip mounting structure according to the present invention includes a circuit board, two or more semiconductor chips stacked on the circuit board and mounted on a flip chip, and a circuit formation surface of each layer of semiconductor chips. A method of manufacturing a semiconductor chip mounting structure comprising a conductive connection member for connecting input / output electrodes arranged on the edge of the circuit board on a wiring electrode on a circuit board , wherein a step is provided on the surface of the circuit board, The wiring electrodes corresponding to the input / output electrodes of the upper semiconductor chip are arranged on the circuit board so as to be higher than the wiring electrodes corresponding to the input / output electrodes of the lower semiconductor chip, and the input / output electrodes are arranged on the lower layer. the upper side of the semiconductor chip which are arranged outside the outer edge of the semiconductor chip, and intussusception on the lower semiconductor chip, separate from the corresponding wiring electrodes on the input and output electrodes and the circuit substrate of the upper layer of the semiconductor chip Connected through a conductive connecting member, after Juseki the step of mounting, all of the semiconductor chip above the circuit board on a circuit board, a liquid in a gap between said circuit board the semiconductor chip A step of injecting a sealing resin to form a sealing portion,
A reinforcing adhesive resin made of an adhesive resin having a lower elastic modulus than the sealing portion is applied to the surface opposite to the circuit formation surface of the lower semiconductor chip, and the upper semiconductor chip is applied to the lower semiconductor chip. It is characterized by joining and stacking .
[0011]
Moreover, the manufacturing method of this invention can repeat a process mounted on the said circuit board, and can stack | stack a semiconductor chip.
[0012]
In the manufacturing method of the present invention, it is preferable to stack three or more semiconductor chips.
[0013]
Further, the manufacturing method of the present invention can use a semiconductor chip in which a conductive connecting member is bonded to input / output electrodes in advance.
[0014]
The manufacturing method of the present invention can also use a circuit board in which a conductive connecting member is bonded to a wiring electrode in advance.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail with reference to the drawings.
Embodiment 1 FIG.
FIG. 1A to FIG. 1D are schematic cross-sectional views showing a manufacturing process of a semiconductor chip mounting structure according to the present embodiment. Here, 1 is a circuit board, 2a is a first wiring electrode, 2b is a second wiring electrode, 2c is a third wiring electrode, 3 is a first semiconductor chip, and 3a is an input / output of the first semiconductor chip. Electrode, 3b is a first conductive connection member, 4 is a second semiconductor chip, 4a is an input / output electrode of the second semiconductor chip, 4b is a second conductive connection member, 5 is a third semiconductor chip, 5a is an input / output electrode of the third semiconductor chip, 5b is a third conductive connecting member, and 6 is a sealing portion.
[0016]
Semiconductor chips 3, 4, and 5 in which conductive connection members are previously formed on input / output electrodes are prepared. Next, the input / output electrode 3a and the corresponding first wiring electrode 2a are aligned, and the input / output electrode 3a and the first wiring electrode 2 are connected via the first conductive connection member 3b. The first semiconductor chip 3 is flip-chip mounted on the circuit board 1 (FIG. 1A).
[0017]
Next, the second semiconductor chip 4 on the upper layer side in which the input / output electrodes 4a are arranged outside the outer edge of the first semiconductor chip 3 on the lower layer side is stacked so as to cover the first semiconductor chip 3, and the second The input / output electrodes 4a of the semiconductor chip and the corresponding wiring electrodes 2b on the circuit board 1 are connected via the second conductive connection member 4b, and the second semiconductor chip 4 is flip-chip mounted on the circuit board 1 ( FIG. 1 (b)). Here, the second conductive connection member 4b is arranged outside the outer edge of the first semiconductor chip 3 in the lower layer adjacent to the lower layer of the second semiconductor chip 4 in the upper layer.
[0018]
Next, the third semiconductor chip 5 on the upper layer side, in which the input / output electrodes 5a are arranged outside the outer edge of the second semiconductor chip 4 on the lower layer side, is stacked so as to cover the second semiconductor chip 4, and the third The input / output electrodes 5a of the semiconductor chip and the corresponding wiring electrodes 2c on the circuit board 1 are connected via the third conductive connection member 5b, and the third semiconductor chip 5 is flip-chip mounted on the circuit board 1. (FIG. 1 (c)). Here, the third conductive connection member 5b is arranged outside the outer edge of the second semiconductor chip 4 in the lower layer adjacent to the lower side of the third semiconductor chip 5 in the upper layer.
[0019]
Next, sealing resin is injected into the gap between the stacked first to third semiconductor chips 3, 4, 5 and the circuit board 1 at one time and cured to form the sealing portion 6 (FIG. 1). (D)). Thereby, the mounting structure which consists of a three-layer semiconductor chip is producible.
[0020]
In the mounting structure according to the present embodiment, the conductive connecting members are arranged outside the outer edge of the lower semiconductor chip adjacent to the lower semiconductor chip below the upper semiconductor chip, and a plurality of semiconductor chips are mounted on the circuit board by flip chip mounting. Since it is mounted in layers, the wiring length to the circuit board can be shortened compared to the mounting structure using the wire bonding method, so that the wiring loss can be reduced and no wire bonding is required. Since the height of the mounting structure can be reduced, higher density mounting is possible.
[0021]
Here, for example, metal bumps can be used as the conductive connection member used for connecting the input / output electrodes and the wiring electrodes. The metal bump can be formed using a conventionally known method. For example, the metal ball can be formed by forming a metal ball on one end of the metal wire and mounting the metal ball on the input / output electrode, and then tearing the wire. Thereby, formation of a metal bump and joining to an input / output electrode can be performed simultaneously. Although the case where the metal bumps are bonded to the input / output electrodes has been described in this embodiment mode, the metal bumps can be bonded to the wiring electrodes by using the wiring electrodes instead of the input / output electrodes.
[0022]
In addition, the input / output electrodes of the upper semiconductor chip must be arranged outside the input / output electrodes of the lower semiconductor chip. However, the position of the input / output electrodes of the lowermost semiconductor chip is not limited as long as it is within the circuit formation surface of the semiconductor chip.
[0023]
In addition, it is preferable that the conductive connecting member of the upper semiconductor chip is formed so as to be higher than the conductive connecting member of the lower semiconductor chip by approximately the thickness of the upper semiconductor chip.
[0024]
In the present embodiment, after all the semiconductor chips are mounted on the circuit board, a sealing resin is injected into the gap between the semiconductor chip and the circuit board to form a sealing portion. Applying resin to the entire surface of the circuit board except for the wiring electrodes, or attaching an insulating sheet to the entire surface of the circuit board except for the wiring electrodes and mounting each semiconductor chip on the circuit board in sequence. You can also.
[0025]
Here, it is preferable to use a thermosetting resin such as an epoxy resin for the sealing resin.
[0026]
Embodiment 2. FIG.
FIG. 2A to FIG. 2D are schematic cross-sectional views showing the manufacturing process of the semiconductor chip mounting structure according to the present embodiment. The mounting structure of the present embodiment is the same as that of the first embodiment except that the circuit board 10 having a step is provided on the circuit board and the reinforcing adhesive layer 7 for temporary fixing is provided between the semiconductor chips. It has a similar structure.
[0027]
The circuit board 10 has a concave portion 11 on the surface, a middle cross section 12 continuous through a step with the outer edge of the bottom surface 11a of the concave portion 11, and an upper cross section 13 continuous with the outer edge of the middle cross section 12 through a step. Yes. A first wiring electrode 2 a is provided on the bottom surface 11 a, a second wiring electrode is provided on the middle cross section 12, and a third wiring electrode is provided on the upper cross section 13.
[0028]
First, the input / output electrode 3a and the corresponding first wiring electrode 2a are aligned, the input / output electrode 3a and the first wiring electrode 2 are connected via the conductive connection member 3b, and the first semiconductor The chip 3 is flip-chip mounted on the circuit board 10 (FIG. 2A).
[0029]
Next, an adhesive resin is applied to the surface opposite to the circuit formation surface of the first semiconductor chip 3, and then the second I / O electrode 4 a is arranged outside the outer edge of the first semiconductor chip 3 on the lower layer side. The semiconductor chip 4 is stacked on the first semiconductor chip 3 through the reinforcing adhesive layer 7, and the input / output electrodes 4 a of the second semiconductor chip 4 and the corresponding wiring electrodes 2 b on the circuit board 10 are stacked. Are connected via the second conductive connection member 4b, and the second semiconductor chip 4 is flip-chip mounted on the circuit board 10 (FIG. 2B).
[0030]
Next, after applying an adhesive resin to the surface opposite to the circuit formation surface of the second semiconductor chip 4, the upper layer side third in which the input / output electrodes 5 a are arranged outside the outer edge of the lower layer side second semiconductor chip 4. The semiconductor chip 5 is stacked over the second semiconductor chip 4 via the reinforcing adhesive layer 7, and the input / output electrodes 5 a of the third semiconductor chip and the corresponding wiring electrodes 2 c on the circuit board 10 are stacked. Are connected via the second conductive connection member 5b, and the third semiconductor chip 5 is flip-chip mounted on the circuit board 10 (FIG. 2C). Next, the sealing resin is injected into the gap between the stacked first to third semiconductor chips 3, 4, 5 and the circuit board 10 at one time and cured to form the sealing resin layer 6 (FIG. 2 (d)). Thereby, the mounting structure which consists of a three-layer semiconductor chip is producible.
[0031]
According to the present embodiment, not only the same effects as in the first embodiment can be obtained, but also the lengths of the conductive connection members of the integrated semiconductor chips can be made the same, and the conductive connection for each layer. Since it is not necessary to change the production conditions of the member, the manufacturing process can be made more efficient. Further, by providing a reinforcing adhesive layer on the surface opposite to the circuit formation surface of the lower semiconductor chip and stacking the upper semiconductor chips, the semiconductor chips can be temporarily fixed. Thereby, the operativity of the semiconductor chip at the time of mounting can be improved.
[0032]
Here, as the adhesive resin, either a thermosetting resin or a thermoplastic resin can be used. However, when sealing is performed at the end, the adhesive resin has a lower elastic modulus than the sealing resin. Is preferably used.
[0033]
In this embodiment mode, an example in which a reinforcing adhesive layer for temporary fixing is provided between semiconductor chips has been described. However, this reinforcing adhesive layer layer can also be applied to Embodiment Mode 1.
[0034]
In the first and second embodiments, the example in which the semiconductor chips are mounted one by one is shown. However, a plurality of semiconductor chips are temporarily fixed and integrated using an adhesive resin in advance, and the plurality of integrated semiconductors are integrated. A method of mounting chips on a circuit board at a time can also be used.
[0035]
In the first and second embodiments, the example in which the upper semiconductor chip is integrated so as to cover the lower semiconductor chip is shown. However, as the upper and lower semiconductor chips, the plane is rectangular, It can also be accumulated as follows. That is, input / output electrodes are formed on the short side edge of the upper and lower semiconductor chips, and the lower side of the lower semiconductor chip is crossed, preferably orthogonally, so that the longer side of the upper semiconductor chip intersects, preferably orthogonally An upper semiconductor chip can be arranged across the semiconductor chips.
[0036]
In the first and second embodiments, an example of a mounting structure composed of a three-layer semiconductor chip is shown. However, the present invention is not limited to this, and the present invention is also applicable to a mounting structure composed of a semiconductor chip having two or more layers. Needless to say, you can.
[0037]
【The invention's effect】
As described above, the semiconductor chip mounting structure of the present invention has two or more semiconductor chips stacked on top and bottom of the circuit board and mounted on a flip chip. Since the conductive connecting members are arranged outside the outer edge of the lower semiconductor chip adjacent to the lower semiconductor chip below the upper semiconductor chip, the wiring length to the circuit board can be shortened, thereby reducing the wiring loss. It becomes possible. Moreover, since the height of the mounting structure can be reduced, higher-density mounting is possible.
[0038]
Further, the mounting structure of the present invention has a step on the surface of the circuit board, and the position of the wiring electrode for the semiconductor chip on the upper layer side is higher than the position of the wiring electrode for the semiconductor chip on the lower layer side. The thickness of the conductive connecting member can be made constant, and the manufacturing process can be made more efficient.
[0039]
In the mounting structure of the present invention, since the upper semiconductor chip is integrated so as to cover the lower semiconductor chip, the upper semiconductor chip can be easily aligned and the manufacturing process can be made more efficient.
[0040]
In the mounting structure of the present invention, the upper semiconductor chip is disposed across the lower semiconductor chip so that the long side of the upper semiconductor chip intersects the long side of the lower semiconductor chip. Since the semiconductor chip does not necessarily need to cover the underlying semiconductor chip, the area of the semiconductor chip can be reduced, and higher-density mounting becomes possible.
[0041]
In addition, since the mounting structure of the present invention has a reinforcing resin layer that joins the lower semiconductor chip and the upper semiconductor chip, handling of the semiconductor chip during mounting is facilitated, and the efficiency of the manufacturing process is improved. Improvement is possible.
[0042]
In addition, since the mounting structure of the present invention has a sealing portion that fills the gaps between the circuit board and a plurality of stacked semiconductor chips, the semiconductor chip can be protected from the external environment and mounted. It becomes possible to improve the reliability of the structure.
[0043]
Further, in the method for manufacturing a mounting structure according to the present invention, an upper semiconductor chip in which input / output electrodes are arranged outside the outer edge of the lower semiconductor chip is integrated on the lower semiconductor chip. Since the input / output electrodes and the corresponding wiring electrodes on the circuit board are connected via a separate conductive connecting member and mounted on the circuit board, the semiconductor chips can be stacked and mounted. Furthermore, by repeating this process, a plurality of semiconductor chips can be easily mounted on a flip chip.
[0044]
In addition, the manufacturing method of the present invention can be suitably used when three or more semiconductor chips are stacked and mounted, and can reduce wiring loss and achieve higher density mounting than the wire bonding method. It becomes.
[0045]
In the manufacturing method of the present invention, the adhesive resin is applied to the surface opposite to the circuit forming surface of the lower semiconductor chip, and the upper semiconductor chip is bonded to and stacked on the lower semiconductor chip. It is possible to improve the operability of the semiconductor chip and improve the efficiency of the manufacturing process.
[0046]
In the manufacturing method of the present invention, a step is provided on the surface of the circuit board, wiring electrodes corresponding to the input / output electrodes of the upper semiconductor chip, wiring corresponding to the input / output electrodes of the lower semiconductor chip Since it arrange | positions so that it may become higher than an electrode, the thickness of an electroconductive connection member can be made constant and the efficiency improvement of a manufacturing process is attained.
[0047]
Moreover, since the manufacturing method of the present invention uses a semiconductor chip to which the conductive connecting member is bonded in advance, the step of forming the conductive connecting member can be omitted, and the manufacturing process can be made more efficient. it can.
[0048]
Moreover, since the manufacturing method of the present invention uses a circuit board in which the conductive connection member is bonded to the wiring electrode in advance, the step of forming the conductive connection member can be omitted, and the manufacturing process can be made more efficient. Can be planned.
[0049]
In the manufacturing method of the present invention, a plurality of semiconductor chips are stacked on a circuit board, and then a liquid sealing resin is injected into a gap between the circuit board and the semiconductor chip to form a sealing portion. Therefore, the time required for mounting can be shortened, and the efficiency of the manufacturing process can be improved.
[0050]
Further, in the manufacturing method of the present invention, prior to mounting the semiconductor chip on the circuit board, a sealing resin is applied to the entire surface of the circuit board surface excluding the wiring electrodes, or an insulating sheet is attached to form a sealing portion. Since it is formed, the time required for mounting can be shortened, and the efficiency of the manufacturing process can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor chip mounting structure according to a first embodiment of the present invention.
FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a semiconductor chip mounting structure according to a second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,10 Circuit board, 2a 1st wiring electrode, 2b 2nd wiring electrode, 2c 3rd wiring electrode, 3 1st semiconductor chip, 3a Input / output electrode of 1st semiconductor chip, 3b 1st electroconductivity Conductive connection member, 4 second semiconductor chip, 4a input / output electrode of second semiconductor chip, 4b second conductive connection member, 5 first semiconductor chip, 5a input / output electrode of first semiconductor chip, 5b 1st electroconductive connection member, 6 sealing part, 7 adhesive layer for reinforcement, 11 recessed part of a circuit board, 11a bottom face of a recessed part, 12 middle cross section, 13 upper cross section.

Claims (5)

回路基板と、該回路基板上に重積してフリップチップ搭載された２層以上の半導体チップと、各層の半導体チップの縁部に配置した入出力電極を回路基板上の配線電極上に接続する導電性接続部材とからなる半導体チップの実装構造体であって、
表面に段差を有する前記回路基板上に、上層の半導体チップの入出力電極に対応する配線電極を、その位置が前記下層の半導体チップの入出力電極に対応する配線電極よりも高くなるように配置し、前記導電性接続部材を下層の半導体チップの外縁より外側に配列した前記上層の半導体チップを前記下層の半導体チップ上に重積して成り、
さらに前記上層の半導体チップと前記下層の半導体チップの間に設けた補強用接着剤層と、前記回路基板と重積された半導体チップとの間隙を充填する封止部を有し、前記補強用接着剤層に前記封止部よりも弾性率の低い接着性樹脂を用いて成る実装構造体。A circuit board, two or more semiconductor chips stacked and flip-chip mounted on the circuit board, and input / output electrodes arranged at the edge of the semiconductor chip of each layer are connected to wiring electrodes on the circuit board A semiconductor chip mounting structure comprising a conductive connecting member,
A wiring electrode corresponding to the input / output electrode of the upper semiconductor chip is arranged on the circuit board having a step on the surface so that the position thereof is higher than the wiring electrode corresponding to the input / output electrode of the lower semiconductor chip. The upper connecting semiconductor chip in which the conductive connecting member is arranged outside the outer edge of the lower semiconductor chip is stacked on the lower semiconductor chip,
Further, the reinforcing adhesive layer provided between the upper semiconductor chip and the lower semiconductor chip, and a sealing portion that fills a gap between the semiconductor chip stacked on the circuit board, A mounting structure using an adhesive resin having an elastic modulus lower than that of the sealing portion for the adhesive layer . 前記の上層及び下層の半導体チップの平面が長方形状であって、上層及び下層の半導体チップの短辺側の縁部には入出力電極が形成され、下層の半導体チップの長辺に上層の半導体チップの長辺が交差するように上層の半導体チップが下層の半導体チップを跨って配置されて成る請求項１記載の実装構造体。The planes of the upper and lower semiconductor chips are rectangular, input / output electrodes are formed on the short side edges of the upper and lower semiconductor chips, and the upper semiconductor is formed on the longer sides of the lower semiconductor chips. the mounting structure of claim 1, wherein the long side of the chip, which are disposed the upper layer of the semiconductor chip over the underlying semiconductor chip so as to intersect. 回路基板と、該回路基板上に重積してフリップチップ搭載された２層以上の半導体チップと、各層の半導体チップの回路形成面の縁部に配置した入出力電極を回路基板上の配線電極上に接続する導電性接続部材とからなる半導体チップの実装構造体の製造方法であって、
前記回路基板の表面に段差を設け、上層の半導体チップの入出力電極に対応する配線電極を、下層の半導体チップの入出力電極に対応する配線電極よりも高くなるように前記回路基板上に配置し、前記入出力電極を前記下層の半導体チップの外縁より外側に配列した前記上層側の半導体チップを、前記下層の半導体チップ上に重積し、前記上層の半導体チップの入出力電極と回路基板上の対応する配線電極とを別体の導電性接続部材を介して接続して、回路基板上に搭載する工程と、
前記回路基板上に前記のすべての半導体チップを重積した後、前記回路基板と前記の半導体チップとの間隙に液状の封止樹脂を注入して封止部を形成する工程を含み、
前記下層の半導体チップの回路形成面の反対面に、前記封止部よりも弾性率の低い接着性樹脂からなる補強用接着性樹脂を塗布し、前記上層の半導体チップを前記下層の半導体チップに接合して重積する半導体チップの実装構造体の製造方法。A circuit board, two or more semiconductor chips stacked on the circuit board and mounted on a flip chip, and input / output electrodes arranged on the edge of the circuit forming surface of the semiconductor chip of each layer are wiring electrodes on the circuit board A method of manufacturing a semiconductor chip mounting structure comprising a conductive connecting member connected to the top,
A step is provided on the surface of the circuit board, and the wiring electrodes corresponding to the input / output electrodes of the upper semiconductor chip are arranged on the circuit board so as to be higher than the wiring electrodes corresponding to the input / output electrodes of the lower semiconductor chip. and, wherein the upper side of the semiconductor chip having an array of input and output electrodes on the outer side than the outer edge of the lower semiconductor chip, and intussusception on the lower semiconductor chip, input and output electrodes and the circuit substrate of the upper layer of the semiconductor chip and corresponding wiring electrodes above connected via a separate conductive connection member, a step of mounting on a circuit board,
Including stacking all the semiconductor chips on the circuit board, and then injecting a liquid sealing resin into a gap between the circuit board and the semiconductor chip to form a sealing portion,
A reinforcing adhesive resin made of an adhesive resin having a lower elastic modulus than the sealing portion is applied to the surface opposite to the circuit formation surface of the lower semiconductor chip, and the upper semiconductor chip is applied to the lower semiconductor chip. A method for manufacturing a semiconductor chip mounting structure that is bonded and stacked . 前記の回路基板上に搭載する工程を繰り返して半導体チップを重積する請求項３記載の製造方法。The manufacturing method according to claim 3, wherein semiconductor chips are stacked by repeating the step of mounting on the circuit board . 前記半導体チップを３層以上重積する請求項３又は４に記載の製造方法。The manufacturing method according to claim 3 or 4 , wherein three or more layers of the semiconductor chips are stacked.
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