JPH07321150A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a technique for controlling a bump electrode which connects a semiconductor chip with a wiring board in characteristic impedance. CONSTITUTION:A semiconductor chip 2 is bonded on the prime surface of a package board 1 through the intermediary of bump electrodes 14 and 16 piled up in layers for the formation of an LSI package, wherein a capacitor element composed of an insulating tape 17 and a pair of conductor patterns 18a and 18b formed on both the sides of the insulating tape 17 is arranged between the bump electrodes 14 and 16, and one of the electrodes of the capacitor element is connected to a signal bump electrode, and the other electrode is connected to a grounding bump electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an LSI package mounting an ultra high speed device.

[0002]

2. Description of the Related Art High-speed devices such as GaAs (gallium arsenide) LSIs are used in many fields including the transmission field, and in recent years, the processing speed has been increasing. In particular, in the field of high-speed digital transmission such as optical communication, the transmission speed far exceeds 1 [Gbit / s], and an ultra-high speed device having a transmission speed of 10 [Gbit / s] is being put to practical use.

By the way, the flip-chip method is adopted as an electrode connecting technique for semiconductor chips in an LSI package in which a high-speed device of this type is mounted. The flip chip method is to form a ball-shaped bump electrode (CCB bump) made of solder on an electrode pad of a semiconductor chip,
This is a technique of face-down bonding a semiconductor chip to a wiring board via the bump electrodes.

According to this flip-chip method, the wiring on the wiring board can be extended to the chip mounting area and the wiring and the electrode pad can be connected directly under the semiconductor chip. High-speed signal transmission becomes possible. Further, according to the flip chip method, the electrode pads can be arranged not only in the peripheral portion of the semiconductor chip but also in the central portion, so that the wiring length in the semiconductor chip can be shortened, and in this respect also, the signal transmission It is advantageous for speeding up.

LSI adopting the above flip chip method
Regarding the package, for example, JP-A-62-24942
9 and JP-A-63-310139.

Further, the LS adopting the flip chip method
As a technique for improving the I package, Japanese Patent Laid-Open No. 63-8655
There is a chip carrier described in Japanese Patent No. 4 publication. This chip carrier forms a capacitor by laminating a first metal layer (GND plate), a dielectric layer (polyimide resin), and a second metal layer on the main surface of a ceramic substrate on which a semiconductor chip is mounted, and a voltage is generated by this capacitance. We are trying to prevent drop and reduce switching noise.

Further, in Japanese Patent Laid-Open No. 64-57727, a semiconductor chip is mounted on a wiring board by a multi-stage solder bump connection method, and the diameter of the solder bump on the semiconductor chip side is larger than the diameter of the solder bump on the wiring board side. A technique for reducing the parasitic capacitance of the solder bumps and realizing high-speed signal transmission by reducing the size is described.

[0008]

When designing an LSI package in which a high speed device as described above is mounted, it is necessary to match the characteristic impedance of the signal transmission line inside the package. This is because if the characteristic impedance of the signal transmission line is mismatched when transmitting a high frequency signal, transmission loss such as signal reflection and waveform distortion occurs, and good transmission characteristics cannot be obtained.

However, the signal transmission rate is 10 [Gb
LSI with ultra-high-speed devices that exceed it / s]
In the case of a package, the mismatch of characteristic impedance and noise due to the inductance of the bump electrode connecting the semiconductor chip and the wiring board cannot be ignored. Therefore, in the conventional LSI package in which the inductance of the bump electrode is not taken into consideration, the deterioration of the electrical characteristics due to the mismatch of the characteristic impedance cannot be avoided.

An object of the present invention is to provide a technique capable of satisfactorily controlling the characteristic impedance of a bump electrode connecting a semiconductor chip and a wiring board.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The typical ones of the inventions disclosed in the present application will be outlined below.

(1) In the semiconductor integrated circuit device of the present invention, a semiconductor chip is face-down bonded via a plurality of bump electrodes stacked on the main surface of a wiring board, and a capacitance is provided between the plurality of bump electrodes. An element is arranged and one electrode thereof is connected to a bump electrode for signals and the other electrode is connected to a bump electrode for GND.

(2). The semiconductor integrated circuit device of the present invention is
In the semiconductor integrated circuit device of (1), the capacitive element is
The insulating tape is arranged between the plurality of bump electrodes and a pair of conductor patterns formed on both surfaces of the insulating tape.

(3). The semiconductor integrated circuit device according to the present invention is
In the semiconductor integrated circuit device of (1), the periphery of the signal bump electrode is surrounded by a plurality of the GND bump electrodes.

(4). A method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) a step of joining a metal ball on an electrode pad of a semiconductor chip to form a bump electrode; and (b) wiring of a wiring board. And a step of forming a bump electrode by flattening the upper surface of the metal ball after bonding the metal ball on the electrode, and (c) a capacitive element on the bump electrode formed on the wiring and the electrode of the wiring board. After mounting, the semiconductor chip on which the bump electrodes are formed is mounted on the capacitance element, and one electrode of the capacitance element is connected to the signal board bump electrodes of the wiring board and the semiconductor chip. , The step of connecting the other electrode to the GND bump electrodes of the wiring board and the semiconductor chip, respectively.

(5). The method for manufacturing a semiconductor integrated circuit device according to the present invention is the same as the method for manufacturing a semiconductor integrated circuit device according to (4) above, except that the electrode pad of the semiconductor chip, the wiring of the wiring board and the electrode pad are heated, The metal balls are joined by a ball bonding method using sound waves or energy of both.

[0018]

According to the above means, a capacitance is formed between a plurality of bump electrodes connecting the wiring board and the semiconductor chip and the capacitance component is controlled, so that the characteristic impedance of the bump electrodes is well matched. Can be made.

According to the above-mentioned means, the signal bump electrode is surrounded by the GND bump electrode, so that the crosstalk and noise of the signal flowing through the signal bump electrode can be reduced.

According to the above-mentioned means, in addition to connecting the wiring board and the semiconductor chip by using the metal balls, which are more resistant to thermal fatigue damage than solder, a plurality of metal balls (bump electrodes) are stacked. By connecting the wiring board and the semiconductor chip, the reliability and life of the connecting portion can be improved.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.

This semiconductor integrated circuit device has a package structure in which a semiconductor chip 2 face-down bonded on the main surface of a package substrate 1 is hermetically sealed with a cap 3. The semiconductor chip 2 is made of, for example, a compound semiconductor such as GaAs, and an ultrahigh-speed device that operates at a high frequency of 10 GHz or higher is formed on its main surface.

The package substrate 1 is made of ceramics such as alumina and aluminum nitride, and the wiring 4 and the electrodes 5 are provided on the main surface thereof. Also,
A GND wiring 6 and a power supply wiring 7 are provided on the inner layer of the package substrate 1. The GND wiring 6 and the power supply wiring 7 are electrically connected to the electrode 5 through the through hole 8. The wiring 4, the electrode 5, the GND wiring 6, and the power supply wiring 7 are composed of a thick film of a refractory metal such as W (tungsten) printed by a screen printing method.
And the surface of the electrode 5 is plated with Au.

A plurality of leads 9 constituting external terminals of the package are provided on the outer periphery of the main surface of the package substrate 1.
Are connected. The lead 9 is made of 42 alloy, Kovar, or the like, and is joined to the wiring 4 and the GND wiring 26 described later through the brazing material 10.

On the back surface of the package substrate 1, the GND
A metallization 11 is provided. GND metallization 1
1 is provided on the entire back surface of the package substrate 1, and is electrically connected to the GND wiring 6 through the through hole 8. The GND metallization 11 is composed of a thick film of a refractory metal such as W, and the surface thereof is made of Au.
Has been plated.

A metal base 12 having substantially the same outer dimensions as the package substrate 1 is provided on the lower surface of the GND metallization 11. The metal base 12 is, for example, 10
% Cu, and is bonded to the GND metallization 11 via the brazing filler metal 13.
The metal base 12 also functions as stabilizing the GND potential, reinforcing the package, and serving as a heat sink.

On the wiring 4 and the electrode 5 of the package substrate 1, a bump electrode 14 of Au whose upper surface is flattened by a method described later is connected. As shown in FIG. 1, in this embodiment, two bump electrodes 14 are overlaid and bonded on each wiring 4 and electrode 5. The bump electrode 14
Only one may be joined, or three or more may be stacked and joined.

On the other hand, on the electrode pad 15 of the semiconductor chip 2, a bump electrode 16 of Au having a diameter smaller than that of the bump electrode 14 is connected. In the present embodiment, two bump electrodes 16 are stacked and bonded on each electrode pad 15, but the number of bump electrodes 16 may be one, or three or more.

An insulating tape 17 made of polyimide resin or the like is interposed between the bump electrodes 14 and 16. A pair of conductor patterns 18a and 18b are formed on both surfaces of the insulating tape 17, and the conductor pattern 18a on the upper surface (semiconductor chip 2 side) and the bump electrodes 16 and the conductor pattern 1 on the lower surface (package substrate 1 side) are formed.
8b and the bump electrode 14 are joined by thermocompression bonding. Further, the conductor pattern 18a and the conductor pattern 18b are electrically connected to each other through a through hole 19 penetrating the upper and lower surfaces of the insulating tape 17. That is,
The bump electrodes 16 on the semiconductor chip 2 side and the package substrate 1
The bump electrode 14 on the side is electrically connected through the conductor pattern 18a, the through hole 19, and the conductor pattern 18b. The conductor patterns 18a and 18b are made of Cu, and their surfaces are plated with Au.

As shown enlarged in FIG. 2, a conductor pattern 18a connected to the signal bump electrode 16 (s),
A part of the conductor pattern 18b connected to the GND bump electrode 14 (GND) adjacent to this is overlapped with the main surface of the package substrate 1 in the direction perpendicular to the conductor pattern 18b. (The area surrounded by a circle)
Thus, a capacitor (C) having the insulating tape 17 as a dielectric, the conductor pattern 18a as one electrode and the conductor pattern 18b as the other electrode is formed.

A dam frame 20 surrounding the semiconductor chip 2 is provided on the outer peripheral portion of the main surface of the package substrate 1. The dam frame 20 is made of a ceramic such as alumina or aluminum nitride, and is bonded to the main surface of the package substrate 1 via a brazing material 21. A cap 3 for sealing the semiconductor chip 2 is provided on the upper surface of the dam frame 20. The cap 3 is made of a metal plate such as a 42 alloy plated with Au, and is joined to the dam frame 20 via a metallization 22 and a brazing material 23.

FIG. 3 is a plan view of the semiconductor chip 2 mounted on the main surface of the package substrate 1.

An LSI / wiring formation region 25 is arranged in a substantially central portion of the semiconductor chip 2, and a capacitive element 24 is arranged in an outer peripheral portion. Of the bump electrodes 16 formed on the semiconductor chip 2, the bump electrodes 16 (Vc
c) is arranged in almost the same area as the LSI / wiring formation area 25, and the bump electrode 16 (s) for signal is
It is arranged adjacent to the wiring formation region 25. Also, G
The bump electrode 16 (GND) for ND is arranged so as to surround the bump electrode 16 (s) for signal.

On the other hand, as shown in FIG. 4, on the main surface of the package substrate 1, the bump electrodes 16 (Vc
c), the bump electrode 16 (s) for signal and the bump electrode 16 (GND) for GND respectively corresponding to the bump electrode 14 (Vcc) for power supply and the bump electrode 14 for signal
(S), the bump electrode 14 (GND) for GND is arranged. The area surrounded by the chain double-dashed line in the figure is the area where the semiconductor chip 2 is mounted.

Further, as shown in FIG. 4, wirings 4 forming signal transmission lines and plate-shaped GND wirings 26 are alternately arranged on the main surface of the package substrate 1. That is, the package substrate 1 surrounds each wiring 4 with the GND wiring 26, the GND wiring 6 and the GND metallization 11 to reduce crosstalk and noise of signals flowing in the wiring 4. ing.

FIG. 5 is a plan view of the upper surface side (semiconductor chip 2 side) of the insulating tape 17 arranged between the package substrate 1 and the semiconductor chip 2, and FIG. 6 is a lower surface side of the insulating tape 17 (package substrate). It is a top view of the 1 side).

As shown in FIGS. 5 and 6, the insulating tape 17
Are the bump electrodes 14 (Vcc) and 16 (Vc) for the power source.
c), signal bump electrodes 14 (s), 16 (s), G
Through hole 19 (Vcc) for power supply for electrically connecting each of bump electrodes 14 (GND) and 16 (GND) for ND, through hole 19 (s) for signal, G
A through hole 19 (GND) for ND is provided.

As shown in FIG. 5, a conductor pattern 18a electrically connected to the signal through hole 19 (s) is provided on the upper surface of the insulating tape 17, and as shown in FIG. On the lower surface of the insulating tape 17, a conductor pattern 18b electrically connected to the GND through hole 19 (GND) is provided. The conductor pattern 18b on the lower surface of the insulating tape 17 has a through hole 19 for power supply.
(Vcc) and the through holes 19 (s) for signals are provided on the entire surface of the insulating tape 17 excluding the periphery thereof.

FIGS. 7 and 8 show TDR (Time Domain Reflectometry) in which the reflection coefficient of the package substrate 1 is shown as a waveform. FIG. 7 shows the reflection coefficient when the bump electrode 14 on the package substrate 1 side and the bump electrode 16 on the semiconductor chip 2 side are directly connected, and FIG. 8 shows the reflection coefficient between the bump electrode 14 and the bump electrode 16. The reflection coefficient when the insulating tape 17 of the present embodiment is arranged is shown. 7 and 8
The area surrounded by a circle is the reflection coefficient due to the inductance of the connecting portion between the package substrate 1 and the semiconductor chip 2, that is, the bump electrode portion.

The above-mentioned reflection coefficient indicates that the more it deviates from the center 0 point, the more the characteristic impedance is mismatched,
This causes deterioration of the electrical characteristics in the high frequency range. As shown in FIG. 7, the reflection coefficient of the bump electrode portion is
It takes a large value on the + side due to the inductance components of 4 and 16.

Therefore, as in the present embodiment, the bump electrode 1
By disposing the insulating tape 17 between 4 and 16 and controlling the capacitance component (negative component) of the capacitance (C) formed on the insulating tape 17, the reflection coefficient of the bump electrode portion is almost zero. The characteristic impedance can be matched well (see FIG. 8). The capacitance component is the material and thickness of the insulating tape 17, and the conductor pattern 18 formed on the upper and lower surfaces of the insulating tape 17.
It can be easily controlled by adjusting the areas of a and 18b.

Next, an example of a method of manufacturing the semiconductor integrated circuit device of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 9, a semiconductor chip 2 having an electrode pad 15 formed on its main surface is prepared. The uppermost layer of the electrode pad 15 is made of a thin film of Au. Next, as shown in FIG. 10, Au bump electrodes 16 are formed on the electrode pads 15 by a well-known ball bonding method using heating, ultrasonic waves, or energy of both. To form the bump electrode 16 on the electrode pad 15, as shown in FIGS.
The Au ball 28 formed at the tip of the is bonded onto the electrode pad 15 using the capillary 101. Next, the same figure (c),
As shown in (d), the bump 101 is formed on the electrode pad 15 by simultaneously lifting the capillary 101 and cutting the Au wire 103 by the neck portion of the Au ball 28 using the torch 102. At this time, an anchor portion 27 having a sharp tip is formed on the upper end portion of the bump electrode 16. An example of the external dimensions of the bump electrode 16 is shown in FIG. 6 (e) (dimension unit is μm).

Then, another bump electrode 16 is bonded onto each bump electrode 16 by the same method. At this time, since the anchor portion 27 formed on the lower bump electrode 16 digs into the bottom of the upper bump electrode 16, the lower bump electrode 16 and the upper bump electrode 16 can be reliably bonded.

On the other hand, a package substrate 1 as shown in FIG. 12 is prepared, and as shown in FIG. 13, two bump electrodes 14 made of Au are bonded on the respective wirings 4 and electrodes 5 so as to be joined. The bump electrodes 14 are joined by using the ball bonding method shown in FIG.

When bonding the bump electrode 14 to the wiring 4 and the electrode 5 of the package substrate 1, the bonding coordinates used when the bump electrode 16 is formed on the electrode pad 15 of the semiconductor chip 2 are mirror-inverted. Use coordinates. By doing so, even if the positions of the wirings 4 and the electrodes 5 deviate from the design coordinates due to printing misalignment or shrinkage tolerance of the package substrate 1, the central coordinates of the bump electrodes 14 and the central coordinates of the bump electrodes 16 can be accurately adjusted. Can be matched.

Next, after positioning the package substrate 1 on a horizontal stage, as shown in FIG. 14, the tool 110 is pressed against the bump electrodes 14 from above, so that all of the products as shown in FIG. At the same time, the upper surface of the bump electrode 14 is flattened. At this time, the load applied to the bump electrode 14 is about 300 gf per bump electrode 14. The bottom surface of the tool 110 is highly accurately flattened. Furthermore, by heating the tool 110 to about 400 ° C., the load applied to the bump electrode 14 can be reduced.

As described above, by simultaneously flattening the upper surfaces of all the bump electrodes 14 on the package substrate 1, the height of the bump electrodes 14 due to the warp or undulation of the main surface of the package substrate 1 can be reduced. Since the variations are absorbed, the heights of all the bump electrodes 14 can be aligned with high accuracy.

Next, as shown in FIG. 16, the insulating tape 17 having conductor patterns 18a and 18b formed on both surfaces is attached to the bottom surface of the thermocompression bonding tool 111, and is placed on the wiring 4 and the electrodes 5 of the package substrate 1. Bonded bump electrode 14
And the conductor pattern 18b on the lower surface of the insulating tape 17 are overlapped with each other and joined by thermocompression bonding.

In order to accurately overlap the bump electrodes 14 of the package substrate 1 and the conductor patterns 18b of the insulating tape 17, first, as shown in FIG. 17 (a), a half mirror 112 and an image analysis device 113 are used. Insulation tape 17
The conductor pattern 18b is recognized, and then the half mirror 112 is rotated by 90 ° to recognize the pattern of the bump electrode 14 on the package substrate 1 as shown in FIG.

Next, the insulating tape 17 is moved back and forth, left and right or rotated to superimpose the image of the conductor pattern 18b and the image of the pattern of the bump electrode 14, and then the same figure is used.
As shown in (c), the tool 111 is lowered from directly above the package substrate 1, and all the conductor patterns 18b and the bump electrodes 14 are thermocompression bonded at the same time.

Next, as shown in FIG. 18, the electrode pad 1
The semiconductor chip 2 having the bump electrodes 16 formed on 5 is attached to the bottom surface of the thermo-compression bonding tool 111 described above, and the bump electrodes 16 of the semiconductor chip 2 and the conductor pattern 18a of the insulating tape 17 corresponding thereto are overlapped. Both are joined together by thermocompression bonding. In order to accurately overlap the bump electrode 16 and the conductor pattern 18a, the half mirror 112 and the image analysis device 113 described above are used.

Finally, the cap 3 is joined to the upper surface of the dam frame 20 of the package substrate 1 to complete the semiconductor integrated circuit device shown in FIG. FIG. 19 is a flowchart of the manufacturing process described above.

As described above, according to this embodiment, the bump electrode 1 for connecting the package substrate 1 and the semiconductor chip 2 to each other.
By forming a capacitance (C) between the capacitors 4 and 16 and controlling the capacitance component, the characteristic impedances of the bump electrodes 14 and 16 can be well matched. The electrical characteristics can be improved.

Further, according to this embodiment, the signal bump electrodes 14 (s), 16 (s) are surrounded by the GND bump electrodes 14 (GND), 16 (GND), so that the signal Since it is possible to reduce the crosstalk and noise of the signals flowing in the bump electrodes 14 (s) and 16 (s) for use, it is possible to further improve the electrical characteristics of the LSI package in which the ultra-high speed device is mounted.

Further, according to the present embodiment, the package substrate 1 and the semiconductor chip 2 are connected to the plurality of bump electrodes 14 and 16.
By connecting via bumps, the strain applied to the bump electrode portion due to the difference in thermal expansion coefficient between the package substrate 1, the semiconductor chip 2, the bump electrodes 14 and 16 and the insulating tape 17 is displaced between the bump electrodes 14 and 16. Since it can be absorbed and alleviated, the connection reliability of the bump electrode portion can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above embodiment, a plurality of bump electrodes 1
An insulating tape 17 is arranged between the insulating tape 17 and the conductor patterns 18a and 18 formed on both surfaces thereof.
The capacitance is formed by b and, for example, as shown in FIG.
The capacitive element 30 is arranged between the bump electrodes 14 and 16, and one electrode of the capacitive element 30 is used as the bump electrode 14 for the signal.
(S) and 16 (s), and connect the other electrode to GND
It may be connected between the bump electrodes 14 (GND) and 16 (GND).

Further, as in the above embodiment, the bump electrode 1
When the insulating tape 17 is arranged between the four and 16, another semiconductor element (for example, a capacitor) can be mounted on a part of the insulating tape 17.

In the above-mentioned embodiment, the case where the present invention is applied to the LSI package has been described, but the present invention can also be applied to the case where the semiconductor chip is face-down bonded to the printed wiring board.

[0062]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by forming a capacitance between a plurality of bump electrodes connecting the wiring substrate and the semiconductor chip and controlling the capacitance component, the characteristic impedance of the bump electrodes can be reduced. Can be matched well.

(2) According to the present invention, by enclosing the periphery of the signal bump electrode with the GND bump electrode, it is possible to reduce the crosstalk and noise of the signal flowing through the signal bump electrode. .

(3) According to the present invention, in addition to connecting the wiring substrate and the semiconductor chip by using the metal balls which are less likely to cause thermal fatigue damage than solder, a plurality of metal balls (bump electrodes) are used. By connecting the wiring board and the semiconductor chip by stacking them one by one, the reliability and life of the connection portion can be improved.

(4) According to the present invention, since metal balls are formed on the electrode pads of the semiconductor chip and the electrodes of the wiring board by the ball bonding method, expensive vapor deposition equipment such as the CCB method and complicated lift-off. No process is required, and the manufacturing cost of the semiconductor integrated circuit device can be reduced and the productivity can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of FIG. 1 in an enlarged manner.

FIG. 3 is a plan view of a semiconductor chip mounted on a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 4 is a main part plan view showing a package substrate of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a plan view of an upper surface side showing an insulating tape of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is a plan view of a lower surface side showing an insulating tape of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a graph showing a reflection coefficient when the bump electrode on the package substrate side and the bump electrode on the semiconductor chip side are directly connected.

FIG. 8 is a graph showing a reflection coefficient of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a perspective view of a semiconductor chip showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a perspective view of a semiconductor chip showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

11A to 11E are schematic views showing a method of connecting bump electrodes on electrode pads of a semiconductor chip in the order of steps.

FIG. 12 is a cross-sectional view of a package substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 13 is a cross-sectional view of a package substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 14 is a cross-sectional view of a package substrate showing a method for manufacturing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 15 is a cross-sectional view of a package substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 16 is a cross-sectional view of a package substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

17A to 17C are schematic views showing a method of mounting an insulating tape on a bump electrode of a package substrate in the order of steps.

FIG. 18 is a cross-sectional view of a package substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 19 is a flowchart showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the main parts of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

 1 Package Substrate 2 Semiconductor Chip 3 Cap 4 Wiring 5 Electrode 6 GND Wiring 7 Power Supply Wiring 8 Through Hole 9 Lead 10 Brazing Material 11 GND Metallization 12 Metal Base 13 Brazing Material 14 Bump Electrode 15 Electrode Pad 16 Bump Electrode 17 Insulating Tape 18a Conductor Pattern 18b Conductor pattern 19 Through hole 20 Dam frame 21 Brazing material 22 Metallizing 23 Brazing material 24 Capacitive element 25 LSI / wiring forming area 26 GND wiring 27 Anchor part 28 Au ball 30 Capacitive element 101 Capillary 102 Torch 103 Au wire 110 Tool 111 Tool 112 Half mirror 113 Image analysis device

Claims (10)

[Claims] 1. A semiconductor integrated circuit device in which a semiconductor chip is face-down bonded via a plurality of bump electrodes stacked on a main surface of a wiring board, wherein a capacitive element is arranged between the plurality of bump electrodes. A semiconductor integrated circuit device, wherein one electrode of the capacitance element is connected to a signal bump electrode and the other electrode is connected to a GND bump electrode. 2. The capacitive element is composed of an insulating tape arranged between the plurality of bump electrodes, and a pair of conductor patterns formed on both surfaces of the insulating tape. The semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 1, wherein a periphery of the signal bump electrode is surrounded by a plurality of the GND bump electrodes. 4. The semiconductor integrated circuit device according to claim 1, wherein a high-speed device that operates at a high frequency of GHz or higher is formed on the main surface of the semiconductor chip. 5. The semiconductor integrated circuit device according to claim 1, wherein the bump electrode is made of Au. 6. A method of manufacturing a semiconductor integrated circuit device according to claim 1, comprising the following steps (a) to (c). (a) A step of joining metal balls on the electrode pads of the semiconductor chip to form bump electrodes, (b) After joining the metal balls on the wiring and electrodes of the wiring board, the upper surface of the metal balls is flattened. A step of forming bump electrodes, (c) mounting a capacitive element on the bump electrodes formed on the wiring and electrodes of the wiring board, and then forming the semiconductor chip having the bump electrodes formed on the capacitive element. Mounted, one electrode of the capacitive element is connected to each signal bump electrode of the wiring board and the semiconductor chip, and the other electrode is connected to each GND bump electrode of the wiring board and the semiconductor chip. The process of connecting. 7. The metal ball is bonded to the electrode pad of the semiconductor chip, the wiring of the wiring board and the electrode pad by a ball bonding method using heating, ultrasonic waves or energy of both. A method of manufacturing a semiconductor integrated circuit device according to claim 6. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the metal balls are made of a malleable metal. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein a plurality of metal balls are bonded to at least one of the electrode pad of the semiconductor chip, the wiring and the electrode of the wiring board. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein an anchor portion having a sharp tip is formed on the metal ball.