JP3568534B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP3568534B2
JP3568534B2 JP51310596A JP51310596A JP3568534B2 JP 3568534 B2 JP3568534 B2 JP 3568534B2 JP 51310596 A JP51310596 A JP 51310596A JP 51310596 A JP51310596 A JP 51310596A JP 3568534 B2 JP3568534 B2 JP 3568534B2
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Japan
Prior art keywords
conductive layer
chip
tape
constant potential
semiconductor device
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Expired - Fee Related
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JP51310596A
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Japanese (ja)
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JP3568534B6 (en
Inventor
元大 諏訪
千代士 鎌田
裕之 高橋
岳 新井
雅彦 西馬
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Renesas Technology Corp
Hitachi Solutions Technology Ltd
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Renesas Technology Corp
Hitachi ULSI Systems Co Ltd
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Publication of JP3568534B2 publication Critical patent/JP3568534B2/en
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Description

技術分野
本発明は、半導体装置に関し、特に、絶縁層に導電層が形成されたテープ上に、半導体チップがフェースダウンボンディングされる半導体装置に適用して有効な技術に関する。
背景技術
最近、携帯電話、自動車電話等の移動体無線機器が広く普及してきており、これら移動体無線機器には高性能のMMIC（Monolithic Microwave Integrated Circuit）が組み込まれている。この種移動体無線機器はマイクロ波帯域の高周波領域で動作するので、これに使用されるICのチップ材料としては一般に広く使用されているシリコンに代わって、高速性能に優れているガリウム砒素（CaAs）が選ばれることが多い。
このようなICを組み立てるには、ICチップの表面に形成されている複数のパッド電極をリードフレームのような外部リードに電気的に接続する必要がある。通常のICにおいては、このような電気的な接続は、複数のパッド電極と対応したリードとの間に金線のようなワイヤをボンディングすることにより行われる。
しかし、MMICのように特にマイクロ波帯域で動作するICの場合は、パッド電極とリードをボンディングワイヤにより接続することは、半導体チップに対して不要な配線を引き回す結果になって、そのボンディングワイヤによって寄生インダクタンス、寄生容量を増加させる原因となる。このように、寄生インダクタンス、寄生容量が増加すると、マイクロ波帯域の高周波信号を伝送する場合、信号の損失が増加して高周波信号を正確に伝送しにくくなる。この傾向は外部リードに対しても同様なことが言える。また、そのような信号損失の増加は特に寄生インダクタンスに起因することが多い。従って、寄生インダクタンスの増加を極力抑える改善策が望まれている。
このため、ボンディングワイヤを不要にしたチップボンディング法として、フェースダウンボンディング法が提案されている。例えば特開平５−251505号公報には、そのようなフェースダウンボンディング法の一方法が開示されている。この公報には、誘電体フィルムからなる基材上に複数の金属配線を形成し、その誘電体フィルムに金属配線に通ずるビアホールを形成したエリアテープを外部リードとして用いて、ビアホールに半田のような金属ボールを挿入した後、この金属ボールにパッド電極が接触するようにICチップを位置決めし、続いてエリアテープ及びICチップを加圧、加熱して金属ボールを溶融させて、ICチップをエリアテープにフェースダウンボンディングする方法が記載されている。
同様にして、例えば、特開平４−99341号公報には、ボンディングワイヤを不要にしたフェースダウンボンディング法の他の方法が開示されている。この公報には、絶縁層を介して設けた第１のTAB（Tape Automated Bonding）リード及び第２のTABリードを有し、各リードの先端部に各々高さの異なるバンプを形成したTABテープを用いて、各バンプを介してICチップをTABテープにフェースダウンボンディングする方法が記載されている。
前記したような従来のフェースダウンボンディング法において、前者に開示されている技術では、半田のような金属ボールを溶融させてICチップをボンディングするので、金属の流れ防止手段が必要になると共に、金属配線が誘電体フィルムの一面側にしか形成されていないので、テープの利用率が低いという問題がある。
すなわち、溶融した金属が流れ出して隣接したもの同士で短絡するおそれがあるため、流れ防止層のような防止手段が必要になる。さらに、誘電体フィルムの一面側にのみ形成された金属配線を利用するので、適用されるICチップは比較的パッド電極の少ないものに制限されるようになる。さらにまた、本従来技術では、誘電体フィルムの一面側にのみ金属配線が形成されているので、高周波信号の伝送路としてよく用いられるマイクロクロストリップライン構造を形成できないため、定インピーダンス信号線路を形成できず、高周波特性に優れた半導体装置を得ることができない。
また、後者に開示されている技術では、絶縁層の両面側に各々第１のTABリード及び第２のTABリードを設けたTABテープを用いているが、バンプは各リードの先端部にしか形成されていないので、パッド電極がチップ周辺のみに形成されたICチップにしか適用できないという問題がある。
すなわち、チップ全面にパッド電極を形成したICチップに対しては、チップ周辺以外のパッド電極にボンディングすることが不可能なので、適用できなくなる。
本発明の目的は、バンプを溶融することなくフェースダウンボンディングを可能にすると共に、テープの利用率を向上して、チップ全面にパッド電極を形成したICチップに適用可能な半導体装置を提供することを目的とする。
ところで、情報通信の増大に伴って、１秒間に数ギガビットの割合で情報を伝送することができるシステムを一つのモジュールに組み込む技術の開発が進展している。このモジュールにおいては周波数が1GHzを越える高周波信号が使用される。このような高周波信号を伝送するためのシステムを組み込んだモジュール（以下、高周波信号用モジュールという。）においては、通常周波数の信号を伝送するためのシステムを組み込んだモジュールに使用されるボトムブレーズ方式又はガル・ウイング方式を採用することができない。なぜならば、これらの方式においては、信号伝送路に少なくとも500μｍ程度の段差が発生することにより信号の反射現象が起こるため、高周波信号用モジュールに使用した場合に信号伝達特性が許容できない程度まで低下してしまうからである。
そこで、例えば、日本国特許庁公開特許公報平６−216272号に示されているように、実装基板の一部に没設した窪みに半導体装置を収容するドロップイン方式が提案されている。しかし、このドロップイン方式においては、実装基板に窪みを形成する必要があるため、実装基板のコストが高くなってしまうという問題点がある。
これに対処するため、実装基板に半導体チップを直接実装することが考えられる。しかし、複数個の半導体チップを直接実装した場合には、そのうちの一つでも故障すると、実装基板全体を取り替えなくてはならないという問題点が発生する。
本発明の第２の目的は、伝送信号の反射現象を防止することができるとともに、リペア性を向上することができて高周波信号用モジュールに好適な半導体装置を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面から明らかになるであろう。
発明の開示
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記の通りである。
本発明の半導体装置は、絶縁層に導電層が形成されたテープ上に、半導体チップがフェースダウンボンディングされる半導体装置であって、前記テープは絶縁層の表面側及び裏面側に各々第１の導電層及び第２の導電層が形成されて、第２の導電層の一部が開口部から表面側に露出されており、前記半導体チップは表面に形成されている複数のパッド電極が、前記第１の導電層及び第２の導電層と導通して各々が同一高さとなるように平坦化されている複数位置のバンプを介して、各バンプが溶融されることなくフェースダウンボンディングされる。
この半導体装置によれば、半導体チップがテープにバンプを溶融することなくフェースダウンボンディングされるため、テープの利用率を向上して、全面にパッド電極を形成した半導体チップであってもTABテープ構造を適用することができる。
また、本発明は、半導体チップがテープにフェースダウンボンディングされた前記半導体装置が複数個配線基板に、配線基板の第１主面にそれぞれ形成された各実装面部に前記第２の導電層を機械的かつ電気的に接続されてそれぞれ実装されていることを特徴とする。
この構成によれば、半導体チップをフェースダウンボンディングされたテープが配線基板の第１主面に表面実装されていることにより、半導体チップと配線基板の第１主面との段差が極小に抑制されるため、信号反射現像が防止されて信号伝送特性が向上される。また、各半導体チップはテープを介して配線基板に表面実装されているため、配線基板から外したい半導体チップはテープと配線基板の各実装面部との接続部の解除によって他の半導体チップから独立して外すことができる。
【図面の簡単な説明】
図１は本発明の実施例１による半導体装置を示す上面図である。
図２は図１のＡ−Ａ断面図である。
図３は図１のＢ−Ｂ断面図である。
図４は図１のＣ−Ｃ断面図である。
図５は実施例１による半導体装置の製造方法の一工程を示す断面図である。
図６は実施例１による半導体装置の製造方法の他の工程を示す断面図である。
図７は実施例１による半導体装置の製造方法のその他の工程を示す断面図である。
図８は実施例１による半導体装置の製造方法のその他の工程を示す断面図である。
図９は実施例１による半導体装置の製造方法のその他の工程を示す断面図である。
図10は本発明の実施例２による半導体装置を示す断面図である。
図11は本発明の実施例３による半導体装置を示す断面図である。
図12は本発明の実施例４による半導体装置を示す正面断面図である。
図13はその平面断面図である。
図14は実施例４による半導体装置に使用されたチップ組立体を示しており、（Ａ）は一部省略平面図、（Ｂ）はＢ−Ｂ線に沿う正面断面図である。
図15は同じくチップ組立体を示しており、（Ａ）は底面図、（Ｂ）はＢ−Ｂ線に沿う側面断面図である。
図16はチップ組立体が実装された配線基板組立体の主要部を示しており、（Ａ）は平面図、（Ｂ）は正面断面図である。
図17は本発明の実施例５による半導体装置を示す正面断面図である。
図18はその平面断面図である。
発明を実施するための最良の形態
以下図面を参照して本発明の実施例を説明する。
本実施例の半導体装置は、特に図２から明らかなように、例えば、ポリイミド、ポリエステルからなる絶縁層１の表面側（図２において上側）に第１の導電層２が形成されると共に、その裏面側（図２において下側）に第２の導電層３が形成されてなるTABテープ（以下、単にテープと称する）４と、表面に複数のパッド電極５が形成された例えばGaAsからなるICチップ６とを備えており、ICチップ６は複数のパッド電極５が第１の導電層２及び第２の導電層３と導通する複数位置のバンプ７を介して、各バンプ７が溶融されることなく、テープ４上にフェースダウンボンディングされている。
テープ４の絶縁層１は厚さ約50μｍに形成され、この絶縁層１の表面側及び裏面側には各々例えばCr、Cu、Auが順次めっき法等によって付着された厚さ約数10μｍからなる、第１の導電層２及び第２の導電層３が形成されている。絶縁層１には部分的に開口部８が形成されていて、第２の導電層３の一部はその開口部８から表面側に露出されている。これによって、第１の導電層２及び第２の導電層３は共に表面側からバンプ７と導通可能に配置されている。開口部８の側面8aは約30゜乃至45゜の傾斜面となるように形成されている。
テープ４の第１の導電層２には、後述のような方法によって、例えば１段のAuバンプ7aが形成されている。一方、第２の導電層３には、開口部８を通じて同様な方法によって、例えば２段のAuバンプ7a、7bが形成されている。各Auバンプ7a、7bは、例えば高さ約60μｍ、直径約150μｍに形成されている。第１の導電層２よりも低い位置に形成されている第２の導電層３に対して、第１の導電層２よりも１段だけ多くAuバンプ7bを形成することにより、かつ後述のような平坦化処理を施すことにより、第１の導電層２及び第２の導電層３上のAuバンプ７の高さは同一となるように図られている。
図１に示すように、テープ４の第１の導電層２上には例えばインダクタ９、10、あるいは容量素子11のような受動素子が形成される。一方、ICチップ６には能動素子が形成されると共に、例えばインダクタ12のような比較的小さい定数の受動素子を形成することができる。また、第１の導電層２に対しては、必要な電源、信号、バイアス調整用配線等を形成する。このように、ICチップ６に形成する受動素子の一部をテープ４に形成することにより、高価なICチップ６のチップ面積を大きくする必要がなくなるので、コストダウンを図ることができるようになる。
一方、テープ４の第２の導電層３はグランド電位として使用され、外部からこの第２の導電層３と導通するグランド用リード13を図１のように接続する。図３は図１のＢ−Ｂ断面図を示すもので、グランド用リード13が開口部８を通じて第２の導電層３と導通する構造を示している。
また、図４は図１のＣ−Ｃ断面図を示すもので、一例として容量素子11の一部構造を示しており、絶縁層１を挟んで配置されている一対の導電層２、３によって容量素子11を構成する例を示している。
テープ４及びICチップ６を含む主要部は樹脂14によって封止される。この樹脂封止は周知のトランスファモールド法によって行われる。なお、図１では説明を理解し易くするため、樹脂14を取り除いた構造で示している。
このような半導体装置によれば、マイクロ波帯域の高周波領域で動作する狭帯域増幅器を構成することができ、入力信号はマイクロストリップライン構造を有するテープ４の第１の導電層２を経てICチップ６に入力され、能動素子あるいは受動素子を経た後、再びテープ４上の受動素子に戻り、以上のような経路を繰り返して出力信号となる。信号がこのようにテープ４とICチップ６間を往復しても、ICチップ６がテープ４上にフェースダウンボンディングされていることにより、ワイヤボンディングを行う場合に比較して、寄生インダクタンスの増加は抑えられるので、信号損失の増加はほとんど抑えることができる。
次の本実施例の半導体装置の製造方法を工程順に説明する。
まず、図５に示すように、例えばポリイミド、ポリエステルからなる絶縁層１の表面側及び裏面側に各々第１の導電層２及び第２の導電層３を形成したテープを用意する。このテープ４は、厚さ約50μｍの絶縁層１を用いて、この絶縁層１の表面側及び裏面側に各々例えばCr、Cu、Auを順次めっき法等によって付着することにより、厚さ約数10μｍからなる第１の導電層２及び第２の導電層３を形成する。
また、絶縁層１には部分的に開口部８を形成し、第２の導電層３の一部をその開口部８から表面側に露出させる。開口部８の側面8aは約30゜乃至45゜の傾斜面となるように形成する。そして、第１の導電層２及び第２の導電層３に対して、直径約30μｍのAu線を用いたボールボンディング法を行って、例えば１段のAuバンプ7aを、例えば高さ約60μｍ、直径約150μｍに形成する。この結果、第１の導電層２上のAuバンプ7aと、第２の導電層３上のAuバンプ7bとには高さに差が生じる。
次に、図６に示すように、第２の導電層３上のAuバンプ7aに対してのみ、前記と同様なボールボンディングを行って、さらに１段のAuバンプ7bをAuバンプ7aと同じサイズに形成する。これによって、第１の導電層２上のAuバンプ7aと、第２の導電層３上のAuバンプ7a、7bとの高さの差を10μｍ程度まで小さくすることができる。
続いて、図７に示すように、第１の導電層２上のAuバンプ7a及び第２の導電層３上のAuバンプ7a、7bを上から治具15を用いて押圧することにより、平坦化処理する。各Auバンプ7a、7b、7cは柔らかい性質を有しているので、治具15による押圧によって容易に変形することにより、完全に平坦化される。これによって、テープ４の異なる複数位置に形成されたAuバンプ7aとAuバンプ7a、7bとの高さの差は吸収されて、完全に同一高さとなる。このようなAuバンプの平坦化処理は、本出願人が先に出願した特開平５−275491号公報に記載されるような方法を採用することにより、容易に行うことができる。
次に、図８に示すように、表面に複数のパッド電極５が形成され、必要に応じて能動素子のみならず受動素子を形成した例えばGaAsからなるICチップ６を用意して、各パッド電極５上に前記のようなボールボンディング法を行って、例えば１段のAuバンプ7cを、例えば高さ約60μｍ、直径約150μｍに形成する。
続いて、図９に示すように、図７において得られたテープ４上に、図８において得られたICチップ６をこのパッド電極５が下方となるように配置し、各パッド電極５上のAuバンプ7cと対応するAuバンプ7a及びAuバンプ7a、7bとを位置決めした状態で、熱圧着法によってICチップ６をテープ４上にフェースダウンボンディングする。この熱圧着法はAuバンプの融点以下の温度で行うことにより、各Auバンプ7a、7b、7cを溶融することなく、フェースダウンボンディングを行う。次に、これらテープ４及びICチップ６をトランスファモールド法によって樹脂封止する。これによって、図２に示したように主要部が樹脂14により封止された半導体装置が得られる。
このような実施例１による半導体装置によれば、次のような効果が得られる。
（１）テープ４上にICチップ６をフェースダウンボンディングする場合、Auバンプ7a、7b、7cを溶融することなく行うことができるので、隣接したAuバンプ同士の短絡のおそれはないため、Auバンプの流れ防止手段は不要になる。
（２）これに伴い、絶縁層１の一面側だけでなく表面側及び裏面側に各々第１の導電層２及び第２の導電層３を形成して、各導電層２、３をICチップ６のパッド電極５と導通させる外部リードとして利用することができるので、テープ４の利用率が向上する。これによって、比較的パッド電極の多いICチップに対してもTABテープ構造が適用可能となる。
（３）絶縁層１の表面側及び裏面側に各々第１の導電層２及び第２の導電層３を形成したテープ４を用いることができるので、チップ全面にパッド電極を形成したICチップ６に対しても適用可能となる。
（４）（１）乃至（３）によって、寄生インダクタンスの増加を抑えられるというフェースダウンボンディングの利点をそのまま生かすことができるので、特にマイクロ波帯域の高周波領域で動作する半導体装置の信号損失の増加を小さく抑えることができる。
（５）ICチップ６に形成される受動素子の一部をテープ４に形成できるので、高価なICチップ６のチップ面積を小さくできるため、コストダウンを図ることができる。
図10は本発明の実施例２による半導体装置を示す断面図である。本実施例の半導体装置は、実施例１による半導体装置において、テープ４の第２の導電層３の底面を樹脂14から露出させて、この第２の導電層３に厚さ数mmの金属板16を取り付けた構造を有している。この金属板16としては、例えばFe−Ni、Mo、Cu−Ｗ等が用いられて、Au−Su等のろう材を介して第２の導電層３に接続される。
このように、第２の導電層３の厚さ（数10μｍ）に比較して板厚の大きな金属板16を第２の導電層３に取り付けることにより、結果的にこの第２の導電層３の寄生インダクタンスを小さくすることができる。これにより、第２の導電層３をグランド電位として使用する場合に、グランド電位を安定化することができる。これは、IC単体で動作させる場合でも、あるいはこのICをシステム装置に組み込んだ場合でも、効果的となる。
このような半導体装置は、予めテープ４の第２の導電層３に金属板16を取り付けた後、ICチップ６をテープ４上にフェースダウンボンディングし、続いて金属板16を除いた部分を樹脂封止することにより、製造することができる。
このような実施例２による半導体装置によれば、実施例１による半導体装置と同様な効果が得られる他に、次のような効果が得られる。
グランド電位として使用されるテープ４の第２の導電層３に板厚の大きい金属板16を取り付けるようにしたので、寄生インダクタンスを小さくできるため、グランド電位を安定化させることができる。
図11は本発明の実施例３による半導体装置を示す断面図である。本実施例の半導体装置は、ICチップ６の裏面に金属板16を取付け、この金属板16に放熱フィン17を取り付けた構造を有している。この放熱フィン17としては、例えばCu−Ｗ、Al、Fe−Ni等の熱放散性に優れた金属材料が用いられて、熱伝導性グリース等の接着剤を介して、あるいはねじ止めにより、または両者の組み合わせによって金属板16に取り付けられる。
このように、金属板16に放熱フィン17を取り付けることにより、冷却効率を高めることができる。これにより、半導体装置を特に大電力用途に用いる場合でも、効率の良い動作を行わせることができるようになる。
このような半導体装置は、ICチップ６をテープ４上にフェースダウンボンディングした後、ICチップ６の裏面にAuめっきした金属板16を取り付け、次に金属板16の裏面を除いた部分を樹脂封止し、続いて金属板16の裏面に放熱フィン17を取り付けることにより、製造することができる。
このような実施例３による半導体装置によれば、実施例１及び実施例２による半導体装置と同様な効果が得られる他に、次のような効果が得られる。
ICチップ６の裏面に金属板16を介して放熱フィン17を取り付けるようにしたので、冷却効率を高めることができるため、大電力用途に用いる場合に効率の良い動作を行わせることができる。
以上、本発明によってなされた発明を、前記実施例に基づき具体的に説明したが、本発明は、前記実施例に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
例えば、テープ４の第１の導電層２及び第２の導電層３に形成するAuバンプ7a、7b、7cの段数は一例を示したものであり、この段数は任意に選ぶことができる。但し、第１の導電層２及び第２の導電層３に形成するAuバンプの高さは、ほぼ同一高さとなるように選ぶ必要がある。
同様にして、Auバンプのサイズも任意に設定することができる。このAuバンプのサイズは使用するAu線の直径によってほぼ決定される。
また、テープ４上にフェースダウンボンディングするICチップ６の数は、１個に限らず、複数個用いることも可能である。
さらに、ICチップ６のパッド電極５に形成するAuバンプは、必ずしも用いる必要はなく、テープ４側に形成する複数のAuバンプによって代用させることも可能である。
以上の説明では主として本発明者によってなされた発明をその背景となった利用分野である半導体装置の技術に適用した場合について説明したが、それに限定されるものではない。本発明は、少なくともマイクロ波帯域の高周波領域で動作させる半導体装置において、寄生インダクタンスの増加を抑えて信号損失の増加を抑える条件のものには適用できる。
次に、図12〜図16に示されている本発明の実施例４による半導体装置を説明する。
本実施例４において、本発明に係る半導体装置は、機能的には高周波信号を分周するものとして構成され、パッケージング的にはマルチ・チップ・モジュール（multi−chip module。以下、MCMという。）として構成されている。このMCM20は前記実施例１と同様にテープ４にICチップ６がフェースダウンボンディングされたチップとテープとの組立体（以下、チップ組立体という。）21と、チップ組立体21を複数個実装するための配線パターンが形成された配線基板22と、チップ組立体21群及び配線基板22を気密封止するための気密封止体41とを備えている。このMCM20にはチップ組立体21が複数個（図示例では４個）使用されており、各チップ組立体21は前記実施例１、かつ、互いに同一又は異なる機能を発揮するように受動素子及び能動素子がそれぞれ組み込まれている。但し、便宜上、受動素子及び能動素子の図示は省略されている。
チップ組立体21に使用されたテープ４における絶縁層１の表面側には第１の導電層２が形成され、絶縁層１の裏面側には第２の導電層３が形成されている。絶縁層１には開口部８がテープ４の中央部に１個、それを取り囲む周辺部に複数個がそれぞれ開設されており、これら開口部８の側面8aは表面側に行くにしたがって内径が大きくなるように傾斜されている。第２の導電層３はテープ４の裏面の略全体にわたって形成されており、第２の導電層３の表面側の一部は各開口部８の底においてそれぞれ露出した状態になっている。第２の導電層３は単一の定電位電極3aと複数本のリード3bとを備えている。定電位電極3aは絶縁層１の裏面の中央部に大きな長方形に敷設されており、中央部に開設された開口部８の底面を構成する位置には複数段のAuバンプ7a、7bがワイヤボンディング法によって突設されている。各外部リード3bは絶縁層１の裏面における周辺部において周方向に略等間隔に配されて径方向外向きに突出するように敷設されている。
他方、第１の導電層２は幅の広い電源線2aと、幅の狭い（例えば、約90μｍ）高速信号線2bとを備えている。各電源線2a及び各高速信号線2bは中央部の開口部８を中心にして放射状にパターニングされている。各電源線2a及び各高速信号線2bの内側端部はICチップ６の各パッド電極５に対応するように配線されており、これらの各パッド電極５にそれぞれ対向した位置には単段のAuバンプ7aがそれぞれワイヤボンディング法によって突設されている。
各電源線2aは絶縁層１の表面において一方の対辺のそれぞれを結ぶ方向（以下、左右方向とする。）に延在するように放射状に敷設されており、周辺部に開設された開口部８において第２の導電層３における各外部リード3bにそれぞれ電気的に接続されている。電源線2aは第２の導電層３における定電位電極3aと絶縁層１を挟んで対向した状態になることよってビルトイン構造の容量素子11を実体的に構成しており、この容量素子11によって電源線2aは電源電位を安定化されている。各高速信号線2bは絶縁層１の表面において左右方向及び他方の対辺のそれぞれを結ぶ方向（以下、前後方向とする。）に延在するように放射状に敷設されており、周辺部に開設された開口部８において第２の導電層３における各外部リード3bに電気的に接続されている。高速信号線2bは第２の導電層３における定電位電極3aと絶縁層１を挟んで対向した状態になることによってマイクロストリップライン構造を構成している。
他方、ICチップ６はGaAsが使用されて長方形の平板形状に形成されている。ICチップ６には高周波信号を分周するための能動素子が作り込まれているとともに、能動素子の動作に必要で、しかも、ICチップ６に合理的にレイアウトすることができる受動素子が作り込まれている。ICチップ６の能動素子が作り込まれた側の主面（以下、第１主面という。）にはパッド電極５が複数個形成されており、各パッド電極５はテープ４側の各Auバンプ7a及び7a、7bにそれぞれ対応するように配置されている。ちなみに、各パッド電極には単段のAuバンプ7aが形成される。
そして、前記構成に係るテープ４とICチップ６とは、定電位電極3a、各電源線2a及び各高速信号線2bと各パッド電極５との間にAuバンプ７をそれぞれ形成されることにより、フェースダウンボンディングされて、機械的かつ電気的に接続された状態になっている。
なお、テープ４の製造方法及びフェースダウンボンディング方法は前記実施例１において説明した製造方法及びボンディング方法に同様であるため、その説明は省略する。
配線基板22はガラス含浸エポキシ樹脂の板材が使用されて長方形の板形状に形成された絶縁板23を備えており、絶縁板23の第１主面には各チップ組立体21を実装するための実装面部24が複数箇所（本実施例では、４箇所）に形成されている。各実装面部24は基板側定電位電極25及び複数個のランド26をそれぞれ備えており、基板側定電位電極25はチップ組立体21の定電位電極3aに対応され、各ランド26はチップ組立体21の外部リード3bにそれぞれ対応されている。各ランド26には絶縁板23に配された電気配線27によって、配線基板22の外周辺部に配置された複数個の外部端子28にそれぞれ電気的に接続されている。この配線基板22において、各電気配線27は多層配線構造に構成されている。絶縁板23の内部には内部定電位電極29が多層配線構造の各電気配線27との短絡を回避する状態で、全面にわたって敷設されている。内部定電位電極29は各実装面部24の基板側定電位電極25にスルーホール導体30によって電気的に接続されている。絶縁板23の第２主面にはグランド電極31が全面にわたって敷設されており、グランド電極31はスルーホール導体32によって内部定電位電極29に電気的に接続されている。
なお、以上の構成に係る配線基板22の製造方法は、一般的な配線基板の製造方法に準ずるため、その説明は省略する。
そして、前記構成に係るチップ組立体21は前記構成に係る配線基板22の各実装面部24にリフロー半田付け方法によって表面実装される。すなわち、チップ組立体21の定電位電極3a及び各外部リード3b又は配線基板22の基板側定電位電極25及び各ランド26の少なくとも一方には、半田クリーム等の予備半田材（図示せず）が予め塗布される。各チップ組立体21が実装面部24に予備半田材によって接着された状態で、配線基板22が加熱炉を通されることにより予備半田材が溶融かつ固化されて形成された半田層33によって、各チップ組立体21は各実装面部24に機械的かつ電気的に接続される。以上のようにして、チップ組立体21が配線基板22に表面実装された配線基板組立体34が製造されたことになる。
気密封止体41は互いに腹合わせに配されて合わせ面において接合されたベース42とキャップ43とを備えており、ベース42内の底面上に配線基板組立体34がグランド電極31を接触されて固定されている。配線基板組立体34が気密封止体41によって気密封止された状態において、配線基板22の外部端子28は気密封止体41のコネクタ44によって外部に電気的に引き出された状態になっており、また、グランド電極31は気密封止体41に電気的接続された状態になっている。
さらに、気密封止体41の外面には放熱フィン45が接合されており、この放熱フィン45によって配線基板組立体34の発熱が効率的に外部に放出されるようになっている。
次に、以上のように構成されているMCM20の作用を説明する。
MCM20が通信機器のマザーボード（図示せず）等に実装された状態で、駆動電力は配線基板22の外部端子28、電気配線27、ランド26、各チップ組立体21の外部リード3b、電源線2a、バンプ７を通じて各ICチップ６に供給される。また、入力信号は配線基板22の外部端子28、電気配線27、ランド26、各チップ組立体21の外部リード3b、高速信号線2b、バンプ７を通じて各ICチップ６に入力される。ICチップ６からの出力信号はバンプ７、高速信号線2b、各チップ組立体21の外部リード3b、配線基板22のランド26、電気配線27、外部端子28を通じて外部の需要部に出力される。この作動中、高速信号線2bは第２の導電層３における定電位電極3aと絶縁層１を挟んで対向した状態になることによってマイクロストリップライン構造を構成しているため、きわめて高い高周波信号が伝送される場合であってもきわめて優れた高速伝送特性を示すことになる。また、電源線2aが第２の導電層３における定電位電極3aと絶縁層１を挟んで対向した状態になることよってビルトイン構造の容量素子11を実体的に構成しているとともに、定電位電極3aが配線基板22の基板側定電位電極25、内部定電位電極29、グランド電極31を介して気密封止体41にグランドされているため、電源線2aはきわめて安定した電源電位を維持した状態になっている。その結果、このMCM20はきわめて優れた高周波特性を示すことになる。
なお、中央部のパッド電極５が中央部の開口部８に配設されたAuバンプ７によって定電位電極3aに電気的に接続されているため、ICチップ６のグランド電位は安定を維持した状態になっている。
前記実施例４によれば次の効果が得られる。
（１） テープ４の裏面に形成された第２の導電層３に定電位電極3aを形成することにより、テープ４の表面に形成された第１の導電層２による高速信号線2bをマイクロストリップライン構造に構成することができるため、信号伝送特性を高めることができ、きわめて高い高周波信号の伝送を実現することができる。
（２） テープ４の裏面に形成された第２の導電層３に定電位電極3aを形成することにより、テープ４の表面に形成された第１の導電層２による電源線2aとの間でビルトイン容量素子11を構成することができるため、電源電位を安定化することができ、前記（１）とあいまって、高周波特性に優れたMCM20を得ることができる。
（３） 前記（２）の定電位電極3aを配線基板22の基板側定電位電極25、内部定電位電極29及びグランド電極31を介して気密封止体41にグランドすることにより、電源電位をより一層安定化させることができるため、MCM20の高周波特性をより一層高めることができる。
（４） 前記（３）の基板側定電位電極25をグランド電極31にスルーホール導体30、32によって内部定電位電極29を介して電気的に接続することにより、長い配線を引き回さずに基板側定電位電極25とグランド電極31とを接続することができるため、電源電位をより一層安定させることができる。
（５） ICチップ６を配線基板22に厚さが約50μｍのテープ４を介して実装することにより、配線基板22とICチップ６との段差をきわめて小さく抑制することができるため、高速信号が伝送される際のインピーダンスの低下を抑制することができ、高速信号線2bのインピーダンスマッチングを容易に確保することができる。
（６） ICチップ６を配線基板22にチップ組立体21の状態で表面実装することにより、配線基板22に窪みを形成しないとも済むため、配線基板22の製造コストしいてはMCM20の製造コストを低減することができる。
（７） ICチップ６を配線基板22にチップ組立体21の状態で表面実装するとともに、テープ４の絶縁層１をポリイミド樹脂等の柔軟性を有する絶縁材を使用して形成することにより、ICチップ６と配線基板22の絶縁板23との熱膨張係数を整合させなくて済むため、GaAsとSiといった熱膨張係数の異なるICチップ６を同一の配線基板22に実装することができ、より一層多機能のMCM20を構成することができ、しいては、より一層高度なシステムを同一のパッケージにパッケージングすることができる。
（８） 前記（７）により、ICチップ６と配線基板22との熱膨張係数をも整合させなくて済むため、ガラス含浸エポキシ樹脂等のICチップ６と熱膨張係数が大きく異なる材料を配線基板22に使用することができ、MCM20の製造コストをより一層低減することができる。
（９） チップ組立体21を配線基板22に半田層33によって表面実装することにより、MCM20に実装されたICチップ６群のうちいずれかに故障が発見された場合に、故障したICチップ６のチップ組立体21だけを容易に交換することができるため、MCM20の製造歩留りや、MCM20のメンテナンス性能及び寿命を向上させることができる。
（10） 前記（４）のスルーホール導体30、32を基板側定電位電極25及び内部定電位電極29の真下に配置することにより、熱伝導度の良好な導体を一直線に並ばせることができるため、MCM20の放熱性能を向上させることができる。
（11） テープ４の絶縁層１における開口部８の側面8aがバンプ７の形成される側が広くなる傾斜面に形成されているため、バンプ７の形成時に第１の導電層２の剥離を防止することができる。
以上本発明者によってなされた発明を実施例に基づき具体的に説明したが、本発明は前記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
例えば、配線基板22の基板側定電位電極25を内部定電位電極29に電気的に接続するスルーホール導体30は、基板側定電位電極25の真下に配置するに限らず、図17及び図18に示されているように、基板側定電位電極25をスルーホール導体30を形成可能な場所まで引き回して、その場所においてスルーホール導体30を形成して内部定電位電極29に接続してもよい。この接続構造によれば、配線基板22において基板側定電位電極25の真下にスルーホール導体30を形成することができない場合であっても、基板側定電位電極25を内部定電位電極29に電気的に接続することができるため、チップ組立体21の定電位電極3aによって電源線2aの電位を安定させることができるとともに、高速信号線2bのマイクロストリップライン構造の信号伝送を安定させることができる。ちなみに、基板側定電位電極25を引き回すことによって第２の導電層３の電位安定性は、基板側定電位電極25の真下にスルーホール導体30が配置された場合に比べて若干低下するが、基板側定電位電極25が敷設されない場合に比べては遙かに向上させることができる。
配線基板組立体34に対する封止構造としては、気密封止構造を採用するに限らず、樹脂封止構造を採用してもよいし、配線基板組立体34をマザーボード等に直接的に実装した後に、他の部品とともに気密封止や樹脂封止、さらには、液密封止する構造としてもよい。
前記実施例においては、通信機器に使用される半導体装置について説明したが、本発明はこれに限らず、スーパーコンピュータ等の高速処理が要求される半導体装置全般に適用することができる。
産業上の利用可能性
以上のように、本発明に係る半導体装置は、MMIC及びMCMとして構成することができ、携帯電話や自動車電話等の移動体無線機器、マルチメディヤ等の情報通信システムにおける高周波信号の処理装置として有用であり、特に、周波数が1GHzを越える高周波信号の伝送処理に用いるのに適している。Technical field
The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in which a semiconductor chip is face-down bonded onto a tape having an insulating layer formed with a conductive layer.
Background art
Recently, mobile wireless devices such as mobile phones and automobile phones have become widespread, and high performance MMIC (Monolithic Microwave Integrated Circuit) is incorporated in these mobile wireless devices. Since this type of mobile radio equipment operates in the high frequency region of the microwave band, gallium arsenide (CaAs), which has excellent high-speed performance, replaces silicon, which is widely used as a chip material for ICs used in this type of mobile radio equipment. ) Is often chosen.
In order to assemble such an IC, it is necessary to electrically connect a plurality of pad electrodes formed on the surface of the IC chip to an external lead such as a lead frame. In a normal IC, such electrical connection is performed by bonding a wire such as a gold wire between a plurality of pad electrodes and corresponding leads.
However, in the case of an IC that operates particularly in the microwave band, such as an MMIC, connecting the pad electrode and the lead with a bonding wire results in unnecessary wiring being routed to the semiconductor chip. This causes an increase in parasitic inductance and parasitic capacitance. As described above, when the parasitic inductance and the parasitic capacitance increase, when transmitting a high frequency signal in the microwave band, the loss of the signal increases and it becomes difficult to accurately transmit the high frequency signal. The same is true for external leads. In addition, such an increase in signal loss is often caused by parasitic inductance. Therefore, an improvement measure that suppresses the increase in parasitic inductance as much as possible is desired.
For this reason, a face-down bonding method has been proposed as a chip bonding method that eliminates the need for bonding wires. For example, Japanese Patent Laid-Open No. 5-251505 discloses a method of such a face-down bonding method. In this publication, an area tape in which a plurality of metal wirings are formed on a base material made of a dielectric film and via holes communicating with the metal wirings are formed on the dielectric film as external leads, and solder is used for the via holes. After the metal ball is inserted, the IC chip is positioned so that the pad electrode is in contact with the metal ball, and then the area tape and IC chip are pressurized and heated to melt the metal ball, and the IC chip is moved to the area tape. Describes a method of face-down bonding.
Similarly, for example, Japanese Patent Laid-Open No. 4-99341 discloses another method of face-down bonding that eliminates the need for bonding wires. In this publication, a TAB tape having a first TAB (Tape Automated Bonding) lead and a second TAB lead provided via an insulating layer and having bumps with different heights formed at the tips of the leads is provided. And a method for face-down bonding of an IC chip to a TAB tape through each bump is described.
In the conventional face-down bonding method as described above, in the technique disclosed in the former method, a metal ball such as solder is melted to bond the IC chip. Since the wiring is formed only on one side of the dielectric film, there is a problem that the utilization rate of the tape is low.
That is, there is a possibility that the molten metal flows out and short-circuits between adjacent ones, so that a prevention means such as a flow prevention layer is required. Further, since the metal wiring formed only on one surface side of the dielectric film is used, the applied IC chip is limited to one having relatively few pad electrodes. Furthermore, in this prior art, since a metal wiring is formed only on one side of the dielectric film, a micro-cross trip line structure often used as a transmission path for high-frequency signals cannot be formed, so a constant impedance signal line is formed. It is not possible to obtain a semiconductor device having excellent high frequency characteristics.
In the technique disclosed in the latter, a TAB tape having a first TAB lead and a second TAB lead on each side of the insulating layer is used, but the bump is formed only at the tip of each lead. Therefore, there is a problem that it can be applied only to an IC chip in which pad electrodes are formed only around the chip.
In other words, it cannot be applied to an IC chip in which pad electrodes are formed on the entire surface of the chip because bonding to pad electrodes other than the periphery of the chip is impossible.
An object of the present invention is to provide a semiconductor device that can be applied to an IC chip in which pad electrodes are formed on the entire surface of the chip by enabling face-down bonding without melting bumps and improving the tape utilization rate. With the goal.
By the way, with the increase in information communication, development of a technology for incorporating a system capable of transmitting information at a rate of several gigabits per second into one module is progressing. In this module, a high frequency signal having a frequency exceeding 1 GHz is used. In a module incorporating a system for transmitting such a high-frequency signal (hereinafter, referred to as a high-frequency signal module), a bottom blaze method used for a module incorporating a system for transmitting a normal frequency signal or The gull wing method cannot be adopted. This is because in these systems, a signal reflection phenomenon occurs due to a step of at least about 500 μm in the signal transmission path, so that the signal transmission characteristics are lowered to an unacceptable level when used in a high frequency signal module. Because it will end up.
In view of this, for example, as disclosed in Japanese Patent Application Publication No. Hei 6-216272, a drop-in method has been proposed in which a semiconductor device is accommodated in a recess submerged in a part of a mounting substrate. However, in this drop-in method, since it is necessary to form a recess in the mounting substrate, there is a problem that the cost of the mounting substrate is increased.
In order to cope with this, it is conceivable to directly mount the semiconductor chip on the mounting substrate. However, when a plurality of semiconductor chips are directly mounted, there is a problem that if one of them fails, the entire mounting board must be replaced.
A second object of the present invention is to provide a semiconductor device suitable for a high-frequency signal module that can prevent a reflection phenomenon of a transmission signal and improve repairability.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Disclosure of the invention
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
The semiconductor device of the present invention is a semiconductor device in which a semiconductor chip is face-down bonded onto a tape having a conductive layer formed on an insulating layer, and the tape is first on the front side and the back side of the insulating layer. A conductive layer and a second conductive layer are formed, a part of the second conductive layer is exposed to the surface side from the opening, and the semiconductor chip has a plurality of pad electrodes formed on the surface, The bumps are face-down bonded without being melted through the bumps at a plurality of positions which are conductively connected to the first conductive layer and the second conductive layer and are flattened so as to have the same height.
According to this semiconductor device, since the semiconductor chip is face-down bonded without melting the bumps on the tape, the tape utilization rate is improved, and even a semiconductor chip having pad electrodes formed on the entire surface has a TAB tape structure. Can be applied.
According to the present invention, the second conductive layer is mechanically attached to each mounting surface portion formed on the first main surface of the wiring board, and a plurality of the semiconductor devices in which the semiconductor chip is face-down bonded to the tape. It is characterized by being mounted by being connected electrically and electrically.
According to this configuration, the tape on which the semiconductor chip is face-down bonded is surface-mounted on the first main surface of the wiring board, so that the step between the semiconductor chip and the first main surface of the wiring board is minimized. Therefore, signal reflection development is prevented and signal transmission characteristics are improved. Since each semiconductor chip is surface-mounted on the wiring board via a tape, the semiconductor chip to be removed from the wiring board becomes independent from the other semiconductor chips by releasing the connection between the tape and each mounting surface of the wiring board. Can be removed.
[Brief description of the drawings]
FIG. 1 is a top view showing a semiconductor device according to Embodiment 1 of the present invention.
2 is a cross-sectional view taken along the line AA in FIG.
3 is a cross-sectional view taken along the line BB of FIG.
4 is a cross-sectional view taken along the line CC of FIG.
FIG. 5 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment.
6 is a cross-sectional view showing another step of the method of manufacturing the semiconductor device according to the first embodiment.
FIG. 7 is a cross-sectional view showing another process of the method of manufacturing a semiconductor device according to the first embodiment.
FIG. 8 is a cross-sectional view showing another process of the method of manufacturing a semiconductor device according to the first embodiment.
FIG. 9 is a cross-sectional view showing another process of the method of manufacturing a semiconductor device according to the first embodiment.
FIG. 10 is a sectional view showing a semiconductor device according to Embodiment 2 of the present invention.
FIG. 11 is a sectional view showing a semiconductor device according to Embodiment 3 of the present invention.
FIG. 12 is a front sectional view showing a semiconductor device according to Embodiment 4 of the present invention.
FIG. 13 is a plan sectional view thereof.
14A and 14B show a chip assembly used in a semiconductor device according to Example 4, wherein FIG. 14A is a partially omitted plan view, and FIG. 14B is a front sectional view taken along line BB.
FIG. 15 also shows the chip assembly, in which (A) is a bottom view and (B) is a side sectional view taken along line BB.
FIG. 16 shows a main part of the wiring board assembly on which the chip assembly is mounted, in which (A) is a plan view and (B) is a front sectional view.
FIG. 17 is a front sectional view showing a semiconductor device according to Embodiment 5 of the present invention.
FIG. 18 is a plan sectional view thereof.
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
As clearly shown in FIG. 2, the semiconductor device of the present embodiment has a first conductive layer 2 formed on the surface side (upper side in FIG. 2) of the insulating layer 1 made of, for example, polyimide or polyester. A TAB tape (hereinafter simply referred to as a tape) 4 having a second conductive layer 3 formed on the back side (lower side in FIG. 2) and an IC made of, for example, GaAs having a plurality of pad electrodes 5 formed on the surface. Each of the bumps 7 is melted via a plurality of bumps 7 where the plurality of pad electrodes 5 are electrically connected to the first conductive layer 2 and the second conductive layer 3. Without being face-bonded on the tape 4.
The insulating layer 1 of the tape 4 is formed to have a thickness of about 50 μm, and the insulating layer 1 has a thickness of about several tens of μm, for example, Cr, Cu, and Au are sequentially deposited on the front side and the back side by plating or the like. The first conductive layer 2 and the second conductive layer 3 are formed. An opening 8 is partially formed in the insulating layer 1, and a part of the second conductive layer 3 is exposed to the surface side from the opening 8. Thus, both the first conductive layer 2 and the second conductive layer 3 are disposed so as to be conductive with the bump 7 from the surface side. The side surface 8a of the opening 8 is formed to be an inclined surface of about 30 ° to 45 °.
On the first conductive layer 2 of the tape 4, for example, a one-step Au bump 7 a is formed by a method as described later. On the other hand, for example, two-stage Au bumps 7a and 7b are formed on the second conductive layer 3 through the opening 8 by the same method. Each Au bump 7a, 7b is formed with a height of about 60 μm and a diameter of about 150 μm, for example. By forming Au bumps 7b one step higher than the first conductive layer 2 with respect to the second conductive layer 3 formed at a position lower than the first conductive layer 2, and as will be described later By performing the flattening process, the heights of the Au bumps 7 on the first conductive layer 2 and the second conductive layer 3 are made the same.
As shown in FIG. 1, passive elements such as inductors 9 and 10 or a capacitive element 11 are formed on the first conductive layer 2 of the tape 4. On the other hand, an active element is formed on the IC chip 6 and a relatively small constant passive element such as an inductor 12 can be formed. For the first conductive layer 2, necessary power supply, signal, bias adjustment wiring, and the like are formed. Thus, by forming part of the passive elements formed on the IC chip 6 on the tape 4, it is not necessary to increase the chip area of the expensive IC chip 6, so that the cost can be reduced. .
On the other hand, the second conductive layer 3 of the tape 4 is used as a ground potential, and a ground lead 13 that is electrically connected to the second conductive layer 3 from the outside is connected as shown in FIG. FIG. 3 is a cross-sectional view taken along the line BB in FIG. 1 and shows a structure in which the ground lead 13 is electrically connected to the second conductive layer 3 through the opening 8.
FIG. 4 is a cross-sectional view taken along the line C-C in FIG. 1. As an example, FIG. 4 shows a partial structure of the capacitive element 11. The example which comprises the capacitive element 11 is shown.
The main part including the tape 4 and the IC chip 6 is sealed with a resin 14. This resin sealing is performed by a well-known transfer mold method. In FIG. 1, the structure is shown with the resin 14 removed for easy understanding of the description.
According to such a semiconductor device, a narrow band amplifier that operates in a high frequency region of the microwave band can be configured, and an input signal passes through the first conductive layer 2 of the tape 4 having a micro strip line structure, and the IC chip. 6 and after passing through an active element or a passive element, it returns to the passive element on the tape 4 again and repeats the above path to become an output signal. Even if the signal reciprocates between the tape 4 and the IC chip 6 in this way, the parasitic inductance increases as compared with the case where wire bonding is performed because the IC chip 6 is face-down bonded on the tape 4. Therefore, an increase in signal loss can be suppressed almost.
Next, a method for manufacturing a semiconductor device according to the present embodiment will be described in the order of steps.
First, as shown in FIG. 5, a tape is prepared in which a first conductive layer 2 and a second conductive layer 3 are formed on the front side and the back side of an insulating layer 1 made of, for example, polyimide or polyester. This tape 4 uses an insulating layer 1 having a thickness of about 50 μm, and deposits, for example, Cr, Cu, Au on the front side and the back side of the insulating layer 1 in sequence by a plating method or the like. A first conductive layer 2 and a second conductive layer 3 of 10 μm are formed.
An opening 8 is partially formed in the insulating layer 1 and a part of the second conductive layer 3 is exposed from the opening 8 to the surface side. The side surface 8a of the opening 8 is formed to be an inclined surface of about 30 ° to 45 °. Then, a ball bonding method using an Au wire having a diameter of about 30 μm is performed on the first conductive layer 2 and the second conductive layer 3, for example, to form a single Au bump 7 a having a height of about 60 μm, for example. A diameter of about 150 μm is formed. As a result, there is a difference in height between the Au bump 7a on the first conductive layer 2 and the Au bump 7b on the second conductive layer 3.
Next, as shown in FIG. 6, only the Au bump 7a on the second conductive layer 3 is subjected to the same ball bonding as described above, and the one-step Au bump 7b is the same size as the Au bump 7a. To form. As a result, the height difference between the Au bumps 7a on the first conductive layer 2 and the Au bumps 7a and 7b on the second conductive layer 3 can be reduced to about 10 μm.
Subsequently, as shown in FIG. 7, the Au bumps 7a on the first conductive layer 2 and the Au bumps 7a and 7b on the second conductive layer 3 are pressed by using a jig 15 from above to flatten them. Process. Since each Au bump 7a, 7b, 7c has a soft property, it is completely flattened by being easily deformed by pressing with the jig 15. As a result, the difference in height between the Au bumps 7a and the Au bumps 7a and 7b formed at different positions on the tape 4 is absorbed and becomes completely the same height. Such planarization of the Au bump can be easily performed by adopting a method as described in Japanese Patent Laid-Open No. 5-275491 filed earlier by the present applicant.
Next, as shown in FIG. 8, a plurality of pad electrodes 5 are formed on the surface, and an IC chip 6 made of, for example, GaAs having not only active elements but also passive elements as necessary is prepared. The above-described ball bonding method is performed on 5 to form, for example, one stage of Au bump 7c having a height of about 60 μm and a diameter of about 150 μm, for example.
Subsequently, as shown in FIG. 9, the IC chip 6 obtained in FIG. 8 is arranged on the tape 4 obtained in FIG. 7 so that the pad electrode 5 is on the lower side. With the Au bump 7c and the corresponding Au bump 7a and the Au bumps 7a and 7b positioned, the IC chip 6 is face-down bonded on the tape 4 by a thermocompression bonding method. This thermocompression bonding method is performed at a temperature lower than the melting point of the Au bump, thereby performing face-down bonding without melting each Au bump 7a, 7b, 7c. Next, the tape 4 and the IC chip 6 are resin-sealed by a transfer mold method. As a result, a semiconductor device in which the main part is sealed with the resin 14 as shown in FIG. 2 is obtained.
According to the semiconductor device according to the first embodiment, the following effects can be obtained.
(1) When the IC chip 6 is face-down bonded on the tape 4, since the Au bumps 7a, 7b, 7c can be performed without melting, there is no possibility of short-circuiting between adjacent Au bumps. No flow prevention means is required.
(2) Along with this, the first conductive layer 2 and the second conductive layer 3 are formed not only on one surface side of the insulating layer 1 but also on the front surface side and the back surface side, and the respective conductive layers 2 and 3 are connected to the IC chip. 6 can be used as an external lead to be electrically connected to the pad electrode 5 of 6, so that the utilization rate of the tape 4 is improved. As a result, the TAB tape structure can be applied to an IC chip having a relatively large number of pad electrodes.
(3) Since the tape 4 in which the first conductive layer 2 and the second conductive layer 3 are respectively formed on the front surface side and the back surface side of the insulating layer 1 can be used, the IC chip 6 in which pad electrodes are formed on the entire surface of the chip. It becomes applicable to.
(4) Since (1) to (3) can take advantage of the face-down bonding that an increase in parasitic inductance can be suppressed as it is, an increase in signal loss particularly in a semiconductor device operating in a high frequency region of the microwave band. Can be kept small.
(5) Since some of the passive elements formed on the IC chip 6 can be formed on the tape 4, the chip area of the expensive IC chip 6 can be reduced, so that the cost can be reduced.
FIG. 10 is a sectional view showing a semiconductor device according to Embodiment 2 of the present invention. The semiconductor device of this example is the same as the semiconductor device of Example 1, except that the bottom surface of the second conductive layer 3 of the tape 4 is exposed from the resin 14, and a metal plate having a thickness of several millimeters is formed on the second conductive layer 3. It has a structure with 16 attached. For example, Fe—Ni, Mo, Cu—W or the like is used as the metal plate 16 and is connected to the second conductive layer 3 via a brazing material such as Au—Su.
Thus, by attaching the metal plate 16 having a plate thickness larger than the thickness (several tens of μm) of the second conductive layer 3 to the second conductive layer 3, the second conductive layer 3 is consequently obtained. The parasitic inductance can be reduced. As a result, the ground potential can be stabilized when the second conductive layer 3 is used as the ground potential. This is effective even when the IC is operated alone or when this IC is incorporated in a system device.
In such a semiconductor device, a metal plate 16 is attached to the second conductive layer 3 of the tape 4 in advance, and then the IC chip 6 is face-down bonded on the tape 4 and the portion excluding the metal plate 16 is then resin-bonded. It can be manufactured by sealing.
According to the semiconductor device according to the second embodiment, in addition to the same effects as the semiconductor device according to the first embodiment, the following effects can be obtained.
Since the metal plate 16 having a large plate thickness is attached to the second conductive layer 3 of the tape 4 used as the ground potential, the parasitic inductance can be reduced, so that the ground potential can be stabilized.
FIG. 11 is a sectional view showing a semiconductor device according to Embodiment 3 of the present invention. The semiconductor device of the present embodiment has a structure in which a metal plate 16 is attached to the back surface of the IC chip 6 and heat radiating fins 17 are attached to the metal plate 16. As the heat dissipating fins 17, for example, a metal material having excellent heat dissipation such as Cu-W, Al, Fe-Ni is used, through an adhesive such as heat conductive grease, or by screwing, or It is attached to the metal plate 16 by a combination of both.
Thus, by attaching the radiation fins 17 to the metal plate 16, the cooling efficiency can be increased. As a result, even when the semiconductor device is used for a particularly high power application, an efficient operation can be performed.
In such a semiconductor device, after the IC chip 6 is face-down bonded on the tape 4, a metal plate 16 plated with Au is attached to the back surface of the IC chip 6, and then the portion excluding the back surface of the metal plate 16 is sealed with resin. It can be manufactured by stopping and subsequently attaching the radiation fins 17 to the back surface of the metal plate 16.
According to the semiconductor device according to the third embodiment, in addition to the same effects as the semiconductor devices according to the first and second embodiments, the following effects can be obtained.
Since the heat dissipating fins 17 are attached to the back surface of the IC chip 6 via the metal plate 16, the cooling efficiency can be increased, so that an efficient operation can be performed when used for high power applications.
Although the invention made by the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Of course.
For example, the number of stages of Au bumps 7a, 7b, 7c formed on the first conductive layer 2 and the second conductive layer 3 of the tape 4 is shown as an example, and the number of stages can be arbitrarily selected. However, the height of the Au bumps formed on the first conductive layer 2 and the second conductive layer 3 needs to be selected so as to be substantially the same.
Similarly, the size of the Au bump can be arbitrarily set. The size of the Au bump is almost determined by the diameter of the Au wire used.
Further, the number of IC chips 6 to be face-down bonded on the tape 4 is not limited to one, and a plurality of IC chips 6 may be used.
Further, the Au bump formed on the pad electrode 5 of the IC chip 6 is not necessarily used, and a plurality of Au bumps formed on the tape 4 side can be substituted.
In the above description, the case where the invention made mainly by the present inventor is applied to the technology of a semiconductor device which is a field of use as the background has been described. However, the present invention is not limited to this. The present invention can be applied to a semiconductor device that operates in at least a high frequency region of a microwave band and has a condition that suppresses an increase in parasitic inductance and suppresses an increase in signal loss.
Next, a semiconductor device according to a fourth embodiment of the present invention shown in FIGS. 12 to 16 will be described.
In the fourth embodiment, the semiconductor device according to the present invention is functionally configured to divide a high-frequency signal and is packaged as a multi-chip module (hereinafter referred to as MCM). ). As in the first embodiment, the MCM 20 has a chip-tape assembly (hereinafter referred to as a chip assembly) 21 in which an IC chip 6 is face-down bonded to a tape 4 and a plurality of chip assemblies 21 are mounted. A wiring board 22 on which a wiring pattern for forming the wiring pattern is formed, and a hermetic sealing body 41 for hermetically sealing the chip assembly 21 group and the wiring board 22 are provided. The MCM 20 includes a plurality of chip assemblies 21 (four in the illustrated example), and each chip assembly 21 has a passive element and an active element so as to perform the same or different functions as those of the first embodiment. Each element is incorporated. However, for the sake of convenience, illustration of passive elements and active elements is omitted.
A first conductive layer 2 is formed on the front surface side of the insulating layer 1 in the tape 4 used in the chip assembly 21, and a second conductive layer 3 is formed on the back surface side of the insulating layer 1. The insulating layer 1 has one opening 8 at the center of the tape 4 and a plurality of openings 8 surrounding the periphery of the tape 4, and the side surface 8a of the opening 8 increases in diameter toward the surface side. It is inclined to become. The second conductive layer 3 is formed over substantially the entire back surface of the tape 4, and a part of the surface side of the second conductive layer 3 is exposed at the bottom of each opening 8. The second conductive layer 3 includes a single constant potential electrode 3a and a plurality of leads 3b. The constant potential electrode 3a is laid in a large rectangle at the center of the back surface of the insulating layer 1, and a plurality of stages of Au bumps 7a and 7b are wire-bonded at the position constituting the bottom surface of the opening 8 formed in the center. Protruded by law. The external leads 3b are laid out at the peripheral portion on the back surface of the insulating layer 1 so as to protrude radially outwardly at substantially equal intervals in the circumferential direction.
On the other hand, the first conductive layer 2 includes a wide power supply line 2a and a narrow (for example, about 90 μm) high-speed signal line 2b. Each power supply line 2a and each high-speed signal line 2b are radially patterned around the central opening 8. The inner ends of each power supply line 2a and each high-speed signal line 2b are wired so as to correspond to each pad electrode 5 of the IC chip 6, and a single stage Au is provided at a position facing each pad electrode 5 respectively. Each bump 7a is projected by a wire bonding method.
Each power line 2a is laid radially so as to extend in the direction connecting the opposite sides (hereinafter referred to as the left-right direction) on the surface of the insulating layer 1, and an opening 8 formed in the peripheral portion. Are electrically connected to the external leads 3b in the second conductive layer 3, respectively. The power source line 2a is in a state of being opposed to the constant potential electrode 3a in the second conductive layer 3 with the insulating layer 1 interposed therebetween, so that a built-in capacitive element 11 is practically formed. The line 2a has a stabilized power supply potential. Each high-speed signal line 2b is laid radially on the surface of the insulating layer 1 so as to extend in the left-right direction and the direction connecting the other opposite sides (hereinafter referred to as the front-rear direction), and is opened in the periphery. The opening 8 is electrically connected to each external lead 3b in the second conductive layer 3. The high-speed signal line 2b forms a microstrip line structure by facing the constant potential electrode 3a in the second conductive layer 3 across the insulating layer 1 therebetween.
On the other hand, the IC chip 6 is formed in a rectangular flat plate shape using GaAs. The IC chip 6 has an active element for dividing a high-frequency signal, and a passive element that is necessary for the operation of the active element and can be rationally laid out on the IC chip 6. It is rare. A plurality of pad electrodes 5 are formed on the main surface of the IC chip 6 on the side where the active elements are formed (hereinafter referred to as the first main surface), and each pad electrode 5 corresponds to each Au bump on the tape 4 side. They are arranged so as to correspond to 7a, 7a and 7b, respectively. Incidentally, a single-stage Au bump 7a is formed on each pad electrode.
The tape 4 and the IC chip 6 according to the above configuration are formed by forming Au bumps 7 between the constant potential electrodes 3a, the power supply lines 2a, the high-speed signal lines 2b, and the pad electrodes 5, respectively. It is face-down bonded and mechanically and electrically connected.
Since the manufacturing method and the face-down bonding method of the tape 4 are the same as the manufacturing method and the bonding method described in the first embodiment, description thereof is omitted.
The wiring board 22 is provided with an insulating plate 23 made of a glass-impregnated epoxy resin plate and formed into a rectangular plate shape. The first main surface of the insulating plate 23 is used for mounting each chip assembly 21. The mounting surface portion 24 is formed at a plurality of locations (4 locations in the present embodiment). Each mounting surface portion 24 includes a substrate-side constant potential electrode 25 and a plurality of lands 26. The substrate-side constant potential electrode 25 corresponds to the constant potential electrode 3a of the chip assembly 21, and each land 26 corresponds to the chip assembly. Each corresponds to 21 external leads 3b. Each land 26 is electrically connected to a plurality of external terminals 28 disposed on the outer peripheral portion of the wiring board 22 by electric wiring 27 disposed on the insulating plate 23. In the wiring board 22, each electric wiring 27 is configured in a multilayer wiring structure. Inside the insulating plate 23, an internal constant potential electrode 29 is laid over the entire surface in a state in which a short circuit with each electric wiring 27 of the multilayer wiring structure is avoided. The internal constant potential electrode 29 is electrically connected to the substrate side constant potential electrode 25 of each mounting surface portion 24 by a through-hole conductor 30. A ground electrode 31 is laid over the entire second main surface of the insulating plate 23, and the ground electrode 31 is electrically connected to the internal constant potential electrode 29 by a through-hole conductor 32.
Note that the manufacturing method of the wiring board 22 according to the above configuration is based on a general manufacturing method of a wiring board, and therefore, the description thereof is omitted.
The chip assembly 21 according to the above configuration is surface-mounted by the reflow soldering method on each mounting surface portion 24 of the wiring board 22 according to the above configuration. That is, a spare solder material (not shown) such as solder cream is applied to at least one of the constant potential electrode 3a and each external lead 3b of the chip assembly 21 or the substrate side constant potential electrode 25 and each land 26 of the wiring board 22. It is applied in advance. With each chip assembly 21 bonded to the mounting surface portion 24 with a preliminary solder material, each solder layer 33 is formed by melting and solidifying the preliminary solder material by passing the wiring board 22 through a heating furnace. The chip assembly 21 is mechanically and electrically connected to each mounting surface portion 24. As described above, the wiring board assembly 34 in which the chip assembly 21 is surface-mounted on the wiring board 22 is manufactured.
The hermetic sealing body 41 includes a base 42 and a cap 43 which are arranged on the mating surfaces and joined to each other on the mating surface. The wiring board assembly 34 is brought into contact with the ground electrode 31 on the bottom surface in the base 42. It is fixed. In the state where the wiring board assembly 34 is hermetically sealed by the hermetic sealing body 41, the external terminals 28 of the wiring board 22 are in a state of being electrically drawn out by the connector 44 of the hermetic sealing body 41. The ground electrode 31 is electrically connected to the hermetic seal 41.
Furthermore, heat radiating fins 45 are joined to the outer surface of the hermetic sealing body 41, and the heat radiating fins 45 efficiently release the heat generated by the wiring board assembly 34 to the outside.
Next, the operation of the MCM 20 configured as described above will be described.
In the state where the MCM 20 is mounted on a motherboard (not shown) of a communication device, the driving power is the external terminal 28 of the wiring board 22, the electrical wiring 27, the land 26, the external lead 3b of each chip assembly 21, and the power line 2a. , And supplied to each IC chip 6 through the bumps 7. The input signal is input to each IC chip 6 through the external terminal 28 of the wiring board 22, the electric wiring 27, the land 26, the external lead 3 b of each chip assembly 21, the high-speed signal line 2 b, and the bump 7. An output signal from the IC chip 6 is output to an external demand section through the bump 7, the high-speed signal line 2 b, the external lead 3 b of each chip assembly 21, the land 26 of the wiring board 22, the electric wiring 27, and the external terminal 28. During this operation, the high-speed signal line 2b is in a state of being opposed to the constant potential electrode 3a in the second conductive layer 3 with the insulating layer 1 interposed therebetween, thereby forming a microstrip line structure. Even when it is transmitted, it exhibits extremely excellent high-speed transmission characteristics. In addition, the power source line 2a is opposed to the constant potential electrode 3a in the second conductive layer 3 with the insulating layer 1 interposed therebetween, so that the built-in capacitive element 11 is substantially configured, and the constant potential electrode Since 3a is grounded to the hermetic sealing body 41 via the substrate-side constant potential electrode 25, the internal constant potential electrode 29, and the ground electrode 31 of the wiring board 22, the power supply line 2a maintains a very stable power supply potential. It has become. As a result, this MCM20 exhibits extremely high frequency characteristics.
The center pad electrode 5 is electrically connected to the constant potential electrode 3a by the Au bump 7 disposed in the center opening 8. Therefore, the ground potential of the IC chip 6 is maintained in a stable state. It has become.
According to the fourth embodiment, the following effects can be obtained.
(1) By forming a constant potential electrode 3a on the second conductive layer 3 formed on the back surface of the tape 4, the high-speed signal line 2b formed by the first conductive layer 2 formed on the surface of the tape 4 is microstriped. Since it can be configured in a line structure, signal transmission characteristics can be improved, and extremely high frequency signal transmission can be realized.
(2) By forming the constant potential electrode 3a on the second conductive layer 3 formed on the back surface of the tape 4, between the power line 2a formed by the first conductive layer 2 formed on the surface of the tape 4 Since the built-in capacitive element 11 can be configured, the power supply potential can be stabilized, and in combination with (1), the MCM 20 having excellent high frequency characteristics can be obtained.
(3) By grounding the constant potential electrode 3a of (2) to the hermetic sealing body 41 via the substrate side constant potential electrode 25, the internal constant potential electrode 29, and the ground electrode 31 of the wiring board 22, the power supply potential is reduced. Since it can be further stabilized, the high frequency characteristics of the MCM 20 can be further enhanced.
(4) By electrically connecting the substrate-side constant potential electrode 25 of the above (3) to the ground electrode 31 through the internal constant potential electrode 29 by the through-hole conductors 30 and 32, a long wiring is not routed. Since the substrate-side constant potential electrode 25 and the ground electrode 31 can be connected, the power supply potential can be further stabilized.
(5) Since the IC chip 6 is mounted on the wiring board 22 via the tape 4 having a thickness of about 50 μm, the step between the wiring board 22 and the IC chip 6 can be suppressed to a very small level. A decrease in impedance during transmission can be suppressed, and impedance matching of the high-speed signal line 2b can be easily ensured.
(6) Since the IC chip 6 is surface-mounted on the wiring board 22 in the state of the chip assembly 21, it is not necessary to form a recess in the wiring board 22. Therefore, the manufacturing cost of the wiring board 22 can be reduced to the manufacturing cost of the MCM 20. Can be reduced.
(7) The IC chip 6 is surface-mounted on the wiring board 22 in the state of the chip assembly 21, and the insulating layer 1 of the tape 4 is formed by using a flexible insulating material such as polyimide resin, whereby the IC Since it is not necessary to match the thermal expansion coefficients of the chip 6 and the insulating plate 23 of the wiring board 22, IC chips 6 having different thermal expansion coefficients such as GaAs and Si can be mounted on the same wiring board 22. A multi-function MCM 20 can be configured, and more sophisticated systems can be packaged in the same package.
(8) Since it is not necessary to match the thermal expansion coefficients of the IC chip 6 and the wiring board 22 according to the above (7), the wiring board is made of a material that differs greatly in thermal expansion coefficient from the IC chip 6 such as glass impregnated epoxy resin. The manufacturing cost of the MCM 20 can be further reduced.
(9) By mounting the chip assembly 21 on the wiring board 22 with the solder layer 33, when a failure is found in any of the IC chip groups 6 mounted on the MCM 20, the failure of the failed IC chip 6 Since only the chip assembly 21 can be easily replaced, the production yield of the MCM 20 and the maintenance performance and life of the MCM 20 can be improved.
(10) By arranging the through-hole conductors 30 and 32 of (4) directly below the substrate-side constant potential electrode 25 and the internal constant potential electrode 29, conductors having good thermal conductivity can be arranged in a straight line. Therefore, the heat dissipation performance of MCM20 can be improved.
(11) Since the side surface 8a of the opening 8 in the insulating layer 1 of the tape 4 is formed on an inclined surface where the side on which the bump 7 is formed is widened, peeling of the first conductive layer 2 is prevented when the bump 7 is formed. can do.
The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor.
For example, the through-hole conductor 30 that electrically connects the substrate-side constant potential electrode 25 of the wiring board 22 to the internal constant-potential electrode 29 is not limited to being disposed directly below the substrate-side constant potential electrode 25, and is not limited to FIGS. As shown in FIG. 4, the substrate-side constant potential electrode 25 may be routed to a place where the through-hole conductor 30 can be formed, and the through-hole conductor 30 may be formed at that location and connected to the internal constant-potential electrode 29. . According to this connection structure, even if the through-hole conductor 30 cannot be formed immediately below the substrate-side constant potential electrode 25 in the wiring board 22, the substrate-side constant potential electrode 25 is electrically connected to the internal constant potential electrode 29. Therefore, the potential of the power supply line 2a can be stabilized by the constant potential electrode 3a of the chip assembly 21, and the signal transmission of the microstrip line structure of the high-speed signal line 2b can be stabilized. . Incidentally, the potential stability of the second conductive layer 3 is slightly reduced by routing the substrate-side constant potential electrode 25 as compared with the case where the through-hole conductor 30 is disposed directly below the substrate-side constant potential electrode 25. Compared with the case where the substrate-side constant potential electrode 25 is not laid, this can be improved significantly.
The sealing structure for the wiring board assembly 34 is not limited to adopting an airtight sealing structure, but may be a resin sealing structure, or after the wiring board assembly 34 is directly mounted on a motherboard or the like. Further, it may have a structure that is hermetically sealed, resin-sealed, and liquid-tightly sealed together with other components.
In the above-described embodiments, the semiconductor device used in the communication device has been described. However, the present invention is not limited to this, and can be applied to all semiconductor devices that require high-speed processing such as a supercomputer.
Industrial applicability
As described above, the semiconductor device according to the present invention can be configured as an MMIC and an MCM, and is useful as a high-frequency signal processing device in mobile radio equipment such as mobile phones and automobile phones, and information communication systems such as multimedia. In particular, it is suitable for use in high-frequency signal transmission processing with a frequency exceeding 1 GHz.

Claims (3)

絶縁層に導電層が形成されたテープ上に半導体チップがフェースダウンボンディングされているチ ップ組立体であって、前記テープは絶縁層の表面側及び裏面側に各々第１の導電層及び第２の導電層が形成されて、第２の導電層の一部が開口部から表面側に露出されており、前記半導体チップは表面に形成されている複数のパッド電極が、前記第１の導電層及び第２の導電層と導通して各々が同一高さとなるように平坦化されている複数位置のバンプを介して、各バンプが溶融されることなくフェースダウンボンディングされているチップ組立 体が複数個、配線基板の第１主面にそれぞれ形成された 各実装面部に前記第２の導電層を機械的かつ電気的に接 続されてそれぞれ実装されており、
前記実装面部にはグランド電極に電気的に接続された基 板側定電位電極がそれぞれ形成されており、これら基板 側定電位電極には前記第２の導電層の中央部にそれぞれ 形成された各チップ側定電位電極が電気的に接続されて いることを特徴とする半導体装置。 A Chi-up assembly semiconductors chips on a tape having a conductive layer formed in the insulating layer is face-down bonding, the tape is first conductive layer and each first surface and the second surface of the insulating layer A second conductive layer is formed, a part of the second conductive layer is exposed to the surface side from the opening, and a plurality of pad electrodes formed on the surface of the semiconductor chip include the first conductive layer each conduction with the conductive layer and the second conductive layer through the bump of the plurality positions is planarized to the same height, the chip assembly the bumps are face-down bonding without being melted There plurality are respectively mounted to be mechanically and electrically connect the second conductive layers to each mounting face respectively formed on the first main surface of the wiring board,
Wherein the mounting surface is electrically connected to base plate side constant electric potential electrode to the ground electrode is formed respectively, each to these substrate side constant potential electrodes respectively formed in a central portion of the second conductive layer A semiconductor device, wherein the chip-side constant potential electrodes are electrically connected . 前記基板側定電位電極は前記配線基板の内The substrate side constant potential electrode is formed on the wiring substrate. 部に形成された内部定電位電極を経由して前記グランドThe ground via the internal constant potential electrode formed in the part 電極に電気的に接続されていることを特徴とする請求のAn electrical connection to the electrode 範囲第１項記載の半導体装置。2. A semiconductor device according to claim 1. 絶縁板の第１主面に形成された複数の実装A plurality of mountings formed on the first main surface of the insulating plate 面部にグランド電極に電気的に接続された基板側定電位Substrate-side constant potential electrically connected to the ground electrode on the surface 電極がそれぞれ形成されている配線基板が準備される配A wiring board on which electrodes are formed is prepared. 線基板準備工程と、Wire board preparation process;
絶縁層に導電層が形成されたテープ上に半導体チップがA semiconductor chip is placed on a tape with a conductive layer formed on the insulating layer. フェースダウンボンディングされているチップ組立体でWith a chip assembly that is face-down bonded あって、前記テープは絶縁層の表面側及び裏面側に各々And the tape is respectively on the front side and the back side of the insulating layer. 第１の導電層及び第２の導電層が形成されて、第２の導A first conductive layer and a second conductive layer are formed to form a second conductive layer. 電層の一部が開口部から表面側に露出されており、前記A part of the electric layer is exposed to the surface side from the opening, 半導体チップは表面に形成されている複数のパッド電極The semiconductor chip has a plurality of pad electrodes formed on the surface が、前記第１の導電層及び第２の導電層と導通して各々Are electrically connected to the first conductive layer and the second conductive layer, respectively. が同一高さとなるように平坦化されている複数位置のバThe multi-position bar is flattened so that the ンプを介して、各バンプが溶融されることなくフェースThe bumps are faced without melting each bump ダウンボンディングされているチップ組立体が複数個、Multiple chip assemblies that are down bonded, 前記配線基板の各実装面部に前記第２の導電層を機械的The second conductive layer is mechanically disposed on each mounting surface portion of the wiring board. かつ電気的に接続されてそれぞれ実装され、前記基板側And are electrically connected and mounted on the board side. 定電位電極には前記第２の導電層の中央部にそれぞれ形The constant potential electrode has a shape at the center of the second conductive layer. 成された各チップ側定電位電極が電気的に接続される接Each chip-side constant potential electrode formed is electrically connected. 続工程と、A follow-up process,
を備えていることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
JP1996513105A 1994-10-18 1995-10-17 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3568534B6 (en)

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