KR100583491B1 - Semiconductor package and its manufacturing method - Google Patents

Semiconductor package and its manufacturing method Download PDF

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KR100583491B1
KR100583491B1 KR1020000018291A KR20000018291A KR100583491B1 KR 100583491 B1 KR100583491 B1 KR 100583491B1 KR 1020000018291 A KR1020000018291 A KR 1020000018291A KR 20000018291 A KR20000018291 A KR 20000018291A KR 100583491 B1 KR100583491 B1 KR 100583491B1
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semiconductor chip
upper surface
semiconductor package
method
means
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KR20010094894A (en
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양준영
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앰코 테크놀로지 코리아 주식회사
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract

이 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 최소의 부품으로 칩싸이즈화가 가능하고, 또한 방열 성능이 우수한 동시에 적층된 구조를 구현할 수 있는 반도체패키지 및 그 제조 방법을 제공하기 위해, 상면에 다수의 입출력패드가 형성된 제1반도체칩과; This invention relates to a semiconductor package and a manufacturing method thereof, Chip customer specification mad possible with a minimum of parts, and also to provide a semiconductor package and a manufacturing method for implementing a laminated structure excellent in heat radiation performance at the same time, a large number on the upper surface a first semiconductor chip of the input-output pads formed and; 상면에 다수의 입출력패드가 형성되어 있으며, 상기 제1반도체칩의 상면에 그 제1반도체칩의 크기보다 작은 크기로서 접착수단에 의해 접착된 제2반도체칩과; And a plurality of input-output pads on the upper surface is formed on the upper surface of the first semiconductor chip first semiconductor bonded by the adhesive it means as a smaller size than the size of the chip and the second semiconductor chip on the; 상기 제1반도체칩 및 제2반도체칩의 입출력패드에 일단이 본딩되고, 타단이 상부를 향해 연장된 신호인출수단과; Wherein the first and one end is bonded to the input and output pads of the semiconductor chip and second semiconductor chip, and the other end is a signal take-off means extending toward the upper and; 상기 신호인출수단의 타단이 상부로 노출되도록 하는 동시에, 상기 제1반도체칩 및 제2반도체칩의 상면을 봉지하는 봉지재를 포함하여 이루어진 것을 특징으로 함. At the same time to be exposed to the upper other end of the signal take-off means, and also characterized by comprising an encapsulation material for sealing the upper surface of the first semiconductor chip and second semiconductor chip.

Description

반도체패키지 및 그 제조 방법{Semiconductor package and its manufacturing method} A semiconductor package and its manufacturing method {Semiconductor package and its manufacturing method}

도1a 내지 도1e는 본 발명에 의한 신호인출수단으로서 도전성와이어를 이용하는 반도체패키지의 단면도이다. Figure 1a to Figure 1e is a cross-sectional view of the semiconductor package using a conductive wire as a signal take-off means according to the present invention.

도2는 도1a 내지 도1e에 도시된 반도체패키지의 통상적인 사시도이다. Figure 2 is a perspective view of a conventional semiconductor package shown in FIG. 1a to 1e.

도3a 내지 도3c는 본 발명에 의한 신호인출수단으로서 도전성와이어 및 도전성볼을 이용한 반도체패키지를 도시한 단면도이다. Figures 3a-3c is a cross-sectional view showing a semiconductor package using a conductive wire and the conductive ball as a signal take-off means according to the present invention.

도4a 내지 도4c는 본 발명에 의한 신호인출수단으로서 도전성 범프를 이용한 반도체패키지를 도시한 단면도이다. Figures 4a to 4c is a sectional view showing a semiconductor package using a conductive bump as a signal take-off means according to the present invention.

도5a 내지 도5d는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 설명도이다. Figures 5a through 5d is an explanatory view showing a method of manufacturing a semiconductor package according to the present invention.

- 도면중 주요 부호에 대한 설명 - - description of the main reference characters -

101~111; 101-111; 본 발명에 의한 반도체패키지 The semiconductor package according to the invention

2; 2; 제1반도체칩 4,8; 4,8 the first semiconductor chip; 입출력패드 O pads

6; 6; 제2반도체칩 10; A second semiconductor chip 10; 도전성와이어 Conductive wires

10a; 10a; 노출면 10b,10d; Exposed surfaces 10b, 10d; 단부 Ends

10c; 10c; 돌출부 12; Protrusions 12; 봉지재 Encapsulant

14; 14; 도전성볼 16; A conductive ball 16; 도전성 범프 Conductive bumps

18; 18; 단부 w; End w; 웨이퍼 wafer

본 발명은 반도체패키지 및 그 제조 방법에 관한 것으로, 더욱 상세하게 설명하면 최소의 부품으로 칩싸이즈화가 가능하고, 또한 방열 성능이 우수한 동시에 적층된 구조를 구현할 수 있는 반도체패키지 및 그 제조 방법에 관한 것이다. The present invention relates to that, more In more detail a semiconductor package with a minimum of components chip customer specification mad possible, and can also implement a multilayer structure excellent in heat radiation performance at the same time and a method of manufacturing a semiconductor package and a method of manufacturing the same .

최근에는 패키지 어셈블링 기술의 발달로 인해 점차 반도체패키지의 크기가 반도체칩의 크기에 근접하고 있다. Recently, with the development of the package assembling technology it is increasingly close to the size of the semiconductor package size of the semiconductor chip. 또한, 반도체패키지의 기능을 최대한 높이기 위해 다수의 반도체칩을 하나의 반도체패키지내에서 적층한 구조도 개시되고 있다. Further, it is also disclosed a structure laminating a plurality of semiconductor chips in order to increase as much as possible the capabilities of a semiconductor package in a single semiconductor package. 더불어, 최근의 반도체칩에 대한 집적도가 커지고 또한 그 동작 주파수가 높아짐에 따라 상기 반도체칩에서 발생하는 열을 적절히 처리할 수 있는 구조도 여러 가지로 개시되고 있다. In addition, the degree of integration of recent semiconductor chip increases have also been disclosed in a number of road structure that can properly handle the heat generated by the semiconductor chip according to the the operating frequency becomes higher.

그러나, 이러한 반도체패키지들은 그 반도체칩을 적층하거나 또는 방열성능을 향상시키기 위해 별도의 구성 부품(예를 들면, 다층의 인쇄회로기판 내지 방열판)이 더 부가되어 비용이 고가로 되는 문제점이 있다. However, such a semiconductor package are separate components, the problem (e.g., a multi-layer printed circuit board to the heat sink) is further added to the cost of high to improve the lamination or heat radiation performance of the semiconductor chip.

또한, 반도체칩을 적층한 상태에서는 칩싸이즈화된 반도체패키지의 구조를 얻기 힘들뿐만 아니라, 방열수단을 장착한 상태에서도 칩싸이즈화된 반도체패키지의 구조를 얻기 힘들다. Further, in the state in which the stacked semiconductor chips, it is difficult to obtain the structure of the chip to customer specification screen, as well as difficult to obtain a structure of the semiconductor package, chip customer specification, even when equipped with a heat sink means Chemistry semiconductor package.

더불어, 상기와 같이 반도체패키지가 칩싸이즈화되고, 반도체칩이 적층되고, 방열성능이 향상된 3가지 효과를 동시에 만족하는 반도체패키지는 아직 개시되지 않았다. In addition, the semiconductor package chip to customer specification and screen as described above, the semiconductor chips are stacked, the semiconductor package that meets the three effects the thermal performance improved at the same time has not been disclosed.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 발명한 것으로, 전체적인 크기는 칩싸이즈화되고, 적층된 반도체칩을 가지며 또한 방열성능이 향상된 반도체패키지 및 그 제조 방법을 제공하는데 있다. Therefore, the present invention is to provide a prior art that invention to address this issue, the overall size of the chip and the customer specification screen, has a stacked semiconductor chip is also improved heat radiation performance and a method of manufacturing a semiconductor package as described above.

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 상면에 다수의 입출력패드가 형성된 제1반도체칩과; A first semiconductor chip, a semiconductor package according to the invention to achieve the above object is formed of a plurality of input-output pads on the upper surface; 상면에 다수의 입출력패드가 형성되어 있으며, 상기 제1반도체칩의 상면에 그 제1반도체칩의 크기보다 작은 크기로서 접착수단에 의해 접착된 제2반도체칩과; And a plurality of input-output pads on the upper surface is formed on the upper surface of the first semiconductor chip first semiconductor bonded by the adhesive it means as a smaller size than the size of the chip and the second semiconductor chip on the; 상기 제1반도체칩 및 제2반도체칩의 입출력패드에 일단이 본딩되고, 타단이 상부를 향해 연장된 신호인출수단과; Wherein the first and one end is bonded to the input and output pads of the semiconductor chip and second semiconductor chip, and the other end is a signal take-off means extending toward the upper and; 상기 신호인출수단의 타단이 상부로 노출되도록 하는 동시에, 상기 제1반도체칩 및 제2반도체칩의 상면을 봉지하는 봉지재를 포함하여 이루어진 것을 특징으로 한다. At the same time to be exposed to the upper other end of the signal take-off means, characterized by comprising an encapsulation material for sealing the upper surface of the first semiconductor chip and second semiconductor chip.

여기서, 상기 제1반도체칩의 하면 및 측면은 봉지재 외측으로 노출되도록 함이 바람직하다. Here, the lower surface of the first semiconductor chip and the side is preferable to be exposed to outside the encapsulation material.

상기 신호인출수단은 도전성와이어 또는 도전성범프가 상부 방향으로 적층되어 이루어질 수 있다. The signal take-off means may be formed of a conductive wire or conductive bumps are stacked in the upper direction.

상기 신호인출수단은 제1반도체칩 및 제2반도체칩의 입출력패드로부터 봉지 재의 상면까지, 상기 봉지재의 상면에 대해 직각 방향으로 연장될 수 있다. The signal take-off means may be extended in a direction perpendicular to the upper surface of the first semiconductor chip and the material to the top sealing member from the input and output pads of the second semiconductor chip, the encapsulation.

또한, 상기 신호인출수단은 봉지재의 상면과 인접하는 부분이 상기 봉지재의 상면과 직각방향으로 위치됨이 바람직하다. In addition, the signal take-off means is a position search is preferably a portion adjacent to the upper surface of sealing material to the upper surface at right angles with the direction of the sealing member.

상기 신호인출수단은 3차원적으로 다수회 절곡됨으로써, 상기 신호인출수단의 단부가 봉지재 상면에 열과 행을 가지며 어레이됨이 바람직하다. The signal take-off means is the search a plurality of times by being bent, the end portions of the signal take-off means having columns and rows on the upper surface of the encapsulant array in three dimensions are preferred.

상기 신호인출단자는 상기 봉지재 상면과 인접하는 상기 봉지재 내측 영역의 단부가 단면상 반구형으로 형성될 수 있다. The signal lead-out terminals has the sealing material of the inner end region adjacent to the upper surface of the sealing material can be formed into a semi-spherical cross section.

상기 신호인출단자는 상기 봉지재 상면으로 단부가 돌출되어 니들형 돌출부가 형성될 수 있다. The signal lead-out terminals are projected in an end portion upper surface of the sealing material it may be formed with a needle-like projection.

상기 신호인출단자는 상기 봉지재 상면으로 단부가 연장되어 단면상 반구형 돌출부가 더 형성될 수도 있다. The signal lead-out terminals are end is extended in the upper surface of the encapsulation material may be a cross-sectionally semi-spherical protrusions further formed. 상기 신호인출단자는 상기 봉지재 상면으로 단부가 돌출된 부분에 단면상 반구형의 돌출부가 더 형성될 수 있다. The signal lead-out terminals may be further formed on the end face of the semi-spherical projection on the end protruding portions in the upper surface of the encapsulation material.

상기 적층된 범프의 단부는 봉지재 상면으로 노출 또는 돌출됨이 바람직하다. It said ends of the stacked bumps is preferably being exposed or protruding top surface encapsulation material.

상기 봉지재 상면으로 노출된 범프의 단부에는 도전성볼이 더 융착될 수 있다. The ends of the bumps exposed to the upper surface of the sealing material, there may be further fused conductive ball.

또한, 상기한 목적을 달성하기 위해 본 발명은 다수의 스크라이브 라인에 의해 다수의 제1반도체칩이 대략 바둑판 형상으로 어레이되어 있는 웨이퍼를 제공하는 단계와; Further, the steps of the present invention to achieve the above object provides a plurality of the wafer with a first semiconductor chip is about the array in a checkerboard-like by a number of scribe line; 상기 각각의 제1반도체칩 상면에 접착수단을 이용하여 상기 제1반도체칩의 크기보다 작은 제2반도체칩을 접착하는 단계와; The step of using the adhesive means on the upper surface of each of the first semiconductor chip bonding the first semiconductor chip smaller than the second size of the first semiconductor chip and; 상기 제1반도체칩 및 제2반도 체칩에 신호인출수단의 단부를 본딩하는 단계와; Wherein the first semiconductor chip and the second peninsula bonding the end portions of the signal take-off means in the chechip; 상기 제1반도체칩, 제2반도체칩 및 신호인출수단을 봉지재로 봉지하는 단계와; The step of sealing the first semiconductor chip, the second semiconductor chip and the signal take-off means in the encapsulation material and; 상기 웨이퍼에 형성된 스크라이브 라인을 따라 상기 봉지재 및 제1반도체칩을 낱개로 절단하는 단계를 포함하여 이루어진 것을 특징으로 한다. Along a scribe line formed on the wafer characterized in that made in a step to cut the sealing material, and the first semiconductor chip individually.

상기 봉지 단계후 상기 제1반도체칩과 제2반도체칩에 본딩된 신호인출수단의 타단이 봉지재 외측으로 노출되도록 일정두께의 봉지재 상면을 그라인딩하는 단계가 더 포함됨이 바람직하다. After the sealing step wherein the first semiconductor chip is further included, and the other end of the second signal take-off means for bonding to a semiconductor chip comprising: grinding a top surface encapsulation material having a predetermined thickness so as to be exposed outside the encapsulating material is preferred.

상기 신호인출수단은 도전성와이어일 수 있다. The signal take-off means may be a conductive wire.

상기 도전성와이어는 일단이 제1반도체칩에 본딩되고, 타단이 제2반도체칩에 본딩됨이 바람직하다. It said conductive wire is bonded to one end and the first semiconductor chip, the other end being bonded to the second semiconductor chip is preferable.

상기 도전성와이어는 제1반도체칩 및 제2반도체칩의 상면에 대해 대략 수직 방향으로 봉지재의 그라인딩될 면까지 연장시킴이 바람직하다. The conductive wire is preferably having to be extended to the surface grinding sealing member in a substantially perpendicular direction to the upper surface of the first semiconductor chip and second semiconductor chip.

상기 도전성와이어는 3차원적으로 절곡시켜 차후 봉지재의 그라인딩된 면에 상기 도전성와이어의 단부가 어레이되도록 함이 바람직하다. The conductive wire is preferably also such that the ends of the conductive wire array to the grinding surface material subsequent bag by bending in three dimensions.

상기 도전성와이어는 제1반도체칩 및 제2반도체칩에 일단을 본딩하고, 봉지재의 그라인딩될 면 근방에서 상기 도전성와이어의 직경보다 크게 볼을 더 형성할 수 있다. The conductive wire may be first bonded to one end to the semiconductor chip and second semiconductor chip, and forming a further view larger than the diameter of the conductive wire in the vicinity of the surface to be sealed grinding material.

상기 도전성와이어는 그 단부가 봉지재 상면으로 돌출되도록 그라인딩할 수도 있다. The conductive wire may be grinding so that the end portion is projected in the upper surface sealing material.

상기 봉지재 상면으로 돌출된 도전성와이어의 단부를 리플로우하여 봉지재 상면에 단면상 반구형 돌출부가 형성되도록 할 수 있다. To reflow the end portion of a conductive wire that protrudes to the upper surface of the encapsulant may be formed such that a cross-sectionally semi-spherical projections on the upper surface of the encapsulation material.

상기 봉지재 상면으로 돌출된 도전성와이어의 단부에는 도전성볼을 더 융착할 수도 있다. End of a conductive wire that protrudes to the upper surface of the encapsulation material may be further fused to the conductive ball.

상기 신호인출수단은 상부로 적층된 다수의 도전성범프로 할 수도 있다. The signal take-off means may be a plurality of conductive bumps in a stacked thereon.

이때, 상기 그라인딩 단계는 도전성범프의 단부가 봉지재 상면으로 돌출되도록 할 수도 있다. In this case, the grinding step may be such that the end portions of the conductive bumps projecting upper surface sealing material.

또한, 상기 절단단계후 봉지재 상면으로 노출된 도전성범프의 표면에 도전성볼을 더 융착할 수도 있다. In addition, a conductive ball on the surface of the conductive bump exposure after the cutting step to the upper surface of the encapsulation material may be further fused.

상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면 반도체칩을 적층함으로 반도체패키지의 고기능화를 구현함은 물론, 반도체칩의 상면에만 봉지재가 봉지됨으로써 칩싸이즈화된 반도체패키지를 얻게 된다. And according to the present invention, a semiconductor package and a manufacturing method by also implementing the high function of the semiconductor package by stacking the semiconductor chip, as well as sealing material sealing only the upper surface of the semiconductor chip as described above, whereby is obtained a semiconductor package chip to customer specification screen.

또한, 종래와 같은 인쇄회로기판이나 써킷필름 등을 구비하지 않고서도 신호인출수단을 이용하여 반도체칩으로부터 신호를 직접 마더보드에 전달할 수 있게 되고, 또한 저렴한 가격으로 반도체패키지를 제조할 수 있게 된다. Further, with reference to Fig signal take-off means without having a, such as a printed circuit board or-circuit film as in the prior art to be able to forward the signal directly to the motherboard from the semiconductor chip, it is possible also to manufacture a semiconductor package at low price.

더불어, 반도체칩의 하면 내지 측면이 공기중으로 직접 노출됨으로써 방열성능이 우수한 반도체패키지를 얻게 된다. Furthermore, by being of the semiconductor chip it is directly exposed to the air side to the heat radiation performance is obtained a superior semiconductor package.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다. Referring now to the accompanying drawings, preferred embodiments of the present invention self skilled enough to easily carry out the present invention in the art and described in detail as follows.

도1a 내지 도1e는 본 발명에 의한 신호인출수단으로서 도전성와이어를 이용 한 반도체패키지(101~105)의 단면도이다. Figure 1a to Figure 1e is a cross-sectional view of a semiconductor package (101 ~ 105) using the conductive wire as a signal take-off means according to the present invention.

먼저 도1a에 도시된 반도체패키지(101)를 참조하면, 상면에 다수의 입출력패드(4)가 형성된 제1반도체칩(2)이 구비되어 있다. Referring first to the semiconductor package 101 shown in Figure 1a, is provided with a first semiconductor chip 2 has a plurality of input-output pad 4 formed on the upper surface. 상기 제1반도체칩(2)의 상면에는 역시 상면에 다수의 입출력패드(8)가 형성된 제2반도체칩(6)이 접착수단 예를 들면 양면접착테이프나 접착제에 의해 접착되어 있다. An upper surface of the first semiconductor chip 2, there are also, for the second semiconductor chip 6, the adhesive means is a plurality of input-output pads (8) formed on an upper surface of the adhesive for example by a double-faced adhesive tape or glue. 물론, 상기 제2반도체칩(6)이 제1반도체칩(2)의 입출력패드(4)와 간섭하지 않토록 상기 제1반도체칩(2)의 입출력패드(4)는 엣지패드형(Edge Pad Type)이며, 상기 제2반도체칩(6)의 크기는 제1반도체칩(2)의 크기보다 작게 되어 있다. Of course, the second semiconductor chip 6, the first input-output pad (4) of the semiconductor chip (2) input pad 4 and does not interfere with ever the first semiconductor chip (2) of the edge pad (Edge Pad Type a), the size of the second semiconductor chip (6) is smaller than the size of the first semiconductor chip (2).

한편, 상기 제1반도체칩(2)의 입출력패드(4)와 상기 제2반도체칩(6)의 입출력패드(8)에는 각각 신호인출수단의 일단이 본딩되어 있고, 타단은 상기 제1반도체칩(2) 및 제2반도체칩(6)의 상부를 향해 연장되어 있다. On the other hand, the second and the first input-output pad (8) of the semiconductor chip (2) input pads 4 of the second semiconductor chip (6) has one end the bonding in each of the signal take-off means, the other end of the first semiconductor chip, (2) and extends towards the top of the second semiconductor chip (6). 여기서, 상기 신호인출수단은 골드와이어 또는 알루미늄와이어와 같은 도전성와이어(10)를 이용할 수 있다. Here, the signal take-off means may utilize a conductive wire 10 such as gold wires or aluminum wires.

계속해서, 상기 제1반도체칩(2) 및 제2반도체칩(6)의 상면은 봉지재(12)로 봉지되어 있되, 상기 신호인출수단의 타단은 상기 봉지재(12) 외측으로 노출되어 상기 봉지재(12) 상면과 동일면의 노출면(10a)을 이루고 있다. Subsequently, the first top surface of the semiconductor chip 2 and the second semiconductor chip (6) is a capping sealed with a sealing material 12, the other end of the signal take-off means is exposed to the outside the sealing material 12, the It forms the encapsulation material (12) exposed surfaces of the upper surface and the same surface (10a). 상기 봉지재(12) 외측으로 노출된 신호인출수단은 차후 마더보드의 패턴에 실장된다. The signal take-off means is exposed to the outside the sealing material 12 is mounted on the pattern of the subsequent motherboard.

한편, 상기 봉지재(12)는 제1반도체칩(2) 및 제2반도체칩(6)의 상면만을 감싸는 형태를 함으로써, 상기 제1반도체칩(2)의 하면과 측면은 공기중으로 직접 노출되어 반도체패키지(101)의 방열성능이 향상된다. On the other hand, the sealing material 12 is first, by the only wrap forms the top surface of the semiconductor chip 2 and the second semiconductor chip 6, when the side surface of the first semiconductor chip 2 is directly exposed to the air the heat radiating performance of the semiconductor package 101 can be improved.

전술한 바와 같이 상기 반도체패키지(101)는 상기 제1반도체칩(2) 및 제2반 도체칩(6)의 입출력패드(4,8)에 연결된 신호인출수단의 노출면(10a)이 직접 마더보드에 실장되며, 따라서 종래와 같은 인쇄회로기판 및 써킷필름과 같은 부자재가 필요없게 된다. The semiconductor package 101 as described above is the first semiconductor chip 2 and the second exposed surface of the take-off means connected to the signal input-output pads (4,8) of the semiconductor chip (6), (10a) a direct motherboard It is mounted on the board, so that the auxiliary materials, such as a printed circuit board and a film-circuit as in the prior art is not required.

다음으로 도1b를 참조하며, 이하의 설명에서 제시되는 반도체패키지는 도1a에서 언급된 것과 유사하므로 그 차이점을 중심으로 설명하기로 한다. With reference to Figure 1b, and so the semiconductor package set forth in the following description is similar to that referred to in Figure 1a it will be described by focusing the difference.

도1b에 도시된 반도체패키지(102)는 도1a의 반도체패키지(101)와 다르게 신호인출수단이 제1반도체칩(2) 및 제2반도체칩(6)의 상면과 수직 방향으로 연장되어 있다. The semiconductor package 102 shown in Fig. 1b is a semiconductor package 101 and the different signal take-off means extends in the upper surface and the vertical direction of the first semiconductor chip 2 and the second semiconductor chip 6 of Figure 1a. 즉, 도1a의 반도체패키지(101)에서는 신호인출수단이 제1반도체칩(2) 및 제2반도체칩(6)의 상면에서 곡선을 그리며 상부로 연장됨에 따라 그 봉지재(12) 상면에 형성되는 신호인출수단의 노출면(10a)이 타원형으로 형성된다. That is, formed on the top semiconductor package 101 of Figure 1a in the signal take-off means is a first semiconductor chip 2 and the second that the encapsulation material (12) drawing a curve on the top surface according to extend to the upper portion of the semiconductor chip 6 the exposed surface (10a) of the signal take-off means is formed as an oval. 그러나, 도1b의 반도체패키지(102)에서는 상기 신호인출수단을 제1반도체칩(2) 및 제2반도체칩(6)의 상면에 대하여 수직 방향으로 연장시킴으로써 봉지재(12) 상면에 노출되는 신호인출수단의 노출면(10a)이 정확히 원형이 되도록 한 것이다. However, the semiconductor package 102 of Figure 1b in the signal which is exposed on the upper surface of the encapsulation material (12) by extending the signal take-off means in a direction perpendicular to the upper surface of the first semiconductor chip 2 and the second semiconductor chip 6 the exposed surface (10a) of the drawing means to the one to be exactly circular.

다음으로 도1c의 반도체패키지(103)를 참조하면, 도1b의 반도체패키지(102)와 다르게 신호인출수단이 봉지재(12)의 상면과 인접하는 부분에서부터 제1반도체칩(2) 및 제2반도체칩(6)의 상면과 수직방향으로 되어 있다. Next, Referring to the semiconductor package 103 of 1c, from the portion different from the semiconductor package 102 of the Figure 1b signal take-off means is adjacent to the upper surface of the sealing material 12, the first semiconductor chip 2 and the second is the upper surface and the vertical direction of the semiconductor chip (6). 이는 도1b에 도시된 반도체패키지(102)와 같은 효과를 얻기 위함이다. This is to obtain the same effect as the semiconductor package 102 shown in Figure 1b. 또한 도1c에 도시된 반도체패키지(103)에서는 상기 신호인출수단을 3차원적으로 절곡하여 상부로 연장시켰다. In addition, the semiconductor package 103 shown in Fig. 1c by bending the signal take-off means in three dimensions was extended to the upper part. 즉, 상기 신호인출수단을 3차원적으로 절곡하게 되면, 봉지재(12) 상면을 매우 효율성있게 이용할 수 있다. In other words, when the bending of the signal take-off means in three dimensions, can be used allowing the encapsulation material (12) the upper face extremely efficient. 다시 말하면, 상기 신호인출수단의 노출면(10a)의 어레이된 상태를 사용자 임의로 디자인할 수 있게 됨으로써 반도체패키지 및 마더보드의 설계를 보다 용이하게 하도록 유도한다. In other words, the induction being an array state of the exposed surface (10a) of the signal take-off means can be designed arbitrarily user to make it easier to design a semiconductor package and a mother board. 또한, 상기 봉지재(12) 상면으로 노출되는 신호인출수단의 노출면(10a) 각각이 최대로 이격되도록 함으로써 상기 반도체패키지(103)를 마더보드에 실장시 각 노출면(10a) 사이의 쇼트 현상도 방지할 수 있게 된다. In addition, the short phenomenon between the sealing material 12 exposed in the signal take-off means which is exposed to the upper surface side (10a) the time of mounting the semiconductor package 103 by to be spaced apart with each up to the mother board each exposed surface (10a) also it can be prevented.

도1d의 반도체패키지(104)를 참조하면, 봉지재(12) 상면과 인접하는 봉지재(12) 내측 영역의 신호인출단자에는 단면상 반구형인 단부(12b)가 형성되어 있다. Referring to the semiconductor package 104 of FIG. 1d, the encapsulant 12 encapsulating material adjacent to the upper surface (12) take-off signal of the inner terminal area are formed at the hemispherical end portion (12b) cross section.

또한, 도1e의 반도체패키지(105)를 참조하면, 봉지재(12) 상면과 인접하는 봉지재(12) 내측 영역의 신호인출수단이 단면상 반구형인 단부(12b)로 되어 있을 뿐만 아니라, 신호인출수단 전체가 제1반도체칩(2) 및 제2반도체칩(6)의 상면과 대략 수직 방향으로 상부를 향해 연장되어 있다. In addition, Referring to the semiconductor package 105 of 1e, not only the signal take-off means of the sealing material 12, the upper surface and the adjacent sealing material 12 inside region, which is a semi-spherical in the end (12b), the cross section, the signal take- It means the entirety extends toward the top by the upper surface and substantially vertical direction of the first semiconductor chip 2 and the second semiconductor chip (6).

따라서, 상기 도1d 및 도1e의 반도체패키지(104,105)에서 봉지재(12) 상면으로 노출되는 신호인출수단의 노출면(10a)은 도1a 내지 도1c의 반도체패키지(101~103)에 개시된 노출면(10a)보다 그 면적이 더 크게 됨으로써 마더보드에의 실장이 보다 안정적으로 수행된다. Thus, the Fig. 1d and the exposed surface (10a) of the signal take-off means which is exposed on the semiconductor packages 104 and 105 of Figure 1e on the upper surface sealing material 12 is disclosed in the semiconductor package 101 to 103 of Fig. 1a to Fig. 1c exposure whereby the area is larger than the surface (10a) is stably performed than the mounting of the motherboard. 또한 여기서 상기 도1d의 반도체패키지(104)에 도시된 신호인출수단의 노출면(10a)은 평면상 타원형인 반면, 도1e의 반도체패키지(105)에 도시된 신호인출수단의 노출면(10a)은 평면상 대략 원형이다. In addition, the signal take-exposed surface (10a) of the means shown in the semiconductor package 104 of Figure 1d is an exposed surface (10a) of the plane ellipse, while the signal take-off means shown in the semiconductor package 105 of FIG. 1e, where It is a substantially circular planar.

도2는 도1a 내지 도1e에 도시된 반도체패키지(101~105)의 통상적인 사시도로서, 도시된 바와 같이 봉지재(12) 상면에 다수의 신호인출수단의 노출면(10a)이 구 비되어 있으며, 상기 노출면(10a)은 행과 열을 가지며 어레이되어 있다. 2 is a typical perspective view of a semiconductor package (101-105) shown in FIG. 1a to 1e, is a plurality of the exposed surface (10a) of the signal take-off means on the upper surface of the encapsulation material (12), obtain, as illustrated non- and the exposed surface (10a) is an array having rows and columns. 상기 노출면(10a)의 어레이 상태는 상기 신호인출수단을 3차원적으로 다수회 절곡함에 의해 임의적으로 조정할 수 있다. The array state of said exposed surface (10a) can be adjusted arbitrarily by a plurality of times as the bending of the signal take-off means in three dimensions.

도3a 내지 도3c는 본 발명에 의한 신호인출수단으로서 도전성와이어 및 도전성볼을 이용한 반도체패키지(106~108)를 도시한 단면도이다. Figures 3a-3c is a cross-sectional view showing a semiconductor package (106 ~ 108) using a conductive wire and the conductive ball as a signal take-off means according to the present invention.

여기서, 도3a 내지 도3c에 도시된 반도체패키지(106~108) 역시 상기 도1a 내지 도1e에 도시된 반도체패키지(101~105)와 유사하므로 그 차이점만을 설명하기로 한다. Here, it is because a semiconductor package (106-108), also the semiconductor package (101-105) shown in FIG. 1a to 1e shown in Figs. 3a to 3c will be explained only the difference.

먼저 도3a의 반도체패키지(106)를 참조하면, 제1반도체칩(2) 및 제2반도체칩(6)의 입출력패드(4,8)에 일단이 본딩된 신호인출수단의 타단은 봉지재(12) 상면상으로 일정길이 돌출되어 돌출부(10c)를 형성하고 있다. Referring first to the semiconductor package 106 of FIG 3a, the first semiconductor chip 2 and the second other end of the one end bonded to the leading unit signal input and output pads (4,8) of the semiconductor chip (6) is a sealing material ( 12) is a predetermined length projected onto the surface to form a projection (10c). 이와 같은 반도체패키지는 상기 돌출부(10c)가 마더보드에 실장될 때에 보다 많은 융착 면적을 제공하게 됨으로써 마더보드와의 조인트력이 향상된다. Such a semiconductor package is thereby to provide the projecting portion (10c) is large than when the welding area to be mounted on a mother board is improved joint force of the motherboard. 여기서 상기 신호인출수단은 도전성와이어(10)이다. Here, the signal take-off means is a conductive wire (10).

또한 도3b의 반도체패키지(107)를 참조하면, 상기 신호인출수단의 타단 즉, 봉지재(12) 상면에는 단면상 반구형의 돌출부(10d)가 형성될 수도 있다. Referring also to the semiconductor package 107 of Figure 3b, the other end of the signal take-off means that is, the upper surface sealing material 12, may be formed with a projection (10d) of the semi-spherical cross section. 이는 도3a에 도시된 반도체패키지(106)의 돌출부(10c)를 리플로우(Reflow)함으로써 형성된 것이다. This is formed by a reflow (Reflow) a projection (10c) of the semiconductor package 106 shown in Figure 3a.

한편, 도3c에 도시된 바와 같이, 상기 신호인출수단의 타단 즉, 봉지재(12) 상면으로 노출된 신호인출수단의 돌출부(10c)에는 별도의 솔더볼이나 골드볼과 같 은 도전성볼(14)을 더 융착시킬 수 있다. On the other hand, the, there is a conductive ball 14 is equal to the extra solder balls or gold ball protrusions (10c) of the signal take-off means for exposing the other end of the signal take-off means that is, the upper surface sealing material 12 as shown in Figure 3c the fusion can be more.

상기와 같은 도3a 내지 도3c에 도시된 모든 반도체패키지(106~108)는 마더보드와의 조인트력을 향상시킬 수 있는 장점이 있다. (108 to 106), Figures 3a to all the semiconductor package shown in Figure 3c as described above has the advantage to improve the joint strength between the mother board.

도4a 내지 도4c는 본 발명에 의한 신호인출수단으로서 도전성 범프를 이용한 반도체패키지(109~111)의 단면도이다. Figures 4a to 4c is a cross-sectional view of the semiconductor package (109 ~ 111) using the bump as a conductive signal take-off means according to the present invention.

먼저 도4a의 반도체패키지(109)를 참조하면, 도시된 바와 같이 신호인출수단으로서 다수의 도전성 범프(16)가 제1반도체칩(2) 및 제2반도체칩(6)의 상면과 수직 방향으로 적층되어 봉지재(12) 상면까지 연장되어 있다. Referring first to the semiconductor package 109 shown in Figure 4a, a plurality of the conductive bumps 16 as a signal take-off means as shown by the upper surface and the vertical direction of the first semiconductor chip 2 and the second semiconductor chip 6 It is stacked and extends to the upper surface sealing material 12. 상기 신호인출수단의 단부(18) 즉, 봉지재(12)의 상면과 인접하는 범프(16)의 단부(18)는 봉지재(12) 상면상으로 일정길이 돌출되어 있다. End 18 of the bump 16 adjacent to the upper surface of the signal means of the take-off end (18) In other words, the encapsulant 12 is a predetermined length projected in the surface encapsulation material (12).

한편, 도4b의 반도체패키지(110)를 참조하면, 상기 범프(16)의 단부(노출면(16a))와 봉지재(12)의 상면은 동일면을 갖도록 할 수도 있다. On the other hand, with reference to semiconductor package 110 of FIGURE 4b, the upper surface of the end portion (exposed surfaces (16a)) and encapsulation material (12) of the bumps 16 may have the same surface.

또한, 도4c의 반도체패키지(111)와 같이, 상기 봉지재(12)의 상면과 동일면인 범프(16)의 단부(16a)에 솔더볼 또는 골드볼과 같은 도전성볼(14)을 더 융착할 수도 있다. Furthermore, as the semiconductor package 111 of 4c, the sealing material 12, an upper surface coplanar with the solder ball to the end portion (16a) of the bump 16 or gold ball and a conductive ball 14 may be further fused to such a have.

상기 도4a 및 도4c의 반도체패키지(109,111)는 봉지재(12) 상면으로 범프(16)가 돌출되어 있던가 또는 별도의 도전성볼(14)이 더 융착되어 있음으로써 마더보드와의 조인트력이 도4b의 반도체패키지(110)에 비해 우수한 장점이 있다. The semiconductor package (109 111) of FIGS. 4a and 4c has a sealing material 12 is a bump 16 projected in the upper surface itdeonga or even the joint force of the extra conductive balls 14 as that is further fused motherboard It has excellent advantages as compared to 4b semiconductor package 110 of.

도5a 내지 도5d는 본 발명에 의한 반도체패키지의 제조 방법을 도시한 설명도이다. Figures 5a through 5d is an explanatory view showing a method of manufacturing a semiconductor package according to the present invention.

먼저 다수의 스크라이브 라인(Scribe Line)(낱개의 반도체칩으로 소잉(Sawing)시 기준이되는 라인)에 의해 다수의 제1반도체칩(2)이 대략 바둑판 형상으로 어레이되어 있는 웨이퍼(w)를 제공한다. First providing a plurality of first semiconductor chip 2 of the wafer that is substantially the array in a checkerboard-like (w) by a plurality of scribe lines (Scribe Line) (in the singulated semiconductor chip sawing (Sawing) line serving as a reference when) do.

이어서 상기 웨이퍼(w)의 각 제1반도체칩(2) 상면에 접착수단을 이용하여 상기 제1반도체칩(2)의 크기보다 작은 제2반도체칩(6)을 접착한다. It is then bonded to each first device using the adhesive on the upper surface of the semiconductor chip (2) is smaller than the size of the first semiconductor chip 2 and the second semiconductor chip (6) of the wafer (w).

여기서, 상기 제1반도체칩(2)은 입출력패드(4)가 엣지패드형으로 된 것을 사용하며, 상기 제2반도체칩(6)은 상기 제1반도체칩(2)의 입출력패드(4)와 간섭하지 않토록 제1반도체칩(2)의 크기보다 작은 것을 이용한다. Here, as the first semiconductor chip 2 is input pad 4 are uses for something in the edge pad, the second semiconductor chip (6) is the first input-output pad (4) of the semiconductor chip (2) ever does not interfere with use is smaller than the size of the first semiconductor chip (2).

계속해서, 상기 제1반도체칩(2)의 입출력패드(4)와 제2반도체칩(6)의 입출력패드(8) 각각에 신호인출수단의 일단을 본딩한다. Subsequently, the bonding of the first end of the signal take-off means in each input-output pads 8 of the input-output pad (4) and the second semiconductor chip (6) of the semiconductor chip (2).

이는 도5a에 도시된 바와 같이 도전성와이어(10)를 이용할 수도 있으며, 이때에는 상기 제1반도체칩(2)의 입출력패드(4)와 제2반도체칩(6)의 입출력패드(8)를 하나의 도전성와이어(10)로 상호 접속함이 바람직하다. This may take advantage of the conductive wire 10 as shown in Figure 5a, this time, the one input pad 4 and the input-output pads (8) of the second semiconductor chip (6) of the first semiconductor chip 2 this is preferably also interconnected by conductive wires (10).

또한, 이때 상기 도전성와이어(10)로 상호 접속하는 중에는 상기 도전성와이어(10)의 중간 부분에 볼을 형성한 후 접속 작업을 완료할 수도 있다. Further, at this time while interconnecting with the electrically conductive wire 10 may be completing the connecting operation after the formation of the ball in the middle portion of the conductive wire (10).

예를 들면, 상기 제1반도체칩(2)의 입출력패드(4)에 도전성와이어(10)의 일단을 본딩한 후 일정 높이에서 볼을 형성하고, 다시 제2반도체칩(6)의 입출력패드(8)에 도전성와이어(10)의 타단을 본딩하기 전에 일정크기의 볼을 형성한 후, 타단을 상기 제2반도체칩(6)의 입출력패드(8)에 본딩할 수 있다. For example, the input-output pads of the first semiconductor chip 2, output pad 4, the conductive wires 10, one end after forming the ball from a predetermined height, the second semiconductor chip (6) re-bonding of the ( 8) to be bonded to the input and output pads (8) of the conductive wire 10 is constant after formation of the size of the ball, and the second semiconductor chip 6 to the other end prior to bonding of the other ends. 상기 볼의 형성 높이는 하기에서 설명할 봉지재(12)의 그라인딩될 면 부근에 형성함이 바람직 하다. It is preferable to be formed in the vicinity of the grinding surface of the encapsulation material 12 to be described the height of the formed ball.

또한, 상기 도전성와이어(10)는 일정 높이로 제1반도체칩(2) 및 제2반도체칩(6)의 상면과 대략 수직이 되도록 연장시킴이 바람직하며, 3차원적으로 다수회 절곡시켜 연장시킬 수도 있다. In addition, the conductive wire 10 and the extension Sikkim preferably such that the top surface and substantially perpendicular to the first semiconductor chip 2 and the second semiconductor chip 6 at a certain height, to bent a plurality of times in a three-dimensional manner to extend may.

또한, 상기 신호인출수단으로서 도전성와이어(10) 대신 다수의 도전성 범프(16)를 적층하여 사용할 수도 있다. Furthermore, as the signal take-off means may be used by laminating a plurality of conductive bumps 16 instead of the conductive wire (10).

계속해서, 도5b에 도시된 바와 같이 상기 웨이퍼(w)(제1반도체칩(2)), 제2반도체칩(6)의 상면을 에폭시몰딩컴파운드 또는 액상봉지재와 같은 봉지재(12)를 이용하여 봉지한다. Subsequently, the said wafer (w) (the first semiconductor chip 2), and the second sealing material, such as the upper surface of the semiconductor chip 6 and an epoxy molding compound or a liquid encapsulant 12 as shown in Figure 5b the bags used. 이때, 상기 신호인출수단 전체가 봉지재(12) 내측으로 완전히 위치하도록 하거나, 또는 신호인출수단(도전성와이어(10) 또는 도전성범프(16))의 일단이 봉지재(12) 외측으로 위치하도록 봉지할 수 있다. At this time, the whole of the signal take-off means for sealing material 12 or to be completely located inside, or the signal take-off means (conductive wire 10 or the conductive bumps 16) once the sealing material 12 of the bag so as to be positioned to the outside can do.

이어서, 도5c에 도시된 바와 같이 상기 봉지재(12)의 상면으로부터 일정깊이의 봉지재(12)를 그라인딩하여 제거한다. Then, as illustrated in Figure 5c removed by grinding the encapsulation material in a predetermined depth (12) from a top surface of the encapsulant (12). 즉, 제1반도체칩(2) 및 제2반도체칩(6)의 각 입출력패드(4,8)에 상호 연결된 신호인출수단이 서로 단선되고, 또한 반도체패키지의 전체적인 두께가 더욱 박형화되도록 봉지재(12)의 상면을 그라인딩하여 제거한다. That is, the first cross-coupled signal take-off means in each input-output pad (4,8) of the semiconductor chip 2 and the second semiconductor chip 6 are disconnected from each other, and sealing material such that further thinning the entire thickness of the semiconductor package ( It is removed by grinding the top surface 12). 상기 신호인출수단으로서 다수의 도전성 범프(16)를 이용했을 경우에는 상기 제1반도체칩(2) 및 제2반도체칩(6)의 입출력패드(4,8)에 형성된 도전성 범프(16)는 이미 단선된 상태이다. When using a plurality of the conductive bumps 16 as the signal take-off means, the conductive bump 16 formed on the input-output pads (4,8) of the first semiconductor chip 2 and the second semiconductor chip 6 has been It is a disconnection state.

상기와 같이 그라인딩 작업이 완료된 후에는 상기 봉지재(12) 상면으로 노출 또는 돌출된 신호인출수단 즉, 도전성와이어(10) 또는 도전성범프(16)의 단부에 도 전성볼(14)을 더 융착할 수 있다. After the grinding operation as described above is completed, the sealing material 12, a signal leading unit exposed or protruded to the upper surface that is, further fused to FIG conductive balls 14 to the ends of the conductive wire 10 or the conductive bumps 16 can. 또한, 상기 봉지재(12) 상면으로 신호인출수단이 돌출된 경우에는 그 돌출된 부분을 리플로우함으로써 단면상 반구형이 되도록 할 수도 있다. Alternatively, if the the sealing material 12, the upper surface to the signal take-off means is a protrusion, it may be reflowed by the protruding portion so that the semi-spherical cross section.

이어서, 도5d에 도시된 바와 같이 웨이퍼(w)에 형성된 스크라이브 라인을 따라서, 봉지재(12) 및 웨이퍼(w)를 동시에 소잉하여 낱개의 반도체패키지로 분리해 내며, 상기와 같이 분리된 반도체패키지는 곧바로 실장 가능한 형태가 된다. Then, along a scribe line formed on the wafer (w) as shown in Figure 5d, the encapsulation material 12 and by sawing the wafer (w) at the same time naemyeo separated into semiconductor packages individually, the semiconductor package separation, such as the is a straight mounting form.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다. The present invention, as in the above will be possible, though has been described only the embodiments of the not limited to this, the embodiment in variously modified without departing from the scope and spirit of the invention.

따라서, 본 발명에 의한 반도체패키지 및 그 제조 방법에 의하면 반도체칩을 적층함으로 반도체패키지의 고기능화를 구현함은 물론, 반도체칩의 상면에만 봉지재가 봉지됨으로써 칩싸이즈화된 반도체패키지를 얻을 수 있는 효과가 있다. Therefore, according to the semiconductor package and a manufacturing method of the present invention also implements the high function of the semiconductor package by stacking the semiconductor chips is, of course, is an effect that it is possible to obtain a semiconductor package chip to customer specification screen whereby only sealing material sealing the upper surface of the semiconductor chip have.

또한, 종래와 같은 인쇄회로기판이나 써킷필름 등을 구비하지 않고서도 신호인출수단을 이용하여 반도체칩으로부터 신호를 직접 마더보드에 전달할 수 있게 되고, 또한 저렴한 가격으로 반도체패키지를 제조할 수 있는 효과가 있다. Further, with reference to Fig signal take-off means without having a, such as a printed circuit board or-circuit film as in the prior art to be able to forward the signal directly to the motherboard from the semiconductor chip, and is an effect that it is possible to manufacture a semiconductor package at low price have.

더불어, 반도체칩의 하면 내지 측면이 공기중으로 직접 노출됨으로써 방열성능이 우수한 반도체패키지를 얻을 수 있는 효과가 있다. Furthermore, by being of the semiconductor chip it is directly exposed to the air side to the effect that can be obtained a semiconductor package excellent heat radiation performance.

Claims (26)

  1. 상면의 내주연에 다수의 입출력패드가 형성된 제1반도체칩과, The first semiconductor chip to the inner periphery of the upper surface of the plurality of input-output pads formed and,
    상면에 다수의 입출력패드가 형성되고, 상기 제1반도체칩에 형성된 입출력패드의 안쪽 영역으로서 상기 제1반도체칩의 상면에 상기 제1반도체칩의 크기보다 작은 크기를 가지며 접착수단에 의해 접착된 제2반도체칩과, The formed a plurality of input-output pads on the upper surface, the first as the inside area of ​​the input-output pads formed on the semiconductor chip has a smaller size than the size of the first semiconductor chip on an upper surface of the first semiconductor chip bonded by an adhesive means the the second semiconductor chip;
    상기 제1반도체칩 및 제2반도체칩의 입출력패드에 일단이 본딩되고, 타단이 상부를 향해 연장된 다수의 신호인출수단과, Wherein the first and one end is bonded to the input and output pads of the semiconductor chip and second semiconductor chip, the other end a plurality of signal take-off means extending toward the upper and,
    상기 제1반도체칩, 제2반도체칩 및 다수의 신호인출수단을 봉지하되, 상기 신호인출수단의 타단이 상부로 노출되고, 상기 제1반도체칩의 하면 및 측면도 외부로 노출되도록 하는 봉지재를 포함하여 이루어진 것을 특징으로 하는 반도체패키지. Comprises a sealing material such that the first lower surface of the semiconductor chip, the second semiconductor chip and a plurality of signal but sealing a drawing means, and exposed to the upper other end of the signal take-off means, wherein the first semiconductor chip and a side exposed to the outside a semiconductor package, characterized in that made in.
  2. 삭제 delete
  3. 제1항에 있어서, 상기 신호인출수단은 도전성와이어인 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal take-off means is a semiconductor package characterized in that the conductive wire.
  4. 제1항에 있어서, 상기 신호인출수단은 다수의 도전성범프가 상부 방향으로 적층되어 이루어진 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal take-off means is a semiconductor package characterized by comprising a plurality of conductive bumps are stacked in the upper direction.
  5. 제1항에 있어서, 상기 신호인출수단은 제1반도체칩 및 제2반도체칩의 입출력패드로부터 봉지재의 상면까지, 상기 봉지재의 상면에 대해 직각 방향으로 연장된 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal take-off means comprises a first semiconductor chip and the semiconductor package, characterized in that the sealing material to the upper surface from the input and output pads of the semiconductor chip 2, extending in a direction perpendicular to the upper surface of the encapsulation material.
  6. 제1항에 있어서, 상기 신호인출수단은 봉지재의 상면과 인접하는 부분이 상기 봉지재의 상면과 직각방향으로 연장된 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal take-off means is a semiconductor package characterized in that a part adjacent to the upper surface of sealing material extending in a direction at right angles with the upper surface of the encapsulation material.
  7. 제1항에 있어서, 상기 신호인출수단은 3차원적으로 다수회 절곡됨으로써, 상기 신호인출수단의 단부가 봉지재 상면에 열과 행을 가지며 어레이 된 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal take-off means comprises three-dimensionally by being bent a number of times, the semiconductor package characterized in that the end of the drawing means a signal having a column and row array on the upper surface of the encapsulation material.
  8. 제1항에 있어서, 상기 신호인출단자는 상기 봉지재 상면과 인접하는 상기 봉지재 내측 영역의 단부가 단면상 반구형으로 형성된 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal lead-out terminals are semiconductor package characterized in that the sealing material of the inner end region adjacent to the upper surface of the sealing material formed in a semi-spherical cross section.
  9. 제1항에 있어서, 상기 신호인출단자는 상기 봉지재 상면으로 단부가 돌출되어 니들형 돌출부가 형성된 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal lead-out terminals are semiconductor package, characterized in that the end portion is projected in the upper surface of the encapsulation material is formed of needle-like projections.
  10. 제1항에 있어서, 상기 신호인출단자는 상기 봉지재 상면으로 단부가 연장되어 단면상 반구형 돌출부가 더 형성된 것을 특징으로 하는 반도체패키지. The method of claim 1, wherein the signal lead-out terminals are semiconductor package, characterized in that the end portion is extended in the upper surface of the encapsulant is further formed a cross-sectionally semi-spherical protrusions.
  11. 제9항에 있어서, 상기 신호인출단자는 상기 봉지재 상면으로 단부가 돌출된 부분에 단면상 반구형의 돌출부가 더 형성된 것을 특징으로 하는 반도체패키지. 10. The method of claim 9, wherein the signal lead-out terminals are semiconductor package, characterized in that the cross section is further formed of a hemispherical projection on the end protruding portions in the upper surface of the encapsulation material.
  12. 제3항에 있어서, 상기 적층된 범프의 단부는 봉지재 상면으로 노출 또는 돌출된 것을 특징으로 하는 반도체패키지. The method of claim 3, wherein the end portion of the laminated bumps semiconductor package, characterized in that the exposed or protruding top surface encapsulation material.
  13. 제12항에 있어서, 상기 봉지재 상면으로 노출된 범프의 단부에는 도전성볼이 더 융착된 것을 특징으로 하는 반도체패키지. The method of claim 12, wherein the ends of the bumps exposed to the upper surface of the semiconductor package encapsulant, characterized in that a conductive ball is more fusion.
  14. 다수의 스크라이브 라인에 의해 다수의 제1반도체칩이 대략 바둑판 형상으로 어레이되어 있는 웨이퍼를 제공하는 단계와, The method comprising: providing a plurality of the wafer with a first semiconductor chip is about the array in a checkerboard-like by a number of scribe lines and,
    상기 각각의 제1반도체칩 상면에 접착수단을 이용하여 상기 제1반도체칩의 크기보다 작은 제2반도체칩을 접착하는 단계와, A step of bonding the first semiconductor chip smaller than the second size of the first semiconductor chip using the adhesive means on the upper surface of each of the first semiconductor chip,
    상기 제1반도체칩 및 제2반도체칩에 신호인출수단의 단부를 본딩하는 단계와, The method comprising: the first semiconductor chip and said bonding ends of the signal take-off means in the second semiconductor chip,
    상기 제1반도체칩, 제2반도체칩 및 신호인출수단을 봉지재로 봉지하는 단계와, A step of sealing the first semiconductor chip, the second semiconductor chip and the signal take-off means in the encapsulation material,
    상기 웨이퍼에 형성된 스Z크라이브 라인을 따라 상기 봉지재 및 제1반도체칩을 낱개로 절단함으로써, 상기 제1반도체칩의 하면뿐만 아니라 측면도 외부로 노출되도록 하는 단계를 포함하고, Along the Z's is greater live line formed on the wafer, comprising: a side view so that the exposed by cutting the sealing material and the first semiconductor chip individually, as well as the lower surface of the first semiconductor chip,
    상기 봉지 단계후 상기 제1반도체칩과 제2반도체칩에 본딩된 다수의 신호인출수단의 타단이 봉지재 외측으로 노출되도록 일정두께의 봉지재 상면을 그라인딩하는 단계를 더 포함하여 이루어진 것을 특징으로 하는 반도체패키지의 제조 방법. After the encapsulation step, characterized in that made in the first semiconductor chip and a second other end of the plurality of signal take-off means for bonding a semiconductor chip comprising the step of grinding the encapsulation material a top surface having a predetermined thickness so as to be exposed to the encapsulant outside more the process for manufacturing a semiconductor package.
  15. 삭제 delete
  16. 제14항에 있어서, 상기 신호인출수단은 도전성와이어인 것을 특징으로 하는 반도체패키지의 제조 방법. 15. The method of claim 14 wherein the signal take-off means for manufacturing a semiconductor package, characterized in that the conductive wires.
  17. 제16항에 있어서, 상기 도전성와이어는 일단이 제1반도체칩에 본딩되고, 타단이 제2반도체칩에 본딩되는 반도체패키지의 제조 방법. 17. The method of claim 16 wherein the conductive wire is temporarily bonded to the first semiconductor chip, a method for manufacturing a semiconductor package that is the other end is bonded to a second semiconductor chip.
  18. 제16항에 있어서, 상기 도전성와이어는 제1반도체칩 및 제2반도체칩의 상면에 대해 대략 수직 방향으로 봉지재의 그라인딩될 면까지 연장시킴을 특징으로 하는 반도체패키지의 제조 방법. 17. The method of claim 16 wherein the conductive wire is for manufacturing a semiconductor package characterized by Sikkim extend to the first semiconductor chip and a second surface to be sealed grinding material in a substantially perpendicular direction to the upper surface of the semiconductor chip.
  19. 제16항에 있어서, 상기 도전성와이어는 3차원적으로 절곡시켜 차후 봉지재의 그라인딩된 면에 상기 도전성와이어의 단부가 어레이되도록 함을 특징으로 하는 반 도체패키지의 제조 방법. The method of claim 16, wherein the method for manufacturing a semiconductor package that is characterized by that the electrically conductive wire is the end of the conductive wire material to the grinding surface of the future bag was folded in three dimensions, the array.
  20. 제16항에 있어서, 상기 도전성와이어는 제1반도체칩 및 제2반도체칩에 일단을 본딩하고, 봉지재의 그라인딩될 면 근방에서 상기 도전성와이어의 직경보다 크게 볼을 더 형성하는 반도체패키지의 제조 방법. 17. The method of claim 16 wherein the conductive wire includes a first semiconductor chip and a second bonding one end to the semiconductor chip, and the method for manufacturing a semiconductor package further form a ball greater than the diameter of the conductive wire in the vicinity of the surface to be grinding material bag.
  21. 제16항에 있어서, 상기 도전성와이어는 그 단부가 봉지재 상면으로 돌출되도록 그라인딩하는 반도체패키지의 제조 방법. 17. The method of claim 16, for manufacturing a semiconductor package in which the conductive wire is the end of the grinding so as to project to the upper surface of the encapsulation material.
  22. 제21항에 있어서, 상기 봉지재 상면으로 돌출된 도전성와이어의 단부를 리플로우하여 봉지재 상면에 단면상 반구형 돌출부가 형성되도록 하는 반도체패키지의 제조 방법. 22. The method of claim 21, for manufacturing a semiconductor package such that the end portion by reflowing of the conductive wire forming the cross-sectionally semi-spherical projections on the upper surface of the encapsulation material projecting in the sealing material plane.
  23. 제21항에 있어서, 상기 봉지재 상면으로 돌출된 도전성와이어의 단부에는 도전성볼을 더 융착하는 반도체패키지의 제조 방법. 22. The method of claim 21, for manufacturing a semiconductor package is further sealed to the conductive ball end portion of a conductive wire that is projected in the upper surface of the encapsulation material.
  24. 제14항에 있어서, 상기 신호인출수단은 상부로 적층된 다수의 도전성범프인 것을 특징으로 하는 반도체패키지의 제조 방법. 15. The method of claim 14 wherein the signal take-off means for manufacturing a semiconductor package, characterized in that a plurality of conductive bumps in a stacked thereon.
  25. 제24항에 있어서, 상기 그라인딩 단계는 도전성범프의 단부가 봉지재 상면으 로 돌출되도록 하여 수행함을 특징으로 하는 반도체패키지의 제조 방법. The method of claim 24, wherein the grinding step for manufacturing a semiconductor package, characterized by carrying out by the end portion of the conductive bumps so as to project to the upper surface coming encapsulant.
  26. 제24항에 있어서, 상기 절단단계후, 봉지재 상면으로 노출된 도전성범프의 표면에 도전성볼을 더 융착하는 반도체패키지의 제조 방법. 25. The method of claim 24, for manufacturing a semiconductor package further fused after the cutting step, a conductive ball on the surface of the conductive bumps top surface exposed to the encapsulant.
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