JPH09199855A - Manufacture of multilayer interconnection board - Google Patents

Manufacture of multilayer interconnection board

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Publication number
JPH09199855A
JPH09199855A JP2318196A JP2318196A JPH09199855A JP H09199855 A JPH09199855 A JP H09199855A JP 2318196 A JP2318196 A JP 2318196A JP 2318196 A JP2318196 A JP 2318196A JP H09199855 A JPH09199855 A JP H09199855A
Authority
JP
Japan
Prior art keywords
hole
layer
copper
layers
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2318196A
Other languages
Japanese (ja)
Inventor
Yoshikuni Taniguchi
芳邦 谷口
Keiko Sogo
啓子 十河
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2318196A priority Critical patent/JPH09199855A/en
Publication of JPH09199855A publication Critical patent/JPH09199855A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To contrive to be able to make a multilayer interconnection board correspond fully to a high-density mounting. SOLUTION: Through holes 52A, 52B and 63A are bored in through hole formation positions on a base board laminated with conductor layers, which consist of a conductive material, on one surface thereof and the other surface thereof and at the same time, a first process for patterning the conductor layers 55 and 56, which are respectively laminated on the one surface of the base board and the other surface of the base board, a second process for laminating resist layers 57 and 60, which consist of a photoresist, on the layers 55 and 56, which are respectively laminated on the one surface of the base board and the other surface of the base board, and a third process, wherein the layers 57 and 60 are exposed and developed into a prescribed pattern, whereby via holes 57A and 60A are respectively formed in the layers 57 and 60 so as to communicate with the holes 52A, 52B and 63A bored in the base board, are provided. Hereby, drilling work processes can be executed together at one time and at the same time, the diameter of lands on the through holes in the outermost conductor layers 55 and 56 can be lessened. In this way, a multilayer interconnection board can be made to correspond fully to a high-density mounting.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【目次】以下の順序で本発明を説明する。 発明の属する技術分野 従来の技術(図4〜図10) 発明が解決しようとする課題(図4〜図10) 課題を解決するための手段(図1〜図3) 発明の実施の形態(図1〜図3) 発明の効果[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIGS. 4 to 10) Problems to be Solved by the Invention (FIGS. 4 to 10) Means for Solving the Problems (FIGS. 1 to 3) Embodiments of the Invention (FIGS. 1 to 3) Effect of the invention

【0002】[0002]

【発明の属する技術分野】本発明は多層配線基板の製造
方法に関し、例えばフオトビア基板及びその製造方法に
適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board, and is suitable for application to, for example, a photo via board and a method for manufacturing the same.

【0003】[0003]

【従来の技術】従来、多層配線基板(以下の例では4層
配線基板)は、図4(A)〜図5(C)に示す以下の手
順により製造されている。すなわち、まず図4(A)に
示すような、絶縁基板1の一面及び他面それぞれ銅箔2
A、2Bが張りつけられてなる両面銅張積層板3の所定
位置に、図4(B)に示すように錐を用いて貫通孔3A
を形成する。
2. Description of the Related Art Conventionally, a multilayer wiring board (a four-layer wiring board in the following example) is manufactured by the following procedure shown in FIGS. 4 (A) to 5 (C). That is, first, as shown in FIG. 4A, a copper foil 2 is formed on each of the one surface and the other surface of the insulating substrate 1.
As shown in FIG. 4B, a through hole 3A is formed at a predetermined position of the double-sided copper clad laminate 3 to which A and 2B are attached.
To form

【0004】次いでこの両面銅張積層板3の一面側及び
他面側からの銅めつき処理によつて、図4(C)のよう
に貫通孔3Aの内面にめつき層4Aを形成することによ
りスルーホール4AXを形成し、かくして当該両面銅張
積層板3の一面側及び他面側の各銅箔2A、2B間を電
気的に接続する。なおこのとき両面銅張積層板3の一面
側及び他面側の各銅箔2A、2B上にもそれぞれ銅めつ
き層4B、4Cが形成される。
Next, a plating layer 4A is formed on the inner surface of the through hole 3A as shown in FIG. 4C by a copper plating process from one side and the other side of the double-sided copper-clad laminate 3. Thus, the through hole 4AX is formed, thus electrically connecting the copper foils 2A and 2B on one side and the other side of the double-sided copper-clad laminate 3 to each other. At this time, copper plating layers 4B and 4C are also formed on the copper foils 2A and 2B on the one surface side and the other surface side of the double-sided copper-clad laminate 3, respectively.

【0005】次いで図4(D)に示すように、この両面
銅張積層板3の一面側の銅箔2A及び銅めつき層4Bで
なる2層目の導体層5と、両面銅張積層板3の他面側の
銅箔2B及び銅めつき層4Cでなる3層目の導体層6と
をそれぞれパターニングすることにより2層目及び3層
目の配線パターンを形成し、この後図4(E)に示すよ
うに、この両面銅張積層板3の一面側及び他面側に接着
層の役割を果たすプリプレグ7A、7Bを挟んで片面銅
張積層板8、9をそれぞれ張り付けることにより4層基
板10を形成する。
Then, as shown in FIG. 4 (D), the double-sided copper-clad laminate 3 has a second conductor layer 5 consisting of the copper foil 2A and the copper plating layer 4B on one side of the double-sided copper-clad laminate 3, and the double-sided copper-clad laminate. The second and third wiring patterns are formed by respectively patterning the copper foil 2B on the other surface side of the third wiring layer 3 and the third conductor layer 6 formed of the copper plating layer 4C, and thereafter, as shown in FIG. As shown in E), the single-sided copper-clad laminates 8 and 9 are attached to one side and the other side of the double-sided copper-clad laminate 3 with the prepregs 7A and 7B serving as an adhesive layer sandwiched between them. The layer substrate 10 is formed.

【0006】次いでこの4層基板10の所定位置に錐を
用いて図5(A)のように当該4層基板10を貫通する
貫通孔10Aを穿設した後、4層基板10の一面側及び
他面側からきめつき処理によつて、図5(B)に示すよ
うに、貫通孔10Aの内面にめつき層11Aを形成する
ことにより貫通スールホール11AXを形成し、かくし
て4層基板10の一面及び他面側の各銅箔12、13間
を電気的に接続する。なおこのときこれら各銅箔12、
13上にもそれぞれ銅めつき層11B、11Cが積層形
成される。
Next, as shown in FIG. 5 (A), a through hole 10A penetrating the four-layer substrate 10 is formed by using a cone at a predetermined position of the four-layer substrate 10, and then one surface side of the four-layer substrate 10 and As shown in FIG. 5 (B), the through-hole hole 11AX is formed by forming the plating layer 11A on the inner surface of the through-hole 10A by the texture treatment from the other surface side, and thus the four-layer substrate 10 is formed. The copper foils 12 and 13 on the one surface and the other surface are electrically connected to each other. At this time, each of these copper foils 12,
Copper plating layers 11B and 11C are also laminated on 13 respectively.

【0007】続いて図5(C)に示すように、この4層
基板10の一面側の銅箔12及び銅めつき層11Bでな
る1層目の導体層14と、4層基板10の他面側の銅箔
13及び銅めつき層11Cでなる4層目の導体層15と
をそれぞれ写真法を用いたエツチングによつてパターニ
ングすることにより、これら1層目及び4層目の各導体
層14、15にそれぞれ配線パターンを形成する。これ
により1〜4層目の各導体層14、5、6、15にそれ
ぞれ所望の配線パターンが形成されてなる4層配線基板
16を得ることができる。
Subsequently, as shown in FIG. 5C, the first conductor layer 14 composed of the copper foil 12 and the copper plating layer 11B on one side of the four-layer board 10 and the other four-layer board 10 are formed. Each of the first and fourth conductor layers is formed by patterning the copper foil 13 on the surface side and the fourth conductor layer 15 including the copper plating layer 11C by etching using a photographic method. Wiring patterns are formed on 14 and 15, respectively. This makes it possible to obtain a four-layer wiring board 16 in which desired wiring patterns are formed on the first to fourth conductor layers 14, 5, 6, and 15, respectively.

【0008】なお、図6(A)〜図7(D)に配線パタ
ーン形成法の1つであるテンテイング法を示す。この方
法では、まず図6(A)に示すように、絶縁基板20の
一面及び他面にそれぞれ銅箔21A、21Bが張りつけ
られてなる両面銅張積層板を所定形状に切断した後、か
くして得られる両面銅張積層板22の所定位置に錐を用
いて図6(B)のように貫通孔22Aを穿設する。
A tenting method, which is one of the wiring pattern forming methods, is shown in FIGS. In this method, first, as shown in FIG. 6 (A), a double-sided copper-clad laminate in which copper foils 21A and 21B are attached to one surface and the other surface of the insulating substrate 20 is cut into a predetermined shape, and thus obtained. A through hole 22A is formed at a predetermined position of the double-sided copper-clad laminate 22 by using a cone as shown in FIG. 6 (B).

【0009】次いでこの両面銅張積層板22の一面側及
び他面側からの無電解めつき処理によつて、図6(C)
のように貫通孔22Aの内面にめつき層23Aを形成
し、かくして両面銅張積層板22の一面側及び他面側の
各銅箔21A、21B間を電気的に接続する。なおこの
ときこれら各銅箔21A、21B上にもそれぞれ第1の
銅めつき層23B、23Cが積層形成される。
Next, the electroless plating treatment from one side and the other side of the double-sided copper-clad laminate 22 is performed as shown in FIG.
As described above, the plating layer 23A is formed on the inner surface of the through hole 22A, thus electrically connecting the copper foils 21A and 21B on one surface side and the other surface side of the double-sided copper-clad laminate 22 to each other. At this time, the first copper plating layers 23B and 23C are laminated on the copper foils 21A and 21B, respectively.

【0010】次いでこの両面銅張積層板22に今度は電
解めつきを施すことにより、図6(D)のように両面銅
張積層板22の一面及び他面側の各第1の銅めつき層2
3B、23C上と、めつき層23A上とにそれぞれ第2
の銅めつき層24B、24C又はめつき層24Aとを積
層形成し、この後図6(E)に示すように、当該両面銅
張積層板22の一面側及び他面側にそれぞれ第2の銅め
つき層24B、24Cを覆うようにフオトレジストの1
種であるドライフイルム25A、25Bを圧着する。
Next, electrolytic plating is applied to the double-sided copper-clad laminate 22 this time, so that the first copper-plating on one side and the other side of the double-sided copper-clad laminate 22 as shown in FIG. 6D. Layer 2
2B on 3B and 23C and on the plating layer 23A, respectively.
The copper plating layers 24B and 24C or the plating layer 24A are laminated and formed, and thereafter, as shown in FIG. 1 of photoresist so as to cover the copper plating layers 24B and 24C.
The seed dry film 25A, 25B is pressure bonded.

【0011】続いて図7(A)に示すように、これら各
ドライフイルム25A、25Bをそれぞれ所望する配線
パターンに応じて露光し、現像することにより各ドライ
フイルム25A、25Bをパターニングし、この後図7
(B)に示すように、残存するドライフイルム25A、
25Bをマスクとして両面銅張積層板22の一面側の銅
箔21A、第1の銅めつき層23B及び第2の銅めつき
層24Bでなる第1の導体層26と、両面銅張積層板2
2の他面側の銅箔21B、第1の銅めつき層23C及び
第2の銅めつき層24Cでなる第2の導体層27とをそ
れぞれエツチングによりパターニングする。
Subsequently, as shown in FIG. 7A, each of the dry films 25A and 25B is exposed in accordance with a desired wiring pattern and developed to pattern each of the dry films 25A and 25B. Figure 7
As shown in (B), the remaining dry film 25A,
Using 25B as a mask, the copper foil 21A on one side of the double-sided copper-clad laminate 22, the first conductor layer 26 including the first copper-plated layer 23B and the second copper-plated layer 24B, and the double-sided copper-clad laminate Two
The copper foil 21B on the other side of the second surface, the second conductor layer 27 composed of the first copper-plated layer 23C and the second copper-plated layer 24C are patterned by etching.

【0012】さらにこの後図7(C)に示すように、こ
の両面銅張積層板22の一面側及び他面側からそれぞれ
ドライフイルム25A、25Bを剥離した後、図7
(D)に示すように、この両面銅張積層板22の一面側
及び他面側にそれぞれソルダーレジスト28A、28B
を塗布し、表面処理を施し、外形加工を施す。これによ
り両面銅張積層板22の一面側及び他面側にそれぞれ所
望の配線パターンを形成することができる。
Further, as shown in FIG. 7C, after the dry films 25A and 25B are peeled off from one side and the other side of the double-sided copper-clad laminate 22, respectively, as shown in FIG.
As shown in (D), solder resists 28A and 28B are formed on one side and the other side of the double-sided copper-clad laminate 22, respectively.
Is applied, surface treatment is performed, and outer shape processing is performed. As a result, desired wiring patterns can be formed on one surface side and the other surface side of the double-sided copper-clad laminate 22, respectively.

【0013】ところで、図4(A)〜図5(C)につい
て上述した積層による多層配線基板の製造方法(以下、
これを積層法と呼ぶ)は一般的であるが、この方法では
銅張積層板3、8、9の銅箔2A、2B、12、13の
厚み(18〔μm 〕)に加え、貫通スルーホール11AX
を形成するためのめつき処理により銅材が約20〔μm〕
も積み上げられるため、1〜4層目の各導体層14、
5、6、15の各銅厚が40〔μm 〕近くにもなる。
By the way, a method of manufacturing a multilayer wiring board by stacking described above with reference to FIGS.
This is called a lamination method), but in this method, in addition to the thickness (18 [μm]) of the copper foils 2A, 2B, 12 and 13 of the copper clad laminates 3, 8 and 9, through through holes are used. 11AX
About 20 [μm] of copper material due to plating treatment to form
, The conductor layers 14 of the first to fourth layers,
The copper thicknesses of 5, 6, and 15 are close to 40 [μm].

【0014】ところが、一般的に銅張積層板3、8、9
をエツチングによりパターニングする工程では、銅厚が
厚いほどエツチングのための時間を必要とし、さらにそ
の分横方向からのエツチング液のしみ込みによつてパタ
ーンが必要以上にエツチングされる(オーバーエツチン
グ)ことがあるため、各導体層14、5、6、15の配
線パターンが所望する太さよりも細くなる問題がある。
このため上述のような積層法では、微細パターンの形成
が困難とされていた。
However, in general, the copper clad laminates 3, 8, 9
In the process of patterning by etching, the thicker the copper is, the longer the etching time is required, and the etching liquid is soaked from the lateral direction, and the pattern is etched more than necessary (over-etching). Therefore, there is a problem that the wiring pattern of each conductor layer 14, 5, 6, 15 becomes thinner than a desired thickness.
Therefore, it has been difficult to form a fine pattern by the above-described lamination method.

【0015】また上述のような積層法では、貫通スルー
ホール11AXを含む全てのスルーホール4AX、11
AXの形成をすべて錐を用いて行つているため、当該ス
ルーホール4AX、11AXの孔径が錐の径に依存す
る。ところが現在では、錐の強度の問題から小径でも直
径0.3 〔mm〕の錐を用いる必要があるために、形成され
た多層配線基板16の最上及び最下の導体層(4層配線
基板では1層目及び4層目の各導体層14、15)にお
ける貫通スルーホール11AXのランド径が大きくな
り、この結果配線効率が低下する問題があつた。
Further, in the laminating method as described above, all the through holes 4AX, 11 including the through through hole 11AX.
Since the AX is formed entirely by using the cone, the hole diameters of the through holes 4AX and 11AX depend on the diameter of the cone. However, at present, since it is necessary to use a cone having a diameter of 0.3 [mm] even if it has a small diameter due to the problem of the strength of the cone, the uppermost and lowermost conductor layers (one layer in a four-layer wiring board) of the formed multilayer wiring board 16 are used. There is a problem that the land diameter of the through-holes 11AX in the first and fourth conductor layers 14 and 15) becomes large, resulting in a decrease in wiring efficiency.

【0016】さらに上述のような積層法では、両面銅張
積層板22の両面側にそれぞれ片面銅張積層板8、9を
張りつけた後に貫通スルーホール11AXを形成するた
めの穴あけ作業を行うようにしているため、両面銅張積
層板22と各片面銅張積層板8、9との位置合わせ精度
に加えて、ドリル加工工程での4層基板10に対する錐
の位置合わせ精度も必要となり、さらにこの位置決め精
度に合わせて貫通スルーホール11AXのランド径が決
定するため、最外の導体層のランド径が半径0.6 〔mm〕
と大きくなることにより配線効率がさらに悪化する問題
があつた。
Further, in the laminating method as described above, after the single-sided copper-clad laminates 8 and 9 are attached to both sides of the double-sided copper-clad laminate 22, the perforating work for forming the through through holes 11AX is performed. Therefore, in addition to the alignment accuracy between the double-sided copper-clad laminate 22 and each of the single-sided copper-clad laminates 8 and 9, the cone alignment accuracy with respect to the four-layer board 10 in the drilling process is also necessary. Since the land diameter of the through-hole 11AX is determined according to the positioning accuracy, the land diameter of the outermost conductor layer has a radius of 0.6 [mm].
However, there is a problem that the wiring efficiency further deteriorates due to the increase in the size.

【0017】これに対して従来、高密度実装に対応し得
るフオトビア基板と呼ばれる基板がある(なお以下では
フオトビア基板として4層フオトビア基板について説明
する)。通常、この種の基板においては、例えば図8
(A)〜図10(C)に示す以下の手順により製造され
ている。
On the other hand, conventionally, there is a substrate called a photo via substrate that can be used for high-density mounting (hereinafter, a 4-layer photo via substrate will be described as a photo via substrate). Usually, in this type of substrate, for example, FIG.
It is manufactured by the following procedure shown in (A) to FIG. 10 (C).

【0018】すなわちまず図8(A)のように絶縁基板
30の一面及び他面にそれぞれ銅箔32A、32Bが張
りつけられてなる両面銅張積層板32の所定位置に、図
8(B)のように錐により貫通孔32Aを穿設した後、
図8(C)に示すように、この両面銅張積層板32の一
面側及び他面側からの銅めつき処理によつて貫通孔32
Aの内面にめつき層33Aを形成することによりスルー
ホール33AXを形成し、かくして各銅箔31A、31
B間を電気的に接続する。なおこのときこれら各銅箔3
1A、31B上にもそれぞれ銅めつき層33B、33C
が形成される。
That is, first, as shown in FIG. 8A, the double-sided copper-clad laminate 32 in which copper foils 32A and 32B are adhered to one surface and the other surface of the insulating substrate 30, respectively, is placed at a predetermined position in FIG. After forming the through hole 32A with a cone like this,
As shown in FIG. 8C, the through holes 32 are formed by the copper plating treatment from one side and the other side of the double-sided copper-clad laminate 32.
The through hole 33AX is formed by forming the plating layer 33A on the inner surface of A, and thus each copper foil 31A, 31
Electrically connect between B. At this time, each of these copper foils 3
Copper plating layers 33B and 33C on 1A and 31B, respectively
Is formed.

【0019】次いで図8(D)に示すように、この両面
銅張積層板32の一面側の銅箔31A及び銅めつき層3
3Bでなる2層目の導体層34と、両面銅張積層板32
の他面側の銅箔31B及び銅めつき層33Cでなる3層
目の導体層35とをそれぞれパターニングすることによ
り2層目及び3層目の配線パターンを形成する。
Then, as shown in FIG. 8D, the copper foil 31A and the copper plating layer 3 on one surface of the double-sided copper-clad laminate 32 are formed.
3B second conductor layer 34 and double-sided copper clad laminate 32
The second-layer and third-layer wiring patterns are formed by respectively patterning the copper foil 31B on the other surface side and the third-layer conductor layer 35 formed of the copper plating layer 33C.

【0020】次いで図8(E)に示すように、この両面
銅張積層板32の一面側にフオトレジトスを塗布するこ
とによりレジスト層36を形成すると共に、この後図9
(A)に示すように、このレジスト層36を両面銅張積
層板32の同じ面側からマスク35を介して露光し、現
像することにより、図9(B)のようにレジスト層36
の所定位置に1層目の導体層と2層目の導体層34との
間の導通をとるためのビアホール36Aを形成する。
Next, as shown in FIG. 8 (E), a resist layer 36 is formed by applying photo resistitos to one surface of the double-sided copper-clad laminate 32, and thereafter, as shown in FIG.
As shown in FIG. 9A, the resist layer 36 is exposed from the same surface side of the double-sided copper clad laminate 32 through the mask 35 and developed to develop the resist layer 36 as shown in FIG. 9B.
A via hole 36A for establishing electrical connection between the first conductor layer and the second conductor layer 34 is formed at a predetermined position.

【0021】続いてこの両面銅張積層板32の他面側に
フオトレジストを塗布することによりレジスト層38を
形成すると共に、この後図9(C)に示すように、この
レジスト層38を両面銅張積層板32の同じ面側からマ
スク39を介して露光し、現像することにより、図9
(D)に示すように、レジスト層38の所定位置に3層
目の導体層35と4層目の導体層との間の導通をとるた
めのビアホール38Aを形成する。
Subsequently, a photoresist is applied to the other surface of the double-sided copper-clad laminate 32 to form a resist layer 38. Thereafter, as shown in FIG. 9C, the resist layer 38 is formed on both sides. By exposing and developing from the same surface side of the copper clad laminate 32 through the mask 39, as shown in FIG.
As shown in (D), a via hole 38A for establishing electrical connection between the third conductor layer 35 and the fourth conductor layer is formed at a predetermined position of the resist layer 38.

【0022】さらに図10(A)に示すように、この両
面銅張積層板32の所定位置に錐を用いて貫通スルーホ
ール用の貫通孔32Bを穿設し、この後図10(B)に
示すように、この両面銅張積層板32の一面側及び他面
側からの銅めつき処理により、各レジスト層36、38
上それぞれ1層目又は4層目の導体層40、41をそれ
ぞれ形成すると共に貫通孔32Bの内面にめつき層42
を形成することにより貫通スルーホール42Aを形成
し、かくして1層目及び4層目の各導体層40、41間
を導通接続する。
Further, as shown in FIG. 10A, a through hole 32B for a through through hole is formed at a predetermined position of the double-sided copper-clad laminate 32 by using a cone, and then, as shown in FIG. As shown, the resist layers 36 and 38 are subjected to the copper plating treatment from one side and the other side of the double-sided copper-clad laminate 32.
The first or fourth conductor layers 40 and 41 are respectively formed on the upper side, and the plating layer 42 is formed on the inner surface of the through hole 32B.
To form the through-hole 42A, and thus the first and fourth conductor layers 40 and 41 are electrically connected.

【0023】さらにこの後図10(C)に示すように、
かくして形成された4層基板43の1層目及び4層目の
各導体層40、41をそれぞれ所望パターンにパターニ
ングする。これにより1層目〜4層目の各導体層40、
34、35、41がそれぞれ所望パターンにパターニン
グされてなる4層のフオトビア基板44を得ることがで
きる。
Further after this, as shown in FIG.
The conductor layers 40 and 41 of the first and fourth layers of the four-layer substrate 43 thus formed are patterned into desired patterns. As a result, the first to fourth conductor layers 40,
It is possible to obtain a four-layer photovia substrate 44 in which 34, 35, and 41 are patterned into desired patterns.

【0024】このようにして形成されたフオトビア基板
44は、通常、隣合う導体層間(1層目及び2層目の各
導体層40、34間、3層目及び4層目の各導体層3
5、41間)の電気的接続をとるための各フオトビア3
6A、38Aが上述のように写真法を用いて形成される
ために直径0.2 〔mm〕程度とかなり小径であり、また最
上及び最下の各導体層(1層目及び4層目の各導体層4
0、41)の銅厚がめつき処理1回分の約20〔μm 〕し
かないため、微細パターン形成に適していると言うこと
ができる。
The photo-via substrate 44 thus formed is usually provided between adjacent conductor layers (between the first and second conductor layers 40 and 34, the third and fourth conductor layers 3).
Photovoltaic 3 for electrical connection (between 5 and 41)
Since 6A and 38A are formed by the photographic method as described above, the diameter is considerably small, about 0.2 [mm], and the uppermost and lowermost conductor layers (each conductor of the first and fourth layers). Layer 4
Since the copper thickness of 0, 41) is about 20 [μm] for one plating treatment, it can be said that it is suitable for forming a fine pattern.

【0025】[0025]

【発明が解決しようとする課題】ところがこの種のフオ
トビア基板44においては、貫通スルーホール42Aの
もととなる貫通孔32Bを上述のようにドリル加工によ
り行つているため、図4(A)〜図5(C)において上
述した積層による多層配線基板の製造方法と同様に貫通
スールホール42Aのランド径を小さくすることが難し
く、この結果当該貫通スールホール42Aのランド周囲
に配線できないことにより配線効率が低下する問題があ
つた。
However, in the photo-via substrate 44 of this type, since the through hole 32B, which is the source of the through hole 42A, is formed by the drilling process as described above, the structure shown in FIG. It is difficult to reduce the land diameter of the through-through hole 42A as in the method of manufacturing a multilayer wiring substrate by stacking described above in FIG. 5C, and as a result, wiring cannot be performed around the land of the through-hole hole 42A, resulting in wiring efficiency. There was a problem of decrease.

【0026】またこのドリル加工工程においては、最上
層及び内層の各導体層(1層目及び2層目の各導体層4
0、34)間、最下層及び内層の各導体層(3層目及び
4層目の各導体層35、41)間において位置合わせ精
度が必要となるが、実際上この工程では、錐の位置を固
定したままワークサイズが600 〔mm〕四方の両面銅張積
層板32を動かして穴開けを行つているために高精度な
位置決めが困難な問題があつた。
Further, in this drilling process, the uppermost conductor layer and the inner conductor layers (first conductor layer 4 and second conductor layer 4) are formed.
0, 34), and between the bottom and inner conductor layers (third and fourth conductor layers 35, 41), alignment accuracy is required. There was a problem that it was difficult to perform high-precision positioning because the double-sided copper-clad laminate 32 with a work size of 600 [mm] was moved while the workpiece was fixed to make holes.

【0027】さらにこの種のフオトビア基板44におい
ては、錐(ドリル)径に加えてこの位置決め精度を含ん
でいるため、最上及び最下の各導体層(1層目及び4層
目の各導体層40、41)における貫通スルーホール4
2Aのランド径が大きくなり、またドリル加工工程が2
回に分かれているためにタクトタイムがかかる問題があ
つた。
Further, in this type of photo-via substrate 44, since this positioning accuracy is included in addition to the diameter of the cone (drill), the uppermost and lowermost conductor layers (first conductor layer and fourth conductor layer). Through-hole 4 in 40, 41)
The land diameter of 2A is large, and the drilling process is 2
There was a problem that it took tact time because it was divided into times.

【0028】本発明は以上の点を考慮してなされたもの
で、高密度実装に十分に対応し得る多層配線基板の製造
方法を提案しようとするものである。
The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a method for manufacturing a multilayer wiring board which can sufficiently cope with high-density mounting.

【0029】[0029]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、一面及び又は他面に導電材でなる
導体層が積層されたベース基板の貫通スルーホール形成
位置に貫通孔を穿設すると共に、ベース基板の導体層を
パターニングする第1の工程と、ベース基板の導体層上
にフオトレジストでなるレジスト層を積層する第2の工
程と、レジスト層を所定パターンに露光し、現像するこ
とによりベース基板の貫通孔と連通するようにレジスト
層にビアホールを形成する第3の工程とを設けるように
した。
In order to solve the above problems, according to the present invention, a through hole is formed at a position where a through hole is formed in a base substrate on which a conductor layer made of a conductive material is laminated on one surface and / or the other surface. At the same time, the first step of patterning the conductor layer of the base substrate, the second step of laminating a resist layer made of photoresist on the conductor layer of the base substrate, and the resist layer is exposed to a predetermined pattern and developed. Thus, a third step of forming a via hole in the resist layer so as to communicate with the through hole of the base substrate is provided.

【0030】このようにした場合、例えばこの後レジス
ト層上にビアホールを避けて導体層を形成した後、この
導体層をパターニングし、さらにこの後第2の工程以降
を同様に繰り返すことにより、容易に貫通スルーホール
を形成することができる。この場合形成された多層配線
基板においては、貫通スルーホールを形成するためにベ
ース基板に貫通孔を形成する工程が導体層上にレジスト
層が順次積層された後ではなくその前に行われるため、
ドリル加工工程を複数回行う必要がなく、また貫通スル
ーホール用のドリル加工を最終的な多層配線基板に対す
るドリル加工に比べて径の小さな錐を用いて行うことが
できるため、その分多層配線基板の最外の導体層におけ
る貫通スルーホールのランド径を小さくすることができ
る。
In this case, for example, after the conductor layer is formed on the resist layer while avoiding the via hole, the conductor layer is patterned, and then the second and subsequent steps are repeated in the same manner. It is possible to form a through-hole therethrough. In the multilayer wiring board formed in this case, since the step of forming the through hole in the base substrate to form the through through hole is performed not after the resist layer is sequentially laminated on the conductor layer, but before that.
It is not necessary to perform the drilling process multiple times, and the drilling for through-holes can be performed using a cone with a smaller diameter than the drilling for the final multilayer wiring board. The land diameter of the through hole in the outermost conductor layer can be reduced.

【0031】[0031]

【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0032】図1(A)〜図3(B)は、実施例による
多層配線基板(4層配線基板)の製造手順を示すもので
あり、まず図1(A)に示すような絶縁基板50の一面
及び他面にそれぞれ銅箔51A、51Bが張り付けられ
てなる両面銅張積層板52の内層スルーホール形成位置
及び貫通スルーホール形成位置に、それぞれ図1(B)
に示すように、錐により第1、第2の貫通孔52A、5
2Bをそれぞれ穿設する。
FIGS. 1A to 3B show a manufacturing procedure of a multilayer wiring board (four-layer wiring board) according to an embodiment. First, an insulating substrate 50 as shown in FIG. 1 (B) at the inner layer through-hole forming position and the through-hole forming position of the double-sided copper-clad laminate 52 in which copper foils 51A and 51B are adhered to one surface and the other surface, respectively.
, The first and second through holes 52A, 5
Drill 2B respectively.

【0033】次いで図1(C)に示すように、この両面
銅張積層板52の一面側及び他面側からのめつき処理に
よつて第1及び第2の貫通孔52A、52Bの各内面に
それぞれめつき層53A、53Bを形成することにより
第1及び第2のスルホール53AX、53BXを形成
し、かくして両面銅張積層板52の各銅箔51A、51
B間の電気的接続をとる。なおこのときこれら各銅箔5
1A、51B上にもそれぞれ銅めつき層54A、54B
が形成される。
Then, as shown in FIG. 1C, the inner surfaces of the first and second through holes 52A and 52B are subjected to the plating treatment from one side and the other side of the double-sided copper-clad laminate 52. The first and second through holes 53AX and 53BX are formed by forming the plating layers 53A and 53B respectively on the copper foils 51A and 51A of the double-sided copper clad laminate 52.
Make electrical connection between B. At this time, each of these copper foils 5
Copper plated layers 54A and 54B on 1A and 51B, respectively
Is formed.

【0034】次いでこの両面銅張積層板52の一面側の
銅箔51A及び銅めつき層54Aでなる2層目の導体層
55と、両面銅張積層板52の他面側の銅箔51B及び
銅めつき層54Bでなる3層目の導体層56とをそれぞ
れ図1(D)のようにパターニングすることにより所望
の配線パターンを形成する。
Next, the second conductor layer 55 consisting of the copper foil 51A and the copper plating layer 54A on one side of the double-sided copper-clad laminate 52, the copper foil 51B on the other side of the double-sided copper-clad laminate 52, and A desired wiring pattern is formed by patterning each of the third conductor layer 56 formed of the copper plating layer 54B as shown in FIG. 1D.

【0035】続いて図1(E)に示すように、この両面
銅張積層板52の一面側にフオトレジストを塗布するこ
とによりレジスト層57を形成すると共に、この後図2
(A)に示すように、このレジスト層57上に、1層目
の導体層と2層目の導体層55との間の導通をとるため
のビアホールの形成位置にそれぞれ対応させて開口58
Aが穿設された第1のマスク58を位置決めして載置し
た後、この第1のマスク58を介してレジスト層57を
両面銅張積層板52の同じ面側から露光する。
Subsequently, as shown in FIG. 1E, a resist layer 57 is formed by applying a photoresist to one surface of the double-sided copper-clad laminate 52, and thereafter, as shown in FIG.
As shown in (A), openings 58 are formed on the resist layer 57 at positions corresponding to via holes for establishing electrical connection between the first conductor layer and the second conductor layer 55.
After positioning and placing the first mask 58 having A formed therein, the resist layer 57 is exposed from the same surface side of the double-sided copper-clad laminate 52 through the first mask 58.

【0036】またこのとき両面銅張積層板52の他面側
にも当該両面銅張積層板52の第2のスルーホール53
BXとそれぞれ対応させて開口59Aが穿設されてなる
第2のマスク59を位置決めして当接させた後、この第
2のマスク59及び第2のスルーホール53BXを順次
介してレジスト層57を両面銅張積層板52の異なる面
側から露光する。
At this time, the second through hole 53 of the double-sided copper-clad laminate 52 is also provided on the other side of the double-sided copper-clad laminate 52.
After positioning and abutting a second mask 59 having an opening 59A corresponding to each BX, the resist layer 57 is formed through the second mask 59 and the second through hole 53BX sequentially. Exposure is performed from the different surface side of the double-sided copper clad laminate 52.

【0037】さらにこの後このレジスト層57を現像す
ることにより、図2(B)のようにレジスト層57の所
定位置に1層目の導体層及び2層目の導体層55間の電
気的接続をとるための第1のビアホール57Aを形成す
ると共に、第2のスルーホール53BXの真上に当該第
2のスルーホール53BXと連通する第2のビアホール
57Bを形成する。
After that, the resist layer 57 is further developed to electrically connect the first conductor layer 55 and the second conductor layer 55 at predetermined positions of the resist layer 57 as shown in FIG. A first via hole 57A for forming the second through hole 53BX is formed immediately above the second through hole 53BX, and a second via hole 57B communicating with the second through hole 53BX is formed immediately above the second through hole 53BX.

【0038】次いで今度はこの両面銅張積層板52の他
面側にフオトレジストを塗布することによりレジスト層
60を形成すると共に(図2(B))、この後図2
(C)に示すように、このレジスト層60上に、3層目
の導体層56と4層目の導体層との間の導通をとるため
のビアホールの形成位置にそれぞれ対応させて開口61
Aが穿設された第3のマスク61を位置決めして載置し
た後、この第1のマスク61を介してレジスト層60を
両面銅張積層板52の同じ面側から露光する。
Next, a photoresist layer 60 is formed by applying a photoresist to the other surface of the double-sided copper-clad laminate 52 (FIG. 2 (B)).
As shown in (C), openings 61 are formed on the resist layer 60 in correspondence with the positions of via holes for establishing conduction between the third conductor layer 56 and the fourth conductor layer.
After positioning and placing the third mask 61 having A formed therein, the resist layer 60 is exposed from the same side of the double-sided copper-clad laminate 52 through the first mask 61.

【0039】またこのとき両面銅張積層板52の一面側
にも当該両面銅張積層板52の第2のスルーホール53
BXとそれぞれ対応させて開口61Aが穿設されてなる
第4のマスク61を位置決めして当接させた後、この第
2のマスク61及び第2のスルーホール53BXを順次
介してレジスト層60を両面銅張積層板52の異なる面
側から露光する。
At this time, the second through hole 53 of the double-sided copper-clad laminate 52 is also provided on one side of the double-sided copper-clad laminate 52.
After positioning and abutting a fourth mask 61 having an opening 61A corresponding to each BX, the resist layer 60 is formed through the second mask 61 and the second through hole 53BX sequentially. Exposure is performed from the different surface side of the double-sided copper clad laminate 52.

【0040】さらにこの後このレジスト層60を現像す
ることにより、図2(D)に示すように、レジスト層6
0の所定位置に3層目の導体層56及び4層目の導体層
間の電気的接続をとるための第1のビアホール60Aを
形成すると共に、第2のスルーホール53BXの真上に
当該第2のスルーホール53BXと連通する第2のビア
ホール60Bを形成する。
After that, the resist layer 60 is further developed, so that the resist layer 6 is formed as shown in FIG.
A first via hole 60A for establishing electrical connection between the third conductor layer 56 and the fourth conductor layer is formed at a predetermined position of 0, and the second via hole 53BX is provided directly above the second through hole 53BX. A second via hole 60B communicating with the through hole 53BX is formed.

【0041】この結果、かくして形成される多層板63
に、レジスト層57の第2のビアホール57Bと、両面
銅張積層板52の第2のスルーホール53BXと、レジ
スト層60の第2のビアホール60Bとからなる貫通孔
63Aが形成される。
As a result, the multilayer plate 63 thus formed
Then, a through hole 63A including the second via hole 57B of the resist layer 57, the second through hole 53BX of the double-sided copper clad laminate 52, and the second via hole 60B of the resist layer 60 is formed.

【0042】次いで図3(A)に示すように、この多層
板63の一面側及び他面側からの銅めつき処理により当
該多層板63の一面側に1層目の導体層64を形成する
と共に、当該多層板63の他面側に4層目の導体層65
を形成する。
Next, as shown in FIG. 3A, a first conductor layer 64 is formed on one surface side of the multilayer board 63 by copper plating treatment from one surface side and the other surface side of the multilayer board 63. At the same time, the fourth conductor layer 65 is formed on the other surface side of the multilayer board 63.
To form

【0043】なおこのとき多層板63の貫通63A内に
も銅材を堆積させることにより、1層目及び4層目の各
導体層64、65を電気的に接続する貫通スルーホール
66を形成する。
At this time, a copper material is also deposited in the through holes 63A of the multi-layer plate 63 to form through through holes 66 for electrically connecting the first and fourth conductor layers 64, 65. .

【0044】さらにこの後図3(B)に示すように、こ
の多層板63の一面側及び他面側にそれぞれ形成された
1層目及び4層目の各導体層64、65をそれぞれ所望
パターンにパターニングする。これにより所望パターン
の導体層64、55、56、65が積層されてなる多層
配線基板67を得ることができる。
After this, as shown in FIG. 3B, the conductor layers 64 and 65 of the first and fourth layers formed on the one surface side and the other surface side of the multilayer board 63 are respectively formed into desired patterns. Pattern. As a result, it is possible to obtain the multilayer wiring board 67 in which the conductor layers 64, 55, 56 and 65 having desired patterns are laminated.

【0045】以上の構成において、この多層配線基板の
製造方法では、両面銅張積層板52の貫通スルーホール
形成位置に貫通孔52Bを穿設し(図1(B))、当該
貫通孔52Bの内面にめつき層53Bを形成することに
よりスルーホール53BXを形成する(図1(C))。
In the above structure, in the method for manufacturing a multilayer wiring board, the through-hole 52B is formed at the position where the through-hole is formed in the double-sided copper clad laminate 52 (FIG. 1 (B)), and the through-hole 52B is formed. The through hole 53BX is formed by forming the plating layer 53B on the inner surface (FIG. 1C).

【0046】次いで両面銅張積層板52の一面側及び他
面側に順次形成されるレジスト層57、60をこのスル
ーホール53BXを介してそれぞれ他面側又は一面側か
ら順次露光するようにしてスルーホール53BXの真上
及び真下位置にビアホール57B、60Bをそれぞれ形
成することにより貫通孔63Aを形成する(図2(A)
〜図2(D))。
Next, the resist layers 57 and 60 sequentially formed on one surface side and the other surface side of the double-sided copper clad laminate 52 are sequentially exposed from the other surface side or the one surface side through the through holes 53BX. Through holes 63A are formed by forming via holes 57B and 60B at positions directly above and below the hole 53BX, respectively (FIG. 2A).
-FIG. 2 (D).

【0047】さらにこの後、かくして形成された多層板
63の一面側及び他面側からのめつき処理により1層目
及び4層目の導体層64、65をそれぞれ形成すると共
に、この際貫通孔63A内にも銅材を堆積させることに
より1層目及び4層目の各導体層64、65間を電気的
に接続する貫通スルーホール66を形成し(図3
(A))、この後1層目及び4層目の各導体層64、6
5をそれぞれ所望パターンにパターニングする。
Thereafter, the first and fourth conductor layers 64 and 65 are respectively formed by plating treatment from the one surface side and the other surface side of the thus formed multilayer plate 63, and at this time, through holes are formed. By depositing a copper material in 63A as well, a through-hole 66 for electrically connecting the first and fourth conductor layers 64, 65 is formed (see FIG. 3).
(A)), and thereafter the first and fourth conductor layers 64, 6
5 is patterned into a desired pattern.

【0048】従つてこの多層配線基板の製造方法によれ
ば、貫通スルーホール66を形成するために必要なドリ
ル加工処理を、内層の各導体層間(2層目及び3層目の
各導体層55、56間)を導通接続するための貫通孔5
2Aを穿設する際に一括して行うためドリル加工工程を
1回にまとめることができ、その分図4及び図5におい
て上述した積層法や、図8〜図10において上述したフ
オトビア法に比べてより容易にかつ短時間で多層配線基
板を製造することができる。
Therefore, according to this method for manufacturing a multilayer wiring board, the drilling process required to form the through-holes 66 is performed by the inner conductor layers (the second conductor layer 55 and the third conductor layer 55). , 56) for conductive connection between the through holes 5
Since the drilling process can be collectively performed at a time when 2A is drilled, compared with the laminating method described above in FIGS. 4 and 5 and the photovia method described in FIGS. 8 to 10, accordingly. Thus, the multilayer wiring board can be manufactured more easily and in a shorter time.

【0049】またこの多層配線基板の製造方法では、上
述のように全てのドリル加工を1工程で行うため、内層
及び外層の各導体層間(1層目及び2層目の各導体層6
4、55間、3層目及び4層目の各導体層56、65
間)でのドリル位置合わせを必要としない。
Further, in this method for manufacturing a multilayer wiring board, since all the drilling is performed in one step as described above, the inner conductor layers and the outer conductor layers (first conductor layer 6 and second conductor layer 6) are formed.
Between 4, 55, the third and fourth conductor layers 56, 65
Does not require drill alignment in (between).

【0050】これに加えこの多層配線基板の製造方法で
は、両面銅張積層板52に予め穿設された貫通孔52B
を利用して貫通スルーホール66を形成するようにして
いるため、例えば厚みのある多層板63(図2(D))
を穿設する場合に使用する錐に比べて径の小さい錐(例
えば直径0.2 〔mm〕程度)を用いて両面銅張積層板52
に貫通スルーホール66用の貫通孔52Bを穿設し得、
かつこの後この貫通孔52Bの内面に例えば厚み0.05
〔μm 〕程度のめつき層53Bを形成するため貫通孔6
3Aの内径をさらに小さくすることができる。
In addition to this, in this method of manufacturing a multilayer wiring board, through-holes 52B pre-drilled in the double-sided copper clad laminate 52 are formed.
Since the through through-hole 66 is formed by using, the multi-layer plate 63 having a large thickness (FIG. 2D), for example.
The double-sided copper-clad laminate 52 is formed by using a cone having a diameter smaller than that of the cone used for drilling (for example, a diameter of about 0.2 mm).
A through hole 52B for the through through hole 66 may be formed in
And after this, for example, a thickness of 0.05
The through hole 6 for forming the plating layer 53B of about [μm]
The inner diameter of 3A can be further reduced.

【0051】従つてこの多層配線基板の製造方法によれ
ば、貫通孔63Aを介した露光により各レジスト層5
7、60に形成されるフオトビア57B、60Bを直径
0.10〜0.15〔mm〕程度に抑えることができるため、貫通
スルーホール66の最外層におけるランド径を小さくす
ることができる。
Therefore, according to this method for manufacturing a multilayer wiring board, each resist layer 5 is exposed by exposure through the through hole 63A.
Diameter of photo vias 57B and 60B formed in
Since it can be suppressed to about 0.10 to 0.15 [mm], the land diameter in the outermost layer of the through through hole 66 can be reduced.

【0052】さらにこの多層配線基板の製造方法では、
両面銅張積層板52の一面側及び他面側に順次形成され
るレジスト層57、60を当該両面銅張積層板52に形
成されたスルーホール53BXを介して露光するように
してこれら各レジスト層57、60にスルーホール53
BXと連通するビアホール57B、60Bを形成するた
め、各レジスト層57、60と同じ側から露光する場合
に比べてマスク59、61の位置決め精度を粗くするこ
とができ、その分多層配線基板67の製造工程を容易に
させ得る利点もある。
Further, in this method for manufacturing a multilayer wiring board,
The resist layers 57 and 60 sequentially formed on one surface side and the other surface side of the double-sided copper-clad laminate 52 are exposed through the through holes 53BX formed in the double-sided copper-clad laminate 52, respectively. Through holes 53 in 57 and 60
Since the via holes 57B and 60B communicating with the BX are formed, the positioning accuracy of the masks 59 and 61 can be made rougher as compared with the case where exposure is performed from the same side as the resist layers 57 and 60. There is also an advantage that the manufacturing process can be facilitated.

【0053】以上の構成によれば、両面銅張積層板52
の貫通スルーホール形成位置に貫通孔52Bを穿設し、
当該貫通孔52Bの内面にめつき層53Bを形成した
後、当該両面銅張積層板52の一面側及び他面側に順次
形成されるレジスト層57、60をこの貫通孔52Bを
介してそれぞれ他面側又は一面側から順次露光するよう
にして貫通孔52Bの真上及び真下位置にビアホール5
7B、60Bをそれぞれ形成することにより貫通孔63
Aを形成し、この後かくして形成された多層板63の一
面側及び他面側からのめつき処理により1層目及び4層
目の導体層64、65をそれぞれ形成すると共に、この
際貫通孔63A内にも銅材を堆積させるようにして貫通
スルーホール66を形成するようにしたことにより、最
外の各導体層における貫通スルーホール66のランド径
を小さくすることができ、かくして高密度実装に十分に
対応し得る多層配線基板の製造方法を実現できる。
According to the above configuration, the double-sided copper clad laminate 52
A through hole 52B is formed at the through hole forming position of
After forming the plating layer 53B on the inner surface of the through hole 52B, the resist layers 57 and 60 sequentially formed on the one surface side and the other surface side of the double-sided copper clad laminate 52 are respectively separated through the through hole 52B. The via holes 5 are formed directly above and below the through holes 52B by sequentially exposing from the surface side or one surface side.
By forming 7B and 60B respectively, the through hole 63
A is formed, and then the first and fourth conductor layers 64 and 65 are respectively formed by plating treatment from the one surface side and the other surface side of the multilayer board 63 thus formed, and at the same time, through holes are formed. By forming the through-holes 66 by depositing the copper material in the 63A as well, the land diameter of the through-holes 66 in each outermost conductor layer can be reduced, and thus high-density mounting can be achieved. It is possible to realize a method for manufacturing a multilayer wiring board that can sufficiently cope with the above.

【0054】なお上述の実施例においては、本発明を導
体層64、55、56、65が4層の多層配線基板67
を製造する際に適用するようにした場合について述べた
が、本発明はこれに限らず、4層以外の多層配線基板を
製造する場合にも適用することができる。実際上本発明
を用いて4層以上の多層配線基板を形成する場合、最終
的に貫通スルーホール用の貫通孔内に銅材を堆積させ又
はスルーホールめつきを形成するまで当該貫通孔がフオ
トレジストや銅めつき等により塞がれないように、裏面
露光によりフオトビアホールが形成できるランド径にす
る必要があるが、光を通過させることができるのであれ
ば最終的に貫通スルーホール用の貫通孔内に銅材を堆積
させ又はスルーホールめつきを形成するまでの間に光透
過性物質が充填された状態にあつても良い。
In the embodiment described above, the present invention is applied to a multilayer wiring board 67 having four conductor layers 64, 55, 56 and 65.
However, the present invention is not limited to this and can also be applied to the case of manufacturing a multilayer wiring board other than four layers. In practice, when a multilayer wiring board having four or more layers is formed using the present invention, until the copper material is finally deposited in the through hole for the through through hole or the through hole is formed, the through hole is not exposed. It is necessary to make the land diameter so that a photo via hole can be formed by backside exposure so that it will not be blocked by resist or copper plating, but if the light can pass through, it will eventually penetrate the through hole. The state in which the light-transmissive substance is filled may be provided until the copper material is deposited in the holes or the through-hole plating is formed.

【0055】また上述の実施例においては、両面銅張積
層板52の一面側及び他面側に順次導体層64、55、
56、65を積層形成するようにした場合について述べ
たが、本発明はこれに限らず、片面銅張積層板の銅箔が
張りつけられた一面上に順次導体層を積層形成するよう
にしても良く、形成される多層配線基板のベースとなる
基板(これをベース基板と呼ぶ)としてはこの他種々の
ベース基板を適用できる。
Further, in the above-mentioned embodiment, the conductor layers 64, 55, are sequentially formed on one surface side and the other surface side of the double-sided copper clad laminate 52.
Although the case where the layers 56 and 65 are formed is described, the present invention is not limited to this, and the conductor layers may be sequentially formed on one surface of the single-sided copper-clad laminate having the copper foil attached thereto. Of course, various other base substrates can be applied as a substrate (this is referred to as a base substrate) which is a base of the formed multilayer wiring substrate.

【0056】さらに上述の実施例においては、両面銅張
積層板52の一面側及び他面側に形成されるレジスト層
57、60を両面銅張積層板52の異なる両側から露光
するようにしてスルーホール53BXと連通するビアホ
ール57B、60Bを形成するようにした場合について
述べたが、本発明はこれに限らず、これらレジスト層5
7、60を両面銅張積層52の同じ面側から露光してビ
アホール57B、60Bを形成するようにしても良い。
Further, in the above-described embodiment, the resist layers 57 and 60 formed on one side and the other side of the double-sided copper-clad laminate 52 are exposed through different sides of the double-sided copper-clad laminate 52. The case where the via holes 57B and 60B communicating with the hole 53BX are formed has been described, but the present invention is not limited to this, and these resist layers 5 are not limited thereto.
The via holes 57B and 60B may be formed by exposing 7 and 60 from the same surface side of the double-sided copper clad laminate 52.

【0057】[0057]

【発明の効果】上述のように本発明によれば、一面及び
又は他面に導電材でなる導体層が積層されたベース基板
の貫通スルーホール形成位置に貫通孔を穿設すると共
に、ベース基板の導体層をパターニングする第1の工程
と、ベース基板の導体層上にフオトレジストでなるレジ
スト層を積層する第2の工程と、レジスト層を所定パタ
ーンに露光し、現像することによりベース基板の貫通孔
と連通するようにレジスト層にビアホールを形成する第
3の工程とを設けるようにしたことにより、ドリル加工
工程を1度にまとめて行い得ると共に、最外の導体層に
おける貫通スルーホールのランド径を小さくすることが
でき、かくして高密度実装に十分に対応し得る多層配線
基板の製造方法を実現できる。
As described above, according to the present invention, a through hole is formed at a position where a through hole is formed in a base substrate having a conductor layer made of a conductive material laminated on one surface and / or the other surface, and the base substrate is formed. Of the base substrate, a second step of laminating a resist layer made of photoresist on the conductor layer of the base substrate, and a step of exposing the resist layer to a predetermined pattern and developing the resist layer to form a base substrate. By providing the third step of forming a via hole in the resist layer so as to communicate with the through hole, the drilling step can be performed at one time and the through hole in the outermost conductor layer can be formed. It is possible to reduce the land diameter, and thus it is possible to realize a method for manufacturing a multilayer wiring board that can sufficiently cope with high-density mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例による多層配線基板の製造手順を示す断
面図である。
FIG. 1 is a cross-sectional view showing a manufacturing procedure of a multilayer wiring board according to an embodiment.

【図2】実施例による多層配線基板の製造手順を示す断
面図である。
FIG. 2 is a cross-sectional view showing the manufacturing procedure of the multilayer wiring board according to the example.

【図3】実施例による多層配線基板の製造手順を示す断
面図である。
FIG. 3 is a cross-sectional view showing the manufacturing procedure of the multilayer wiring board according to the example.

【図4】従来の積層による多層配線基板の製造手順を示
す断面図である。
FIG. 4 is a cross-sectional view showing a conventional procedure for manufacturing a multilayer wiring board by lamination.

【図5】従来の積層による多層配線基板の製造手順を示
す断面図である。
FIG. 5 is a cross-sectional view showing a manufacturing procedure of a conventional multilayer wiring board by lamination.

【図6】テンテイング法によるパターン形成手順を示す
断面図である。
FIG. 6 is a cross-sectional view showing a pattern forming procedure by a tenting method.

【図7】テンテイング法によるパターン形成手順を示す
断面図である。
FIG. 7 is a cross-sectional view showing a pattern forming procedure by a tenting method.

【図8】従来のフオトビア基板の製造手順を示す断面図
である。
FIG. 8 is a cross-sectional view showing a procedure for manufacturing a conventional photovia substrate.

【図9】従来のフオトビア基板の製造手順を示す断面図
である。
FIG. 9 is a cross-sectional view showing a procedure for manufacturing a conventional photovia substrate.

【図10】従来のフオトビア基板の製造手順を示す断面
図である。
FIG. 10 is a cross-sectional view showing a procedure for manufacturing a conventional photovia substrate.

【符号の説明】[Explanation of symbols]

52……両面銅張積層板、52A、52B、63A……
貫通孔、53AX、53BX……スルーホール、55、
56、64、65……導体層、57、60……レジスト
層、57A、60A……ビアホール、58、59、6
1、62……マスク、63A……貫通孔、66……貫通
スルーホール、67……多層配線基板。
52: Double-sided copper clad laminate, 52A, 52B, 63A
Through hole, 53AX, 53BX ... through hole, 55,
56, 64, 65 ... Conductor layer, 57, 60 ... Resist layer, 57A, 60A ... Via hole, 58, 59, 6
1, 62 ... Mask, 63A ... Through hole, 66 ... Through hole, 67 ... Multilayer wiring board.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】一面及び又は他面に導電材でなる導体層が
積層されたベース基板の貫通スルーホール形成位置に貫
通孔を穿設すると共に、上記ベース基板の上記導体層を
パターニングする第1の工程と、 上記ベース基板の上記導体層上にフオトレジストでなる
レジスト層を積層形成する第2の工程と、 上記レジスト層を所定パターンに露光し、現像すること
により上記ベース基板の上記貫通孔と連通するように上
記レジスト層にビアホールを形成する第3の工程とを具
えることを特徴とする多層配線基板の製造方法。
1. A through hole is formed at a position where a through hole is formed in a base substrate having a conductor layer made of a conductive material laminated on one surface and / or the other surface, and the conductor layer of the base substrate is patterned. And a second step of laminating and forming a resist layer made of photoresist on the conductor layer of the base substrate, and exposing the resist layer to a predetermined pattern and developing the through hole of the base substrate. And a third step of forming a via hole in the resist layer so as to communicate with the above-mentioned resist layer.
【請求項2】上記第3の工程では、上記ベース基板の上
記貫通孔と連通する上記ビアホールを形成するための上
記レジスト層の露光を、上記ベース基板の上記レジスト
層とは異なる面側から上記ベース基板の上記貫通孔を介
して行うことを特徴とする請求項1に記載の多層配線基
板の製造方法。
2. In the third step, the exposure of the resist layer for forming the via hole communicating with the through hole of the base substrate is performed from the surface side of the base substrate different from the resist layer. The method for manufacturing a multilayer wiring board according to claim 1, wherein the method is performed through the through hole of the base substrate.
JP2318196A 1996-01-17 1996-01-17 Manufacture of multilayer interconnection board Pending JPH09199855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2318196A JPH09199855A (en) 1996-01-17 1996-01-17 Manufacture of multilayer interconnection board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2318196A JPH09199855A (en) 1996-01-17 1996-01-17 Manufacture of multilayer interconnection board

Publications (1)

Publication Number Publication Date
JPH09199855A true JPH09199855A (en) 1997-07-31

Family

ID=12103484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2318196A Pending JPH09199855A (en) 1996-01-17 1996-01-17 Manufacture of multilayer interconnection board

Country Status (1)

Country Link
JP (1) JPH09199855A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000016597A1 (en) * 1998-09-14 2000-03-23 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
JP2000216307A (en) * 1999-01-20 2000-08-04 Nec Corp Amplifying device
US6487088B2 (en) * 1997-10-17 2002-11-26 Ibiden Co., Ltd. Package substrate
KR100707818B1 (en) * 1998-09-14 2007-04-13 이비덴 가부시키가이샤 Printed wiring board and its manufacturing method

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487088B2 (en) * 1997-10-17 2002-11-26 Ibiden Co., Ltd. Package substrate
WO2000016597A1 (en) * 1998-09-14 2000-03-23 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
EP1667504A1 (en) 1998-09-14 2006-06-07 Ibiden Co., Ltd. Process for manufacturing a multilayer printed circuit board, and multilayer printed circuit board
EP1667507A1 (en) * 1998-09-14 2006-06-07 Ibiden Co., Ltd. A multilayer printed circuit board and a process for manufacturing the same
KR100707818B1 (en) * 1998-09-14 2007-04-13 이비덴 가부시키가이샤 Printed wiring board and its manufacturing method
US7230188B1 (en) 1998-09-14 2007-06-12 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
EP1923489A3 (en) * 1998-09-14 2009-05-27 Ibiden Co., Ltd. A multilayer printed circuit board and a process for manufacturing the same
US7691189B2 (en) 1998-09-14 2010-04-06 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
US7827680B2 (en) 1998-09-14 2010-11-09 Ibiden Co., Ltd. Electroplating process of electroplating an elecrically conductive sustrate
US8065794B2 (en) 1998-09-14 2011-11-29 Ibiden Co., Ltd. Printed wiring board and its manufacturing method
EP1667504B1 (en) * 1998-09-14 2012-02-01 Ibiden Co., Ltd. Process for manufacturing a multilayer printed circuit board
JP2000216307A (en) * 1999-01-20 2000-08-04 Nec Corp Amplifying device

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