CN115915649A - Multilayer circuit board and manufacturing method thereof - Google Patents
Multilayer circuit board and manufacturing method thereof Download PDFInfo
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- CN115915649A CN115915649A CN202110960839.XA CN202110960839A CN115915649A CN 115915649 A CN115915649 A CN 115915649A CN 202110960839 A CN202110960839 A CN 202110960839A CN 115915649 A CN115915649 A CN 115915649A
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Abstract
A manufacturing method of a multilayer circuit board comprises the following steps: providing a first circuit substrate, wherein the first circuit substrate comprises an insulating layer and a first conducting layer which are arranged in a stacked mode, and the first conducting layer comprises an unpatterned area; providing a first single-sided board which comprises a first base layer and a first metal layer which are arranged in a stacked mode, wherein the first single-sided board is provided with a window penetrating through the first base layer and the first metal layer; providing a second single panel comprising a second base layer and a second metal layer; laminating a first base layer of the first single panel and a second base layer of the second single panel on two opposite sides of the first circuit substrate, wherein at least one part of the unpatterned area is exposed from the window; through holes are formed in the first circuit substrate and the second single panel, penetrate through the first conducting layer and the second metal layer and are communicated with the windowing; and electroplating the through hole to form a conductive hole, wherein the conductive hole is electrically connected with the first conductive layer and the second metal layer. The application also provides a multilayer circuit board prepared by the method.
Description
Technical Field
The invention relates to the field of circuit boards, in particular to a multilayer circuit board and a manufacturing method thereof.
Background
Consumer electronic products are gradually developing towards light, thin, short and intelligent, and circuit boards (FPCs) as important components are widely used therein, and the requirements for different stacking functions of the same FPC are more and more strict. For this reason, different areas on the same FPC are designed for different traces and different numbers of layers. The multilayer circuit board is provided with a cover opening area exposing an inner layer circuit, and the manufacturing method for forming a through inner layer circuit board and an outer layer circuit board in the cover opening area generally comprises the steps of firstly providing the inner layer circuit board, then laminating two copper-clad plates on the inner layer circuit board through glue layers, opening a cover on one copper-clad plate to expose part of the inner layer circuit, and then opening through holes and electroplating on the inner layer circuit board and the outer layer circuit board in the cover opening area to form conductive holes. However, when the conductive hole is manufactured by the method, because the circuit is formed around the through hole, the current during electroplating can only go from the outer layer to the inner layer, a potential difference is formed between the inner layer and the outer layer, and the thickness of the formed copper plating layer is not uniform in the thickness direction of the circuit board, and the metal plating layer of the conductive hole has a tapered profile in the thickness direction of the circuit board.
Disclosure of Invention
In view of the above, the present invention provides a method for manufacturing a multilayer circuit board to solve the above technical problems and a multilayer circuit board manufactured by the method.
A first aspect of the present application provides a method for manufacturing a multilayer circuit board, including the steps of:
providing a first circuit substrate, wherein the first circuit substrate comprises an insulating layer and a first conducting layer which are arranged in a stacked mode, and the first conducting layer comprises a patterned area and an unpatterned area;
providing a first single-sided board, wherein the first single-sided board comprises a first base layer and a first metal layer which are arranged in a stacked mode, and a window penetrating through the first base layer and the first metal layer is formed in the first single-sided board;
providing a second single-sided board comprising a second base layer and a second metal layer;
pressing a first base layer of the first single panel and a second base layer of the second single panel on two opposite sides of the first circuit substrate, wherein at least one part of the unpatterned region of the first conductive layer is exposed from the window;
through holes are formed in the first circuit substrate and the second single-sided board, penetrate through the first conducting layer and the second metal layer and are communicated with the windowing;
and electroplating the through hole to form a conductive hole, wherein the first conductive layer and the second metal layer are electrically connected through the conductive hole.
The second aspect of the present application provides a multilayer circuit board, including first circuit substrate with set up in the second circuit substrate and the third circuit substrate of the relative both sides of first circuit substrate, second circuit substrate offers and exposes the window of the subregion of first circuit substrate, first circuit substrate with the electrically conductive hole has been seted up on the third circuit substrate, electrically conductive hole with it is linked together and electricity is connected to open the window first circuit substrate with the third circuit substrate, the pore wall of electrically conductive hole forms the metal coating, follows multilayer circuit board thickness direction, everywhere thickness is unanimous on the metal coating.
According to the manufacturing method of the multilayer circuit board, when the first conducting layer is formed in the manufacturing mode, circuit manufacturing is not carried out on the part of the first conducting layer to be exposed in the window of the second circuit substrate, so that when the conducting holes penetrating through the first circuit substrate and the third circuit substrate are formed in an electroplating mode, the metal coating with uniform thickness can be formed.
Drawings
Fig. 1 to 5 are schematic cross-sectional views illustrating a manufacturing process of a multilayer circuit board according to a first embodiment of the present application.
Description of the main elements
First conductive layer 12
Second conductive layer 13
First single panel 200
Second single panel 300
Second base layer 31
Through-hole 110
Conductive via 101
First conductive line layer 23
Second conductive line layer 33
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following embodiments, features of the embodiments may be combined with or replaced by each other without conflict.
Referring to fig. 1 to 5, a first embodiment of the present application provides a method for manufacturing a multilayer circuit board, including the following steps:
step S1, referring to fig. 1, a first circuit substrate 10 is provided, which includes an insulating layer 11, and a first conductive layer 12 and a second conductive layer 13 disposed on two opposite surfaces of the insulating layer 11.
The first conductive layer 12 includes a patterned region 122 and an unpatterned region 121, wherein a circuit is formed on the patterned region 122, and no circuit is formed on the unpatterned region 121. The position of the unpatterned region 121 corresponds to the position of the fenestration of the multilayer circuit board. In this embodiment, the unpatterned region 121 is located in the middle region of the first conductive layer 12, and the unpatterned region 121 is a complete metal plate. Other regions of the first conductive layer 12, except for the region where the unpatterned region 121 is located, are patterned regions 122.
The material of the insulating layer 11 is a dielectric material commonly used in the art, such as polyimide, epoxy resin, etc. The material of the second conductive layer 13 and the first conductive layer 12 may include, but is not limited to, copper, gold, silver, and the like.
The first circuit substrate 10 may be manufactured by the following steps: providing a substrate, wherein the substrate comprises an insulating layer 11 and metal layers arranged on two opposite surfaces of the insulating layer; carrying out circuit manufacturing on all regions of one metal layer to form a second conductive layer 13; and (4) conducting circuit manufacturing on partial area of the other metal layer to form a first conducting layer 12.
The first conductive layer 12 and the second conductive layer 13 are formed by an image transfer process and an etching process.
During the circuit fabrication, the remaining region on the other metal layer is not etched to form the unpatterned region 121.
Step S2, please refer to fig. 2, providing a first single panel 200 and a second single panel 300, and respectively pressing the first single panel 200 and the second single panel 300 on the first conductive layer 12 and the second conductive layer 13.
The first single panel 200 includes a first base layer 21 and a first metal layer 22 which are stacked. The first single panel 200 is provided with a window 201, and the window 201 penetrates through the first base layer 21 and the first metal layer 22. The size of the window 201 is smaller than or equal to the size of the unpatterned region 121, so that at least a portion of the unpatterned region 121 can be exposed from the window 201, and the patterned region 122 with the circuit on the first conductive layer 12 cannot be exposed from the window.
In this embodiment, the window 201 is opened in advance on the first single panel 200. Before bonding, the first single board 200 and the first circuit substrate 10 are aligned, so that the window 201 is aligned with the unpatterned region 121. In other embodiments, the window 201 may be formed after the first single panel 200 is laminated on the first circuit substrate 10, for example, by a cover-opening process.
The second single panel 300 includes a second base layer 31 and a second metal layer 32 which are stacked. The second single panel 300 covers the second conductive layer 13.
The second base layer 31 and the first base layer 21 are respectively laminated on the second conductive layer 13 and the first conductive layer 12 through an adhesive layer 40. The adhesive layer 40 is an adhesive commonly used in the art, such as a thermally conductive pressure sensitive adhesive.
The material of the first base layer 21 and the second base layer 31 is a dielectric material commonly used in the art, such as polyimide, epoxy resin, etc. The material of the first metal layer 22 and the second metal layer 32 may include, but is not limited to, copper, gold, silver, and the like.
In step S3, referring to fig. 3, a through hole 110 is formed on the first circuit substrate 10 and the second single board 300.
The via hole 110 penetrates the unpatterned region 121 of the first conductive layer 12 and the second metal layer 32 in the thickness direction of the multilayer circuit board, and communicates with the window 201. In the present application, the thickness direction of the multilayer circuit board refers to the stacking direction of the first single panel 200, the first circuit substrate 10, and the second single panel 300.
The vias 110 may be formed using a mechanical drilling or laser drilling process.
Step S4, referring to fig. 4, electroplating is performed on the through hole 110 to form a conductive hole 101. The conductive via 101 is connected to the unpatterned area 121 of the first conductive layer 12 and the second metal layer 32.
During electroplating, a metal plating layer 111 is deposited on the wall of the through hole 110 to form the conductive via 101. The metal plating layer 111 is connected to the unpatterned region 121 of the first conductive layer 12 and the second metal layer 32. The material of the metal plating layer 111 may include, but is not limited to, copper, gold, silver, and the like.
Since the unpatterned region 121 of the first conductive layer 12 and the second metal layer 32 are both complete metal plates, when the through hole 110 is electroplated, current flows from the unpatterned region 121 of the first conductive layer 12 to the second metal layer 32, and from the second metal layer 32 to the unpatterned region 121 of the first conductive layer 12, and the current flows in both directions, so that a potential difference is not formed between the second metal layer 32 and the unpatterned region 121 of the first conductive layer 12, and the thickness of the deposited metal plating layer 111 is uniform in the thickness direction of the multilayer circuit board. That is, the thickness of the metal plating layer 111 is uniform throughout the thickness direction of the multilayer circuit board. In the present application, the thickness of the metal plating layer 111 refers to a distance between a surface of the metal plating layer 111 away from the hole wall of the through hole 110 and the hole wall of the through hole 110.
In step S5, referring to fig. 5, a circuit is fabricated on the first metal layer 22 and the second metal layer 32 to form a first conductive circuit layer 23 and a second conductive circuit layer 33, so as to obtain a multilayer circuit board.
The first conductive trace layer 23 and the first base layer 21 constitute a second trace substrate 20. The second conductive wiring line layer 33 and the second base layer 31 constitute a third wiring substrate 30. The first conductive line layer 23 and the second conductive line layer 33 may be formed through an image transfer process and an etching process.
At the same time as routing on the first metal layer 22 and the second metal layer 32, routing is performed on the unpatterned area 121 of the first conductive layer 12 to form part of the routing of the first conductive layer 12.
Referring to fig. 5, an embodiment of the present invention provides a multilayer circuit board, which includes a first circuit substrate 10, and a second circuit substrate 20 and a third circuit substrate 30 disposed on two opposite sides of the first circuit substrate 10. The second circuit board 20 has an opening 201, and a partial region of the first circuit board 10 is exposed through the opening 201. The first circuit substrate 10 and the third circuit substrate 30 are provided with conductive holes 101, the conductive holes 101 penetrate through and are electrically connected with the first circuit substrate 10 and the third circuit substrate 30 and communicated with the windowing 201, the side walls of the conductive holes 101 are provided with metal plating layers 111, and the thicknesses of the metal plating layers 111 are consistent in the thickness direction of the multilayer circuit board.
According to the manufacturing method of the multilayer circuit board, when the first conducting layer is formed in a manufacturing mode, circuit manufacturing is not carried out on the part, to be exposed, of the first conducting layer in the window of the second circuit substrate, so that when conducting holes penetrating through the first circuit substrate and the third circuit substrate are formed in an electroplating mode, a metal coating with uniform thickness can be formed; and when the circuits of the second circuit substrate and the third circuit substrate are formed, the circuits are formed on the unpatterned area of the first conductive layer, so that the process flow is simplified.
Although the present invention has been described with reference to the above preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A manufacturing method of a multilayer circuit board is characterized by comprising the following steps:
providing a first circuit substrate, wherein the first circuit substrate comprises an insulating layer and a first conducting layer which are arranged in a stacked mode, and the first conducting layer comprises a patterned area and an unpatterned area;
providing a first single-sided board, wherein the first single-sided board comprises a first base layer and a first metal layer which are arranged in a stacked mode, and a window penetrating through the first base layer and the first metal layer is formed in the first single-sided board;
providing a second single panel comprising a second base layer and a second metal layer;
pressing a first base layer of the first single panel and a second base layer of the second single panel on two opposite sides of the first circuit substrate, wherein at least one part of the unpatterned region of the first conductive layer is exposed from the window;
through holes are formed in the first circuit substrate and the second single-sided board, penetrate through the first conducting layer and the second metal layer and are communicated with the windowing;
and electroplating the through hole to form a conductive hole, wherein the first conductive layer and the second metal layer are electrically connected through the conductive hole.
2. The method of manufacturing a multilayer circuit board according to claim 1, wherein the step of providing a first circuit substrate comprises:
providing a substrate, wherein the substrate comprises an insulating layer and a metal layer which are arranged in a stacked mode;
and etching a part of the metal layer to form a circuit, and simultaneously not etching the rest part of the metal layer to obtain a first circuit substrate.
3. The method of claim 1, wherein the size of the opening is smaller than or equal to the size of the unpatterned area of the first conductive layer, such that the trace of the first conductive layer is not exposed from the opening during the bonding.
4. The method of manufacturing a multilayer circuit board according to claim 1, further comprising the steps of: and carrying out circuit manufacturing on the first metal layer and the second metal layer to form a first conductive circuit layer and a second conductive circuit layer.
5. The method for manufacturing a multilayer circuit board according to claim 4, wherein a first conductive line layer and a second conductive line layer are formed, and simultaneously, a circuit is formed in an unpatterned area of the first conductive layer.
6. The method for manufacturing a multilayer circuit board according to claim 1, wherein the first base layer and the second base layer are respectively laminated on two opposite sides of the first circuit substrate by an adhesive layer.
7. The method of manufacturing a multilayer circuit board according to claim 1, wherein the step of laminating the first base layer of the first single board and the second base layer of the second single board on opposite sides of the first circuit substrate further comprises the steps of: and aligning the first single-panel and the first circuit substrate to align the window with the unpatterned area of the first conductive layer.
8. The method of claim 1, wherein the first circuit substrate further comprises a second conductive layer disposed on a side of the insulating layer facing away from the first conductive layer, and the first base layer and the second base layer are respectively laminated on the first conductive layer and the second conductive layer.
9. A multilayer circuit board comprises a first circuit substrate, a second circuit substrate and a third circuit substrate, wherein the second circuit substrate and the third circuit substrate are arranged on two opposite sides of the first circuit substrate, the second circuit substrate is provided with a window exposing a partial area of the first circuit substrate, the first circuit substrate and the third circuit substrate are provided with conductive holes, the conductive holes are communicated with the window and electrically connected with the first circuit substrate and the third circuit substrate, the hole wall of each conductive hole forms a metal coating, and the thickness of each metal coating is consistent along the thickness direction of the multilayer circuit board.
10. The multilayer circuit board according to claim 9, wherein the second wiring substrate and the third wiring substrate are bonded to the first wiring substrate by adhesive layers, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110960839.XA CN115915649A (en) | 2021-08-20 | 2021-08-20 | Multilayer circuit board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110960839.XA CN115915649A (en) | 2021-08-20 | 2021-08-20 | Multilayer circuit board and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115915649A true CN115915649A (en) | 2023-04-04 |
Family
ID=86482696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110960839.XA Pending CN115915649A (en) | 2021-08-20 | 2021-08-20 | Multilayer circuit board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115915649A (en) |
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2021
- 2021-08-20 CN CN202110960839.XA patent/CN115915649A/en active Pending
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