CN115708401A - Manufacturing method of circuit board and circuit board - Google Patents

Manufacturing method of circuit board and circuit board Download PDF

Info

Publication number
CN115708401A
CN115708401A CN202110962686.2A CN202110962686A CN115708401A CN 115708401 A CN115708401 A CN 115708401A CN 202110962686 A CN202110962686 A CN 202110962686A CN 115708401 A CN115708401 A CN 115708401A
Authority
CN
China
Prior art keywords
layer
circuit
copper
dielectric layer
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110962686.2A
Other languages
Chinese (zh)
Inventor
李洋
祝长赫
李艳禄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Avary Holding Shenzhen Co Ltd
Original Assignee
Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Avary Holding Shenzhen Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongqisheng Precision Electronics Qinhuangdao Co Ltd, Avary Holding Shenzhen Co Ltd filed Critical Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Priority to CN202110962686.2A priority Critical patent/CN115708401A/en
Publication of CN115708401A publication Critical patent/CN115708401A/en
Pending legal-status Critical Current

Links

Images

Abstract

A manufacturing method of a circuit board comprises the following steps: providing a first copper-clad plate, wherein the first copper-clad plate comprises a first dielectric layer and a first copper layer which are arranged in a laminated manner; carrying out circuit manufacturing on the first copper layer to form a first circuit layer; providing a second copper-clad plate, wherein the second copper-clad plate comprises a second dielectric layer and a second copper layer which are arranged in a stacked mode; etching the second dielectric layer to form an opening penetrating through the second dielectric layer in the stacking direction; forming a metal layer connecting the second copper layer in the opening; providing a glue layer, bonding the metal layer and the first circuit layer, and bonding a first dielectric layer and a second dielectric layer on the glue layer; and carrying out circuit manufacturing on the second copper layer to form a bottom copper circuit layer, wherein the bottom copper circuit layer and the metal layer jointly form a second circuit layer with local thickening. The application also provides a circuit board.

Description

Manufacturing method of circuit board and circuit board
Technical Field
The present disclosure relates to the field of circuit boards, and particularly to a method for manufacturing a circuit board and a circuit board.
Background
Due to the limitation of the manufacturing method of the circuit board, the circuit layers of the circuit board are generally in the same thickness specification. However, under the trend of multi-functionalization (inductance/resistance/heat dissipation) of electronic products, there is an increasing demand for manufacturing circuit layers with different thicknesses on the same circuit layer, thereby realizing multi-functionalization and high-integration circuit boards.
The existing circuit board manufacturing method generally comprises the steps of firstly carrying out primary exposure and development processes on a copper-clad plate to form a circuit layer, then carrying out selective plating on the surface of a local circuit layer after secondary exposure and development to form a local thickened circuit layer, wherein the widths of the circuit layer in a thickened area are inconsistent (please refer to figures 1 and 2) due to large errors of the secondary exposure and development processes, and bubbles can be generated in the area with inconsistent line width in the subsequent glue filling process to influence the connection reliability of the circuit board; in addition, the copper plating process capacity is limited during selective plating, the thickening thickness is limited, and the smoothness of the circuit board in the selective plating thickening area is affected.
Disclosure of Invention
Therefore, it is desirable to provide a method for forming a local thick copper layer to solve the above problems.
The application also provides a circuit board.
A manufacturing method of a circuit board comprises the following steps: providing a first copper-clad plate, wherein the first copper-clad plate comprises a first dielectric layer and a first copper layer which are arranged in a stacked mode; carrying out circuit manufacturing on the first copper layer to form a first circuit layer; providing a second copper-clad plate, wherein the second copper-clad plate comprises a second dielectric layer and a second copper layer which are arranged in a stacked mode; etching the second dielectric layer to form an opening penetrating through the second dielectric layer in the stacking direction; forming a metal layer connecting the second copper layer in the opening; providing an adhesive layer and bonding the metal layer and the first circuit layer, wherein the adhesive layer is also bonded with the first dielectric layer and the second dielectric layer; and carrying out circuit manufacturing on the second copper layer to form a bottom copper circuit layer, wherein the bottom copper circuit layer and the metal layer jointly form a second circuit layer with local thickening.
In some embodiments, the metal layer extends through the second dielectric layer and protrudes from a surface of the second dielectric layer facing away from the second copper layer.
In some embodiments, before the step of bonding with the adhesive layer, the manufacturing method further includes forming a conductive layer on a surface of the first circuit layer and/or the metal layer, where the conductive layer is used to electrically connect the first circuit layer and the metal layer.
In some embodiments, the manufacturing method further includes a step of forming a solder mask layer on the surfaces of the second dielectric layer and the second circuit layer.
In some embodiments, the metal layer and the adjacent underlying copper wire layer have the same width in a direction perpendicular to the direction in which the metal layer and the underlying copper wire layer are stacked.
A circuit board comprises a first circuit substrate, an adhesive layer and a second circuit substrate, wherein the first circuit substrate comprises a first dielectric layer and a first circuit layer positioned on the surface of the first dielectric layer; the adhesive layer is positioned on the surface of the first circuit substrate with the first circuit layer and is bonded with the first circuit layer; the second circuit substrate is located the surface that the glue film deviates from first circuit substrate, and the second circuit substrate includes second dielectric layer and second circuit layer, and the second circuit layer includes interconnect's end copper circuit layer and metal level, and end copper circuit layer is located the surface that the second dielectric layer deviates from the glue film, and the metal level runs through the second dielectric layer and bonds with the glue film, and the metal level forms the second circuit layer of local bodiness with the regional formation that end copper circuit layer corresponds.
In some embodiments, the metal layer further extends into the glue layer, and a portion of the metal layer is embedded in the glue layer.
In some embodiments, the circuit board further includes a conductive layer between and connecting the first circuit layer and the metal layer.
In some embodiments, the circuit board further includes a solder mask layer covering the second dielectric layer and the second circuit layer.
In some embodiments, the metal layer and the adjacent underlying copper wire layer have the same width in a direction perpendicular to the direction in which the metal layer and the underlying copper wire layer are stacked.
According to the manufacturing method of the circuit board, the opening penetrating through the second medium layer is formed on the second medium layer, the metal layer is filled for thickening, the second circuit layer with local thickening is formed through one-time exposure and development, and the first medium layer and the first circuit layer are bonded through the glue layer to form the circuit board. According to the manufacturing method for local thickening, the inner side (the metal layer faces the glue layer) of the circuit board is thickened without changing the original circuit design, the inner layer space of the circuit board is occupied, local area thickening can be achieved without changing the original circuit design, and the thickness of the circuit board is not increased; the second circuit layer with the metal layer and the bottom copper circuit layer can be formed by adopting one-time exposure and development processes, the accuracy is higher, and the inconsistency of the widths of the adjacent metal layer and the bottom copper circuit layer along the second direction caused by the error of multiple times of exposure and development is avoided.
Drawings
Fig. 1 is a cross-sectional view of a line layer subjected to a thickening process, which is manufactured in the prior art.
Fig. 2 is a cross-sectional view of another line layer after thickening in the prior art.
Fig. 3 is a schematic cross-sectional view of a first copper-clad plate provided in the embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a first wiring substrate obtained by wiring the first copper layer shown in fig. 3.
Fig. 5 is a schematic cross-sectional view of the second copper-clad plate provided in the present application after an opening is formed in the second dielectric layer.
Fig. 6 is a schematic cross-sectional view of the opening shown in fig. 5 after a metal layer is formed therein.
Fig. 7 is a schematic cross-sectional view illustrating the structure shown in fig. 6 bonded to opposite surfaces of the first circuit substrate shown in fig. 4 by using an adhesive layer.
Fig. 8 is a schematic cross-sectional view of the second copper layer of fig. 7 after a second wiring layer is formed.
Fig. 9 is a schematic cross-sectional view of the circuit board obtained after forming solder masks on the surfaces of the second dielectric layer and the second circuit layer shown in fig. 8.
Fig. 10 is a schematic cross-sectional view of a circuit board obtained by disposing a conductive layer between a first circuit layer and a metal layer according to another embodiment of the present disclosure.
Description of the main elements
Figure BDA0003222826590000041
Figure BDA0003222826590000051
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application, and the described embodiments are merely a subset of the embodiments of the present application, rather than all embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes all and any combination of one or more of the associated listed items.
In various embodiments of the present application, for convenience in description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical connections, either direct or indirect. "upper", "lower", "above", "below", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly. It is to be understood that the following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 3 to 10, an embodiment of the present invention provides a method for manufacturing a circuit board 100, including the following steps:
step S1: referring to fig. 3, a first copper clad laminate 10 is provided, which includes a first dielectric layer 11 and a first copper layer 13 stacked together.
The first copper-clad plate 10 can be a single-sided copper-clad plate and can also be a double-sided copper-clad plate. In this embodiment, the first copper-clad plate 10 is a double-sided copper-clad plate, and includes a first dielectric layer 11 and first copper layers 13 located on two opposite surfaces of the first dielectric layer 11.
The first copper-clad plate 10 may be a soft plate or a hard plate, and the material of the first dielectric layer 11 may be one of flexible materials such as Polyimide (PI), liquid Crystal Polymer (LCP), modified Polyimide (MPI), and the like, or one of hard materials such as Polypropylene (PP) and Polytetrafluoroethylene (PTFE).
Step S2: referring to fig. 4, a first copper layer 13 is patterned to form a first circuit layer 132.
In the present embodiment, the first copper layer 13 on the two opposite surfaces of the first dielectric layer 11 is subjected to circuit fabrication, and the first copper layer 13 may be subjected to circuit fabrication by using exposure, development and electroplating processes to form the first circuit layer 132. The first wiring layers 132 on the opposite surfaces of the first dielectric layer 11 may be electrically connected through the first conductive holes 15 penetrating the first dielectric layer 11.
The first circuit layer 132 formed after the circuit fabrication and the first dielectric layer 11 together form the first circuit substrate 17. In this embodiment, the first circuit substrate 17 includes a first dielectric layer 11 and first circuit layers 132 disposed on two opposite surfaces of the first dielectric layer 11, and the first circuit layers 132 are electrically connected through the first conductive vias 15.
In some embodiments, the layer-adding process may be performed according to the requirement of the number of the line layers, that is, the number of the first line layers 132 of the first line substrate 17 may be one or more.
And step S3: referring to fig. 5, a second copper clad laminate 20 is provided, which includes a second dielectric layer 21 and a second copper layer 23 stacked together, and the second dielectric layer 21 is etched to form an opening 212 penetrating through the second dielectric layer 21.
The second copper-clad plate 20 may be a soft plate or a hard plate, and the material of the second dielectric layer 21 may be selected from one of flexible materials such as polyimide, liquid crystal high molecular polymer and modified polyimide, or from one of hard materials such as polypropylene and polytetrafluoroethylene.
The second copper-clad plate 20 may be a single-sided copper-clad plate or a double-sided copper-clad plate. In this embodiment, the second copper-clad plate 20 is a single-sided copper-clad plate, and includes a second dielectric layer 21 and a second copper layer 23 located on one surface of the second dielectric layer 21.
The manner of forming the opening 212 includes, but is not limited to, machining or laser etching. The second dielectric layer 21 and the second copper layer 23 are stacked along the first direction L1, and the opening 212 penetrates through the second dielectric layer 21 along the first direction L1, so that a part of the surface of the second copper layer 23 is exposed to the second dielectric layer 21.
And step S4: referring to fig. 6, a metal layer 214 is formed in the opening 212 to connect to the second copper layer 23.
The surface of the second copper layer 23 facing away from the second dielectric layer 21 may be masked, and then the metal layer 214 may be formed by surface plating. The metal layer 214 may penetrate through the second dielectric layer 21 and may further protrude from the second dielectric layer 21 so as to be thickened in the stacking direction. The thickness of the metal layer 214 in the stacking direction may be set as desired. In the present embodiment, the metal layer 214 protrudes from the surface of the second dielectric layer 21 facing away from the second copper layer 23.
The metal layer 214 is formed by surface plating, which can fundamentally replace the selective plating process, thereby avoiding the problems of tolerance and deviation caused by the selective plating process; in addition, the metal layer 214 may be formed to have a wider width in the surface plating direction.
Step S5: referring to fig. 7, an adhesive layer 30 is provided and adheres to the metal layer 214 and the first circuit layer 132, and the adhesive layer 30 also adheres to the first dielectric layer 11 and the second dielectric layer 21.
The first circuit substrate 17, the glue layer 30, the second dielectric layer 21, and the second copper layer 23 are stacked along the first direction L1. The metal layer 214 and the first circuit layer 132 are disposed toward the adhesive layer 30, so that the adhesive layer 30 bonds the metal layer 214 and the first circuit layer 132, and the adhesive layer 30 fills a gap between the first circuit layer 132 to bond the first dielectric layer 11, and fills a gap between the metal layer 214 and the second dielectric layer 21 to bond the second dielectric layer 21. Wherein the second copper layer 23 is located on a layer of the second dielectric layer 21 away from the glue layer 30, and is used for forming an outer layer circuit of the circuit board 100.
In the present embodiment, the above-described structure is bonded to both of the opposite surfaces of the first wiring substrate 17.
In the present embodiment, a portion of the metal layer 214 is embedded in the glue layer 30, and it can be understood that, along the first direction L1, the glue layer 30 provides a space for thickening the metal layer 214, and the portion of the metal layer 214 embedded in the glue layer 30 can increase the thickness of the metal layer 214.
Step S6: referring to fig. 8, the second copper layer 23 is patterned to form an underlying copper circuit layer 232, wherein the underlying copper circuit layer 232 and the metal layer 214 together form a locally thickened second circuit layer 25.
Specifically, a dry film (not shown) is coated on the surface of the second copper layer 23, and the dry film is exposed, developed, and etched to form the bottom copper wiring layer 232. In the developing step, the second copper layer 23 corresponding to the metal layer 214 is still covered by the dry film and is prevented from being etched, so that the width of the bottom copper circuit layer 232 corresponding to the metal layer 214 along a second direction L2 perpendicular to the first direction L1 is equal. That is, the second circuit layer 25 thickened along the first direction L1 can be formed by combining the metal layer 214 and the bottom copper circuit layer 232 through one exposure and development process, so that the accuracy is higher, and the inconsistency of the widths of the adjacent metal layer 214 and the bottom copper circuit layer 232 along the second direction L2 caused by the error of multiple exposure and development is avoided.
The second dielectric layer 21 and the second circuit layer 25 together form a second circuit substrate 27.
In the step of forming the second circuit layer 25, a second conductive via 28 is also formed, and the second conductive via 28 is connected to penetrate through the second dielectric layer 21 and the adhesive layer 30 to electrically connect the second circuit layer 25 and the first circuit layer 132.
Step S7: referring to fig. 9, a solder mask layer 40 is formed on the surface of the second circuit substrate 27 away from the first circuit substrate 17, and the solder mask layer 40 covers the second dielectric layer 21 and the second circuit layer 25.
The solder mask 40 covers the second circuit substrate 27, and the second circuit layer 25 is used as an outer circuit layer of the circuit board 100.
In some embodiments, referring to fig. 10, in some application scenarios of the circuit board 100a, for example, when the first circuit layer 132 and the second circuit layer 25 are circuit networks with the same property, before the step of bonding with the adhesive layer 30, the manufacturing method may further include forming a conductive layer 50 on the surface of the first circuit layer 132 and/or the metal layer 214, where the conductive layer 50 is used to electrically connect the first circuit layer 132 and the second circuit layer 25.
Referring to fig. 9, the present application further provides a circuit board 100, and the circuit board 100 can be manufactured by the above manufacturing method. The circuit board 100 includes a first circuit substrate 17, a glue layer 30, and a second circuit substrate 27 stacked along a first direction L1, wherein the glue layer 30 is located between the first circuit substrate 17 and the second circuit substrate 27 and is used for bonding the first circuit substrate 17, i.e., the second circuit substrate 27.
The first circuit board 17 includes a first dielectric layer 11 and a first circuit layer 132 stacked in the first direction L1. The first circuit board 17 may be a single-layer circuit board or a multi-layer circuit board, and when the first circuit board 17 is a multi-layer circuit board, the multi-layer circuit layers may be electrically connected through the first conductive via 15.
In this embodiment, the first circuit substrate 17 is a double-layer circuit substrate, the first circuit layer 132 is disposed on two opposite surfaces of the first dielectric layer 11, and the first circuit layer 132 is bonded to the adhesive layer 30. The glue layer 30 also fills the gaps between the first line layers 132 to be bonded to the first dielectric layer 11.
The second wiring substrate 27 is a single-layer wiring substrate. The second circuit substrate 27 is located on the surface of the glue layer 30 facing away from the first circuit substrate 17. The second wiring board 27 includes a second dielectric layer 21 and a second wiring layer 25 stacked in the first direction L1. The second circuit layer 25 is located on the surface of the second dielectric layer 21 and at least a portion of the second circuit layer 25 penetrates through the second dielectric layer 21.
Specifically, the second wiring layer 25 includes a bottom copper wiring layer 232 and a metal layer 214 connected to the bottom copper wiring layer 232. The first dielectric layer 11 is bonded to the surface of the glue layer 30, the bottom copper circuit layer 232 is located on the surface of the second dielectric layer 21 away from the glue layer 30, and the metal layer 214 penetrates through the second dielectric layer 21 and is bonded to the glue layer 30.
It is understood that, along the first direction L1, the thickness of the region of the second line layer 25 having the metal layer 214 is greater than the thickness of the second line layer 25 not provided with the metal layer 214, which realizes local region thickening of the circuit board 100. In the second direction L2 (i.e. perpendicular to the direction in which the metal layer 214 and the bottom copper circuit layer 232 are stacked), the width of the metal layer 214 is equal to the width of the second circuit layer 25.
In the embodiment, a portion of the metal layer 214 further extends to the adhesive layer 30 and is embedded in the adhesive layer 30, that is, the metal layer 214 occupies a portion of the space of the adhesive layer 30, so as to further increase the thickness of the metal layer 214 along the first direction L1, and the thickness of the circuit board 100 along the first direction L1 is not increased at this time.
In some embodiments, the circuit board 100 further includes a solder mask layer 40, the solder mask layer 40 covers the second circuit substrate 27, and the second circuit substrate 27 is an outer side of the circuit board 100, i.e. the second circuit layer 25 is an outer circuit layer of the circuit board 100. In some application scenarios of the circuit board 100 (e.g., the locally thickened region serves as a power line), that is, the power line is located on the outer surface of the circuit board 100, which is beneficial for heat dissipation.
In some embodiments, referring to fig. 10, in some application scenarios of the circuit board 100a, for example, when the first circuit layer 132 and the second circuit layer 25 are circuit networks with the same property, the circuit board further includes a conductive layer 50, and the conductive layer 50 is located between the first circuit layer 132 and the metal layer 214 and connects the first circuit layer 132 and the metal layer 214.
According to the manufacturing method of the circuit board 100 and 100a, the opening 212 penetrating through the second dielectric layer 21 is formed on the second dielectric layer 21, the metal layer 214 is filled for thickening, the second circuit layer 25 with local thickening is formed through exposure and development once, and the first dielectric layer 11 and the first circuit layer 132 are bonded through the adhesive layer 30 to form the circuit board 100. In the above manufacturing method for local thickening, the inner side (the metal layer 214 faces the glue layer 30) of the circuit board 100 is thickened without changing the original circuit design, so that the inner layer space of the circuit board 100 is occupied, and the local area thickening can be realized without changing the original circuit design and without increasing the thickness of the circuit board 100; the second circuit layer 25 having the metal layer 214 and the bottom copper circuit layer 232 can be formed by one exposure and development process, so that the accuracy is higher, and the inconsistency of the widths of the adjacent metal layer 214 and the bottom copper circuit layer 232 along the second direction L2 caused by the error of multiple exposure and development is avoided.
Although the present application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.

Claims (10)

1. The manufacturing method of the circuit board is characterized by comprising the following steps:
providing a first copper-clad plate, wherein the first copper-clad plate comprises a first dielectric layer and a first copper layer which are arranged in a stacked mode;
carrying out circuit manufacturing on the first copper layer to form a first circuit layer;
providing a second copper-clad plate which comprises a second dielectric layer and a second copper layer which are arranged in a laminated manner;
etching the second dielectric layer to form an opening penetrating through the second dielectric layer in the stacking direction;
forming a metal layer connecting the second copper layer in the opening;
providing an adhesive layer and bonding the metal layer and the first circuit layer, wherein the adhesive layer is also bonded with the first dielectric layer and the second dielectric layer; and
and carrying out circuit manufacturing on the second copper layer to form a bottom copper circuit layer, wherein the bottom copper circuit layer and the metal layer jointly form a second circuit layer with local thickening.
2. The method of claim 1, wherein the metal layer penetrates the second dielectric layer and protrudes from a surface of the second dielectric layer facing away from the second copper layer.
3. The method for manufacturing a circuit board according to claim 1, wherein before the step of bonding with the adhesive layer, the method further comprises forming a conductive layer on a surface of the first circuit layer and/or the metal layer, the conductive layer being configured to electrically connect the first circuit layer and the metal layer.
4. The method of claim 1, further comprising a step of forming a solder mask layer on the surfaces of the second dielectric layer and the second circuit layer.
5. The method of claim 1, wherein the metal layer and the adjacent underlying copper trace layer have the same width in a direction perpendicular to the direction in which the metal layer and the underlying copper trace layer are stacked.
6. A circuit board, comprising:
the first circuit substrate comprises a first dielectric layer and a first circuit layer positioned on the surface of the first dielectric layer;
the adhesive layer is positioned on the surface, provided with the first circuit layer, of the first circuit substrate and is bonded with the first circuit layer; and
second circuit base plate is located the glue film deviates from the surface of first circuit base plate, second circuit base plate includes second dielectric layer and second circuit layer, second circuit layer includes interconnect's end copper circuit layer and metal level, end copper circuit layer is located the second dielectric layer deviates from the surface of glue film, the metal level runs through the second dielectric layer and with the glue film bonds, the metal level with the regional local bodiness of formation that corresponds on end copper circuit layer second circuit layer.
7. The circuit board of claim 6, wherein the metal layer further extends into the glue layer, and a portion of the metal layer is embedded in the glue layer.
8. The circuit board of claim 6, further comprising a conductive layer between and connecting the first circuit layer and the metal layer.
9. The circuit board of claim 6, further comprising a solder mask layer covering the second dielectric layer and the second circuit layer.
10. The circuit board of claim 6, wherein the metal layer has a width equal to that of an adjacent underlying copper trace layer in a direction perpendicular to a direction in which the metal layer and the underlying copper trace layer are stacked.
CN202110962686.2A 2021-08-20 2021-08-20 Manufacturing method of circuit board and circuit board Pending CN115708401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110962686.2A CN115708401A (en) 2021-08-20 2021-08-20 Manufacturing method of circuit board and circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110962686.2A CN115708401A (en) 2021-08-20 2021-08-20 Manufacturing method of circuit board and circuit board

Publications (1)

Publication Number Publication Date
CN115708401A true CN115708401A (en) 2023-02-21

Family

ID=85212732

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110962686.2A Pending CN115708401A (en) 2021-08-20 2021-08-20 Manufacturing method of circuit board and circuit board

Country Status (1)

Country Link
CN (1) CN115708401A (en)

Similar Documents

Publication Publication Date Title
KR100962837B1 (en) Multilayer printed wiring board and process for producing the same
KR100836653B1 (en) Circuit board and method for manufacturing thereof
US9338891B2 (en) Printed wiring board
KR20030088357A (en) Metal core substrate and process for manufacturing same
US20150334844A1 (en) Printed wiring board
JP2006165496A (en) Parallel multi-layer printed board having inter-layer conductivity through via post
KR100757910B1 (en) Buried pattern substrate and manufacturing method thereof
TWI479972B (en) Multi-layer flexible printed wiring board and manufacturing method thereof
TW201410097A (en) Multilayer flexible printed circuit board and method for manufacturing same
KR20050095893A (en) Multilayer board and its manufacturing method
TWI714953B (en) Printed circuit board
US20170006699A1 (en) Multilayer circuit board, semiconductor apparatus, and method of manufacturing multilayer circuit board
US8546698B2 (en) Wiring board and method for manufacturing the same
KR100536315B1 (en) Semiconductor packaging substrate and manufacturing method thereof
JP2004186235A (en) Wiring board and method for manufacturing the same
JPH0794868A (en) Multilayered wiring board and its manufacture
CN115708401A (en) Manufacturing method of circuit board and circuit board
CN107231757B (en) Flexible circuit board and manufacturing method thereof
US20170271734A1 (en) Embedded cavity in printed circuit board by solder mask dam
KR100441253B1 (en) method for manufacturing multi-layer printed circuit board using bump
US10051736B2 (en) Printed wiring board and method for manufacturing printed wiring board
JP2000340954A (en) Wiring board, manufacture thereof and multilayered wiring board
TWI778356B (en) Rigid-flexible circuit board and method of manufacturing the same
JP2019091897A (en) Component mounting resin substrate
CN112566390B (en) Multilayer flexible circuit board and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination