JP3165617B2 - Multilayer printed wiring board and method of manufacturing the same - Google Patents

Multilayer printed wiring board and method of manufacturing the same

Info

Publication number
JP3165617B2
JP3165617B2 JP6812695A JP6812695A JP3165617B2 JP 3165617 B2 JP3165617 B2 JP 3165617B2 JP 6812695 A JP6812695 A JP 6812695A JP 6812695 A JP6812695 A JP 6812695A JP 3165617 B2 JP3165617 B2 JP 3165617B2
Authority
JP
Japan
Prior art keywords
hole
copper foil
layer
inner layer
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6812695A
Other languages
Japanese (ja)
Other versions
JPH08264952A (en
Inventor
明男 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP6812695A priority Critical patent/JP3165617B2/en
Publication of JPH08264952A publication Critical patent/JPH08264952A/en
Application granted granted Critical
Publication of JP3165617B2 publication Critical patent/JP3165617B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は硬質、フレキシブル、複
合の多層プリント配線基板に関し、特に多層プリント配
線基板の導体層間接続構造及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rigid, flexible, composite multilayer printed wiring board, and more particularly to a structure for connecting conductive layers of a multilayer printed wiring board and a method of manufacturing the same .

【0002】[0002]

【従来の技術】従来の多層プリント配線基板は、エッチ
ング等により回路形成された複数の導体層(導体パター
ン)と、その各層を接続するスルーホールにて構成され
ている。
2. Description of the Related Art A conventional multilayer printed wiring board is composed of a plurality of conductor layers (conductor patterns) formed by etching or the like, and through holes connecting the respective layers.

【0003】従来の多層プリント配線基板及びその製造
工程を図6及び図7に従って説明する。図6は、多層プ
リント配線基板の製造工程の前半工程を示す断面図であ
り、図7は多層プリント配線基板の構造及びその製造工
程の後半工程をしめす断面図である。本従来例では、代
表的な4層構成の多層プリント配線基板を用いて説明す
る。
A conventional multilayer printed wiring board and its manufacturing process will be described with reference to FIGS. FIG. 6 is a cross-sectional view showing the first half of the manufacturing process of the multilayer printed wiring board, and FIG. 7 is a cross-sectional view showing the structure of the multilayer printed wiring board and the second half of the manufacturing process. This conventional example will be described using a typical four-layered multilayer printed wiring board.

【0004】該多層プリント配線基板の構造は、図7
(c)に示すように、第1層となる外層導体パターン1
を有する第1片面コア材(外層基板)2と、第2層及び
第3層となる内層導体パターン3,4を有する両面コア
材(内層基板)5と、第4層となる外層導体パターン6
を有する第2片面コア材(外層基板)7と、前記片面コ
ア材2,7と両面コア材5との間に介在される接着材層
(絶縁層)8と、これらを貫通する貫通孔9と、該貫通
孔9表面及び外層導体パターン1,6表面を被覆する銅
メッキ10とを備えてなる構造である。
The structure of the multilayer printed wiring board is shown in FIG.
As shown in (c), the outer layer conductor pattern 1 serving as the first layer
, A double-sided core material (inner substrate) 5 having inner layer conductor patterns 3 and 4 serving as second and third layers, and an outer layer conductor pattern 6 serving as fourth layer
A single-sided core material (outer layer substrate) 7 having an adhesive, an adhesive layer (insulating layer) 8 interposed between the single-sided core materials 2, 7 and the double-sided core material 5, and a through hole 9 penetrating therethrough And a copper plating 10 covering the surface of the through hole 9 and the surface of the outer layer conductor patterns 1 and 6.

【0005】前記片面コア材2,7はベース基材2′,
7′の一表面に外層導体パターン1,6が形成されてな
り、前記両面コア材5はベース基材5′の表裏面に内層
導体パターン3,4が形成されてなる。
[0005] The single-sided core members 2 and 7 are made of a base material 2 ',
Outer conductor patterns 1 and 6 are formed on one surface of 7 ', and double-sided core material 5 is formed by inner conductor patterns 3 and 4 formed on the front and back surfaces of base substrate 5'.

【0006】前記貫通孔9とその表面を被覆する金属メ
ッキ10とで、各導体パターン1,3,4,6を接続す
るスルーホール11を構成している。
The through hole 9 and the metal plating 10 covering the surface thereof constitute a through hole 11 for connecting the conductor patterns 1, 3, 4, and 6.

【0007】以下、上記多層プリント配線基板の製造工
程を説明する。
Hereinafter, a process of manufacturing the multilayer printed wiring board will be described.

【0008】まず、図6(a)に示すように内層回路と
なる未加工の連続した銅箔3′,4′をベース基材5′
の表裏面に積層した両面コア材5を用意し、図6(b)
に示すように前記銅箔3′,4′をエッチング等により
必要な内層導体パターン3,4に形成して内層コア材5
を形成する。
First, as shown in FIG. 6 (a), unprocessed continuous copper foils 3 ', 4' serving as an inner layer circuit are formed on a base material 5 '.
6B, a double-sided core material 5 laminated on the front and back surfaces is prepared.
As shown in FIG. 3, the copper foils 3 'and 4' are formed into necessary inner conductor patterns 3 and 4 by etching or the like, and the inner core material 5 is formed.
To form

【0009】次に、図6(c)に示すように、内層導体
パターン3,4を形成した両面コア材5の表裏面側に、
それぞれ接着シート8′と外層回路となる未加工の連続
した銅箔1′,6′をベース基材2′,7′の一表面に
積層した片面コア材2,7とを順次積層し、この後これ
らを加熱しながら圧力を加えて図6(d)に示すように
積層し、一枚の積層板12とする。
Next, as shown in FIG. 6C, on the front and back sides of the double-sided core material 5 on which the inner layer conductor patterns 3 and 4 are formed,
Adhesive sheet 8 'and single-sided core materials 2 and 7 in which unprocessed continuous copper foils 1' and 6 'serving as outer layer circuits are laminated on one surface of base materials 2' and 7 'are sequentially laminated. Thereafter, pressure is applied while heating them, and they are laminated as shown in FIG.

【0010】この状態では、内層回路と外層回路とが未
接続であるので、次に図7(a)に示すように、内層回
路を含む積層板12全体を貫通する貫通孔9をドリル等
により加工し、さらに図7(b)に示すように、前記貫
通孔9内壁表面及び外層の銅箔1′,6′表面全体に無
電解及び電解銅メッキ10を施す。この段階で内層回路
と外層回路とがスルーホール11によって電気的に接続
される。
In this state, since the inner layer circuit and the outer layer circuit are not connected, as shown in FIG. 7A, a through hole 9 penetrating the entire laminated board 12 including the inner layer circuit is drilled or the like. Then, as shown in FIG. 7B, electroless and electrolytic copper plating 10 is applied to the inner wall surface of the through hole 9 and the entire surface of the copper foils 1 'and 6' of the outer layer. At this stage, the inner layer circuit and the outer layer circuit are electrically connected by the through hole 11.

【0011】最後に、図7(c)に示すように、外層の
銅箔1′,6′及びその表面に施された銅メッキ10を
エッチング等により必要な外層導体パターン1,6に形
成され、4層プリント配線基板が得られる。
Finally, as shown in FIG. 7 (c), the outer copper foils 1 ', 6' and the copper plating 10 applied to the surfaces thereof are formed into necessary outer conductor patterns 1, 6 by etching or the like. A four-layer printed wiring board is obtained.

【0012】このように、従来の多層プリント配線基板
において、内層導体パターン3,4と外層導体パターン
1,6との電気的接続は、貫通孔9を設けることにより
該貫通孔9内壁に露出する内層導体パターン3,4の銅
箔厚み分の断面とスルーホール11における銅メッキ1
0とを介してなされていた。
As described above, in the conventional multilayer printed wiring board, the electrical connection between the inner conductor patterns 3 and 4 and the outer conductor patterns 1 and 6 is provided on the inner wall of the through hole 9 by providing the through hole 9. Cross section of inner conductor patterns 3 and 4 corresponding to copper foil thickness and copper plating 1 in through hole 11
It was done through zero.

【0013】[0013]

【発明が解決しようとする課題】技術の進歩により、多
層プリント配線基板に搭載される部品が多機能化且つ小
型化し、配線密度が高くなっている。また、多層プリン
ト配線基板が組み込まれる製品の寸法も軽薄短小の流れ
により小型化、薄型化が進行している。このことによ
り、多層プリント配線基板の薄型化、ファインパターン
化が求められ、それを実現するために外層及び内層導体
パターン1,3,4,6の銅箔厚みの薄型化が要求され
ている。ちなみに、一般的な従来の導体パターンの銅箔
厚みは35μmであり、現在18μmの銅箔厚みとする
ことが検討されつつあり、将来的には9μmの銅箔厚み
とすることが考えられている。
As the technology advances, the components mounted on the multilayer printed wiring board have become multifunctional and smaller, and the wiring density has been increased. In addition, the dimensions of products in which a multilayer printed wiring board is incorporated are also becoming smaller and thinner due to the trend toward light, thin and small. As a result, the multilayer printed wiring board is required to be thinner and finer, and in order to realize this, the copper foil of the outer and inner conductor patterns 1, 3, 4, and 6 is required to be thinner. Incidentally, the copper foil thickness of a general conventional conductor pattern is 35 μm, and it is currently being considered to have a copper foil thickness of 18 μm, and it is considered that the copper foil thickness will be 9 μm in the future. .

【0014】ところが、内層導体パターン3,4の銅箔
が薄くなると、従来の構造では内層導体パターン3,4
と外層導体パターン1,6との電気的接続は、内層導体
パターン3,4が貫通孔9内壁に露出する銅箔厚み分の
断面のみとスルーホール11における銅メッキ10を介
してなされているため、接続面積が少なくなり、接続信
頼性が低下する傾向にある。
However, when the copper foil of the inner conductor patterns 3 and 4 becomes thinner, the inner conductor patterns 3 and 4 in the conventional structure become thinner.
The electrical connection between the outer conductor patterns 1 and 6 is made only through the cross section of the copper foil thickness where the inner conductor patterns 3 and 4 are exposed on the inner wall of the through hole 9 and through the copper plating 10 in the through hole 11. In addition, the connection area tends to decrease, and the connection reliability tends to decrease.

【0015】また、配線密度を高くするためにスルーホ
ール11、詳細には貫通孔9の孔径が小径化しているた
めに、きれいな形状に孔明けができる加工条件範囲が狭
くなっており、孔明け時にスミアと呼ばれる樹脂の溶着
物が孔の内壁に発生し易くなる。ちなみに、一般的な従
来の貫通孔9の孔径は0.5φであり、小径化に伴って
0.4φの孔径が検討されつつある。
In addition, since the diameter of the through hole 11, specifically, the diameter of the through hole 9 is reduced in order to increase the wiring density, the range of processing conditions for forming a beautiful shape is narrowed. A resin deposit sometimes called smear is likely to be generated on the inner wall of the hole. Incidentally, the hole diameter of a general conventional through-hole 9 is 0.5φ, and a hole diameter of 0.4φ is being studied as the diameter is reduced.

【0016】図8は、孔明け加工後、スミアが発生した
状態を説明するための貫通孔断面の斜視図である。図
中、3,4が内層導体パターンであり、9が貫通孔であ
り、13がスミアである。
FIG. 8 is a perspective view of a cross section of a through hole for explaining a state in which smear has occurred after drilling. In the figure, 3 and 4 are inner layer conductor patterns, 9 is a through hole, and 13 is a smear.

【0017】該スミア13が図8に示すように内層導体
パターン3,4の貫通孔9内壁に露出している部分に発
生した場合、該貫通孔9内壁表面に施される銅メッキ1
0と内層導体パターン3,4との接続面積が著しく減少
することになり、両者の接続信頼性が低下し、最悪の場
合スルーホール接続部の断線の原因となる。
When the smear 13 occurs on the portion of the inner conductor patterns 3 and 4 exposed on the inner wall of the through hole 9 as shown in FIG.
The connection area between 0 and the inner conductor patterns 3 and 4 is remarkably reduced, and the connection reliability between the two is reduced. In the worst case, the through-hole connection is broken.

【0018】本発明は、上記課題に鑑み、内層導体パタ
ーンの薄型化並びにスルーホール孔径の小径化に対応
し、スルーホール接続部の断線を防止してなる多層プリ
ント配線基板及びその製造方法を提供することを目的と
する。
SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a multilayer printed wiring board and a method of manufacturing the multilayer printed wiring board, in which the thickness of the inner conductor pattern is reduced and the diameter of the through hole is reduced to prevent disconnection of the through hole connection part. The purpose is to do.

【0019】[0019]

【課題を解決するための手段】本発明の請求項1記載の
多層プリント配線基板は、内層ベース基材の少なくとも
一表面に内層導体パターンが形成されてなる内層基板
と、該内層基板の表裏面に絶縁層を介して積層される外
層導体パターンと、これらを貫通する第1貫通孔と、該
第1貫通孔表面及び前記外層導体パターン表面を覆う第
1金属メッキとを備えてなる多層プリント配線基板にお
いて、前記内層基板は、連続した銅箔が表面に積層され
た内層ベース基材に前記第1貫通孔と略同心状の第2貫
通孔が形成された後に、該第2貫通孔内壁表面及び前記
内層ベース基材表面の銅箔表面全体に無電解及び電解メ
ッキが施され第2金属メッキが形成されてから、前記内
層ベース基材表面の銅箔及び該銅箔表面に形成された第
2金属メッキがエッチングにより内層導体パターンに形
成され、該内層基板表面の内層導体パターンに絶縁層を
介して外層パターンとなる銅箔が積層された後に、前記
第2貫通孔内壁表面及び前記外層パターンとなる銅箔表
面全体に無電解及び電解メッキが施され第1金属メッキ
が形成されてから、前記外層パターンとなる銅箔及び該
銅箔表面に形成された第1金属メッキがエッチングによ
り外層導体パターンに形成されてなることを特徴とする
ものである。
According to a first aspect of the present invention, there is provided a multilayer printed wiring board comprising an inner layer base material having an inner layer conductor pattern formed on at least one surface thereof; Printed wiring, comprising: an outer conductor pattern laminated on an insulating layer via an insulating layer; a first through hole penetrating the outer conductor pattern; and a first metal plating covering the surface of the first through hole and the outer conductor pattern. In the substrate, the inner layer substrate has a continuous copper foil laminated on the surface.
A second through hole substantially concentric with the first through hole in the inner layer base material.
After the through hole is formed, the second through hole inner wall surface and the
Electroless and electrolytic plating is applied to the entire copper foil surface on the inner layer base substrate surface.
After the hook is applied and the second metal plating is formed,
Copper foil on the surface of the layer base material and the second copper foil formed on the surface of the copper foil
2 Metal plating forms inner layer conductor pattern by etching
And an insulating layer on the inner conductor pattern on the inner substrate surface.
After the copper foil serving as the outer layer pattern is laminated via the
Copper foil table as inner wall surface of second through hole and outer layer pattern
First metal plating with electroless and electrolytic plating on the entire surface
Is formed, a copper foil serving as the outer layer pattern and the copper foil
The first metal plating formed on the copper foil surface is etched
The outer conductor pattern .

【0020】[0020]

【0021】本発明の請求項記載の多層プリント配線
基板は、前記第2貫通孔及びその表面を覆う第2金属メ
ッキとからなる内層接続用スルーホールの孔径を前記第
1貫通孔の孔径と略同径としてなること特徴とするもの
である。
According to a second aspect of the present invention, in the multi-layer printed wiring board, the diameter of the through hole for the inner layer formed of the second through hole and the second metal plating covering the surface thereof is made equal to the diameter of the first through hole. It is characterized by having substantially the same diameter.

【0022】本発明の請求項記載の多層プリント配線
基板は、前記第2貫通孔及びその表面を覆う第2金属メ
ッキとからなる内層接続用スルーホールの孔径を前記第
1貫通孔の孔径よりも小径としてなること特徴とするも
のである。本発明の請求項4記載の多層プリント配線基
板の製造方法は、連続した銅箔が内層ベース基材の表裏
面に積層された内層両面コア材に貫通孔を形成し、該貫
通孔内壁表面及び前記内層ベース基材表裏面の銅箔表面
全体に無電解及び電解銅メッキを施し、前記内層ベース
基材表裏面の銅箔及び該銅箔表面に形成された銅メッキ
をエッチングにより内層導体パターンに形成し、前記内
層両面コア材に形成された貫通孔と同心状の貫通部を有
する接着シートと、連続した銅箔が外層ベース基材の表
面に積層され前記内層両面コア材に形成された貫通孔と
同心状の貫通部を有する外層コア材とを、前記内層両面
コア材の内層導体パターン側に順次積層した後、加熱し
ながら圧力を加えて積層板を形成し、前記内層両面コア
材に形成された貫通孔と前記接着シートの貫通部と前記
外層コア材の貫通部との内壁表面及び前記外層ベース基
材表面の銅箔表面全体に無電解及び電解銅メッキを施
し、前記外層ベース基材表面の銅箔及び該銅箔表面に形
成された銅メッキをエッチングにより外層導体パターン
に形成することを特徴とするものである。
According to a third aspect of the present invention, in the multi-layer printed wiring board according to the present invention, the diameter of the through hole for connecting the inner layer made of the second through hole and the second metal plating covering the surface thereof is made larger than the diameter of the first through hole. Also has a small diameter. The method for manufacturing a multilayer printed wiring board according to claim 4 of the present invention is characterized in that a continuous copper foil is formed on both sides of the inner layer base material.
A through hole is formed in the inner double-sided core material laminated on the surface, and the through hole is formed.
Copper foil surface on the inner wall surface of the through hole and on the front and back surfaces of the inner layer base material
Electroless and electrolytic copper plating on the whole, the inner layer base
Copper foil on the front and back of the substrate and copper plating formed on the surface of the copper foil
Is formed on the inner conductor pattern by etching,
With a through-hole concentric with the through-hole formed in the core material
Adhesive sheet and continuous copper foil
Through holes formed in the inner layer double-sided core material laminated on the surface
An outer layer core material having concentric through portions,
After sequentially laminating on the inner conductor pattern side of the core material, heat
While applying pressure to form a laminate, the inner layer double-sided core
A through hole formed in the material, a through portion of the adhesive sheet,
Inner wall surface with penetration of outer layer core material and outer layer base substrate
Electroless and electrolytic copper plating on the entire copper foil surface
And forming a copper foil on the surface of the outer layer base material and a surface of the copper foil.
Outer layer conductor pattern by etching the formed copper plating
It is characterized by being formed in.

【0023】[0023]

【作用】上記構成によれば、本発明は、上記のような
成なので、第2金属メッキ表面又は内層両面コア材の貫
通孔内壁表面に形成された銅メッキが第1貫通孔内壁
は積層板の貫通孔に露出して接続部となり従来の貫通孔
内壁に露出する内層導体パターンの厚み分の断面のみの
接続部の接続面積に比較して大幅に接続面積が増加し、
内層導体パターンの厚みが薄くなった場合においても高
い接続信頼性を得ることができる。
According to the above structure, the present invention has the above-described structure, and therefore , the penetration of the second metal plating surface or the inner layer double-sided core material.
Copper plating formed on the hole inner wall surface of the first inner wall of the through hole also
Is exposed to the through-hole of the laminated plate and becomes a connection part, and the connection area is significantly increased compared to the connection area of the connection part only in the cross section corresponding to the thickness of the inner conductor pattern exposed to the inner wall of the conventional through-hole,
High connection reliability can be obtained even when the thickness of the inner conductor pattern is reduced.

【0024】また、内層ベース基材,外層ベース基材等
の孔加工時に内層導体パターン断面,外層導体パターン
断面等にスミアが発生しても、内層導体パターンと外層
導体パターンとの主な接続は、内層導体パターン表面、
第2金属メッキ又は内層両面コア材の貫通孔内壁表面に
形成された銅メッキ、第1金属メッキ又は内層両面コア
材に形成された貫通孔と接着シートの貫通部と外層コア
材の貫通部との内壁表面に形成された銅メッキ、外層導
体パターン表面を通じて行われるため、前記スミアによ
って接続信頼性が損なわれることが無い。
Further, even if a smear occurs in the cross section of the inner conductor pattern, the outer conductor pattern, or the like at the time of forming a hole in the inner base material, the outer base material, or the like, the main connection between the inner conductor pattern and the outer conductor pattern is maintained. , Inner layer conductor pattern surface,
On the inner wall surface of the through-hole of the second metal plating or inner layer double-sided core material
Formed copper plating , first metal plating or inner double-sided core
Through-holes formed in the material, through-holes in the adhesive sheet and outer layer core
Since the copper plating is formed on the inner wall surface with the through portion of the material and is performed through the outer layer conductor pattern surface, the connection reliability is not impaired by the smear.

【0025】さらに、本発明の請求項記載の多層プリ
ント配線基板は、前記第2貫通孔及びその表面を覆う第
2金属メッキとからなる内層接続用スルーホールの孔径
が前記第1貫通孔の孔径よりも小径としてなる構成なの
で、内層導体パターンの表面を覆う第2金属メッキが第
1貫通孔内に露出することになり、該第2金属メッキに
ついても前記第1金属メッキと接続されることから、さ
らに高い接続信頼性を得ることができる。
Further, in the multilayer printed wiring board according to a third aspect of the present invention, the diameter of the through hole for the inner layer formed of the second through hole and the second metal plating covering the surface of the second through hole is smaller than that of the first through hole. Since the diameter is smaller than the hole diameter, the second metal plating covering the surface of the inner conductor pattern is exposed in the first through hole, and the second metal plating is also connected to the first metal plating. Therefore, higher connection reliability can be obtained.

【0026】[0026]

【実施例】本発明の一実施例よりなる多層プリント配線
基板及びその製造工程を図1及び図2に従って説明す
る。図1は多層プリント配線基板の構造及びその製造工
程の後半工程を示す断面図であり、図2は多層プリント
配線基板の製造工程の前半工程を示す断面図である。本
実施例では、代表的な4層構成の多層プリント配線基板
を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer printed wiring board according to an embodiment of the present invention and a manufacturing process thereof will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing the structure of the multilayer printed wiring board and the latter half of the manufacturing process, and FIG. 2 is a cross-sectional view showing the first half of the manufacturing process of the multilayer printed wiring board. In the present embodiment, description will be made using a typical multilayer printed wiring board having a four-layer structure.

【0027】該多層プリント配線基板の構造は、図1
(d)に示すように、第1層となる外層導体パターン2
1を有する第1片面コア材(外層基板)22と、第2層
及び第3層となる内層導体パターン23,24を有する
両面コア材(内層基板)25と、第4層となる外層導体
パターン26を有する第2片面コア材(外層基板)27
と、前記片面コア材22,27と両面コア材25との間
に介在される接着材層(絶縁層)28と、これらを貫通
する第1貫通孔29と、該第1貫通孔29表面及び外層
導体パターン21,26表面を被覆する第1銅メッキ3
0とを備えてなる構造であって、前記両面コア材25は
前記第1貫通孔29と同心状であって前記内層導体パタ
ーン23,24を含む両面コア材25を貫通する第2貫
通孔31と、該第2貫通孔31表面及び内層導体パター
ン23,24表面を被覆する第2銅メッキ32とを有
し、該第2銅メッキ32表面が前記第1銅メッキ30に
て被覆されてなる構造からなる。
The structure of the multilayer printed wiring board is shown in FIG.
As shown in (d), the outer layer conductor pattern 2 serving as the first layer
, A double-sided core material (inner substrate) 25 having inner and outer conductor patterns 23 and 24 serving as second and third layers, and an outer conductor pattern serving as a fourth layer Second single-sided core material (outer layer substrate) 27 having 26
And an adhesive layer (insulating layer) 28 interposed between the single-sided core members 22 and 27 and the double-sided core material 25, a first through hole 29 penetrating therethrough, a surface of the first through hole 29, First copper plating 3 covering surfaces of outer conductor patterns 21 and 26
0, wherein the double-sided core material 25 is concentric with the first through-hole 29 and extends through the double-sided core material 25 including the inner-layer conductor patterns 23 and 24. And a second copper plating 32 covering the surface of the second through-hole 31 and the surface of the inner conductor patterns 23 and 24, and the surface of the second copper plating 32 is covered with the first copper plating 30. Consists of a structure.

【0028】前記片面コア材22,27は、それぞれベ
ース基材(外層ベース基材)22′,27′の一表面に
外層導体パターン21,26が形成され、該外層導体パ
ターン21,26を含む片面コア材22,27を貫通す
る貫通部が形成されてなる。
The single-sided core members 22, 27 have outer conductor patterns 21, 26 formed on one surface of base materials (outer base materials) 22 ', 27', respectively, and include the outer conductor patterns 21, 26. A penetrating portion penetrating the single-sided core members 22 and 27 is formed.

【0029】前記両面コア材25は、ベース基材(内層
ベース基材)25′の表裏面に内層導体パターン23,
24が形成され、該内層導体パターン23,24を含む
両面コア材25を貫通する第2貫通孔31が形成され、
該第2貫通孔31内壁表面及び内層導体パターン23,
24表面に第2銅メッキ32が施されてなる。即ち、該
第2貫通孔31とその内壁表面を被覆する第2銅メッキ
32とで互いの内層導体パターン23,24を接続する
内層接続用スルーホール33を構成している。前記片面
コア材22,27と両面コア材25とは、前記片面コア
材22,27の貫通部と前記両面コア材25の内層接続
用スルーホール33の互いの中心軸を合わせて積層され
て多層プリント配線基板としての一つの貫通孔29が形
成され、その表面を第1金属メッキ30にて被覆するこ
とにより、内層導体パターン23,24と外層導体パタ
ーン21,26とを接続してなる。即ち、前記第1貫通
孔29とその内壁表面を被覆する第1銅メッキ30とで
内層導体パターン23,24と外層導体パターン21,
26とを接続するスルーホール34を構成している。
The double-sided core material 25 is provided on the front and back surfaces of a base material (inner layer base material) 25 'with an inner conductor pattern 23,
24, and a second through hole 31 penetrating the double-sided core material 25 including the inner conductor patterns 23 and 24 is formed.
The inner wall surface of the second through hole 31 and the inner conductor pattern 23;
The second copper plating 32 is applied to the surface of the substrate 24. That is, the second through hole 31 and the second copper plating 32 covering the inner wall surface constitute an inner layer connection through hole 33 for connecting the inner conductor patterns 23 and 24 to each other. The single-sided core members 22 and 27 and the double-sided core member 25 are laminated with the central axes of the through-holes of the single-sided core members 22 and 27 and the through-holes 33 for connecting the inner layer of the double-sided core member 25 aligned. One through hole 29 as a printed wiring board is formed, and the surface thereof is covered with a first metal plating 30 to connect the inner conductor patterns 23 and 24 and the outer conductor patterns 21 and 26. That is, the first through-hole 29 and the first copper plating 30 covering the inner wall surface form the inner conductor patterns 23 and 24 and the outer conductor patterns 21 and 24.
26 are formed.

【0030】以下、上記多層プリント配線基板の製造工
程を説明する。
Hereinafter, the manufacturing process of the multilayer printed wiring board will be described.

【0031】まず、図2(a)に示すように内層回路と
なる未加工の連続した銅箔23′,24′をベース基材
25′の表裏面に積層した両面コア材25を用意し、図
2(b)に示すように該両面コア材25の所定位置に所
定径の貫通孔31をドリル等により形成する。
First, as shown in FIG. 2 (a), a double-sided core material 25 is prepared by laminating unprocessed continuous copper foils 23 'and 24' serving as an inner layer circuit on the front and back surfaces of a base material 25 '. As shown in FIG. 2B, a through hole 31 having a predetermined diameter is formed at a predetermined position of the double-sided core material 25 by a drill or the like.

【0032】次に、図2(c)に示すように前記貫通孔
31内壁表面及び銅箔23′,24′表面全体に無電界
及び電界銅メッキ32を施し、内層接続用スルーホール
33を形成する。これによって前記銅箔23′,24′
が電気的に接続される。
Next, as shown in FIG. 2 (c), an electric field-free and electric field copper plating 32 is applied to the inner wall surface of the through hole 31 and the entire surface of the copper foils 23 ', 24' to form a through hole 33 for connecting the inner layer. I do. Thereby, the copper foils 23 ', 24'
Are electrically connected.

【0033】次に、図2(d)に示すように前記銅箔2
3′,24′及びその表面に形成された銅メッキ32を
エッチング等により必要な内層導体パターン23,24
に形成する。
Next, as shown in FIG.
3 ', 24' and the copper plating 32 formed on the surface thereof are etched to form necessary inner layer conductor patterns 23, 24.
Formed.

【0034】次に、図1(a)に示すように内層導体パ
ターン23,24及び内層接続用スルーホール33を形
成した両面コア材25の表裏面側にそれぞれ、前記内層
接続用スルーホール33と対応する位置に該スルーホー
ル33に対して同心状且つ同径状の貫通部28aを有す
る接着シート28′と、外層回路となる未加工の連続し
た銅箔21′,26′をベース基材22′,27′の一
表面に積層し、同じく該スルーホール30に対して同心
状且つ同径上の貫通部22a,27aを有する片面コア
材22,27とを順次積層し、この後これらを加熱しな
がら圧力を加えて図1(b)に示すように積層し、貫通
孔29を有する一枚の積層板35を形成する。
Next, as shown in FIG. 1A, the inner-layer connection through-holes 33 and 24 and the inner-layer connection through-holes 33 are formed on the front and back surfaces of the double-sided core material 25, respectively. An adhesive sheet 28 'having a penetrating portion 28a concentric and the same diameter with respect to the through hole 33 at a corresponding position, and unprocessed continuous copper foils 21' and 26 'serving as an outer layer circuit are attached to the base substrate 22. , 27 ′, and single-sided core members 22, 27 having through-holes 22 a, 27 a concentric and of the same diameter with respect to the through-hole 30. While applying pressure, the layers are laminated as shown in FIG. 1B to form one laminated plate 35 having the through holes 29.

【0035】この状態では、内層回路と外層回路とが未
接続であるので、次に図1(c)に示すように貫通孔2
9内壁表面及び外層の銅箔21′,26′表面全体に無
電解及び電解銅メッキ30を施す。この段階で内層回路
と外層銅箔21′,26′とがスルーホール34によっ
て電気的に接続される。
In this state, since the inner layer circuit and the outer layer circuit are not connected, as shown in FIG.
9. Electroless and electrolytic copper plating 30 is applied to the inner wall surface and the entire surface of the outer copper foils 21 'and 26'. At this stage, the inner circuit and the outer copper foils 21 ', 26' are electrically connected by the through holes 34.

【0036】最後に、図1(d)に示すように、外層の
銅箔21′,26′及びその表面に施された銅メッキ3
0をエッチング等により必要な外層導体パターン21,
26に形成され、4層プリント配線基板が得られる。
Finally, as shown in FIG. 1D, the outer copper foils 21 'and 26' and the copper plating 3
0 is a necessary outer layer conductor pattern 21 by etching or the like.
26 to obtain a four-layer printed wiring board.

【0037】このように、本実施例の多層プリント配線
基板によれば、内層接続用スルーホール33(具体的に
は第2銅メッキ32)が第1貫通孔29内壁に露出して
内層回路の接続部となり、その接続面積が従来の貫通孔
内壁に露出する内層導体パターンの厚み分の断面のみの
接続面積に比較して大幅に増加し、内層導体パターン2
1,26の厚みが薄くなった場合においても高い接続信
頼性を得ることができる。
As described above, according to the multilayer printed wiring board of this embodiment, the through holes 33 (specifically, the second copper plating 32) for connecting the inner layer are exposed on the inner wall of the first through hole 29, and the inner layer circuit is formed. The connection area increases significantly as compared with the connection area of only the cross section corresponding to the thickness of the conventional inner conductor pattern exposed on the inner wall of the through-hole.
High connection reliability can be obtained even when the thickness of the first and the second 26 is reduced.

【0038】また、内層ベース基材25′,外層ベース
基材22′,27′の孔加工時に内層導体パターン2
3,24断面,外層導体パターン21,26断面等にス
ミアが発生しても、図3に示すように内層導体パターン
23,24と外層導体パターン21,26との主な接続
は、内層導体パターン23,24表面、第2銅メッキ3
2、第1銅メッキ30、外層導体パターン21,26表
面を通じて行われるため、前記スミアによって接続信頼
性が損なわれることが無い。図中、36はスミアであ
る。
Also, when the inner layer base material 25 'and the outer layer base materials 22' and 27 'are drilled, the inner layer conductor pattern 2' is formed.
Even if smears occur in the cross sections 3 and 24 and the cross sections of the outer conductor patterns 21 and 26, the main connection between the inner conductor patterns 23 and 24 and the outer conductor patterns 21 and 26 is made as shown in FIG. 23, 24 surface, second copper plating 3
2. Since the first copper plating 30 is performed through the surface of the outer conductor patterns 21 and 26, the connection reliability is not impaired by the smear. In the figure, 36 is a smear.

【0039】このため、内層導体パターン23,24の
ファインパターン化や多層プリント配線基板の薄型化、
即ち導体パターン21,23,24,26の薄型化(特
に、銅箔厚み:18μm以下)、スルーホール34の小
径化(特に、孔径:0.4φ〜0.2φ)によるスルー
ホール接続部の断線を防止できる。
For this reason, fine patterning of the inner conductor patterns 23 and 24, thinning of the multilayer printed wiring board,
That is, the conductor patterns 21, 23, 24, and 26 are made thinner (especially, copper foil thickness: 18 μm or less), and the diameter of the through holes 34 is reduced (especially, the hole diameters: 0.4 to 0.2 φ), thereby breaking the connection portions of the through holes. Can be prevented.

【0040】図4は、本発明の他の実施例よりなる多層
プリント配線基板を示す断面図である。本実施例につい
て、上記実施例と相違する点のみ説明する。
FIG. 4 is a sectional view showing a multilayer printed wiring board according to another embodiment of the present invention. In the present embodiment, only the points different from the above embodiment will be described.

【0041】該多層プリント配線基板は、接着剤層28
及び外層基板である片面コア材22,27の貫通部28
a,22a,27a孔径を内層基板である両面コア材2
5の内層接続用スルーホール33の孔径よりも大きくし
てなる構造、逆に言うと内層コア材25の内層接続用ス
ルーホール33の孔径を小径としてなる構造である。
The multi-layer printed wiring board has an adhesive layer 28
And the penetrating portions 28 of the single-sided core members 22 and 27 as the outer layer substrates
a, 22a, 27a Double-sided core material 2 as inner layer substrate
5 is a structure in which the hole diameter of the through hole 33 for the inner layer connection is larger than the hole diameter of the through hole 33 for the inner layer connection.

【0042】これにより、スルーホール34内において
段ができ、内層コア材25の内層導体パターン23,2
4表面を被覆する第2銅メッキ32の一部が露出するこ
とになり、内層接続用スルーホール33における第2銅
メッキ部分と併せて第1銅メッキ30と電気的に接続さ
れるので、上記実施例と比較してより高い接続信頼性を
得ることができる。
Thus, a step is formed in the through hole 34, and the inner conductor patterns 23, 2 of the inner core material 25 are formed.
Since the part of the second copper plating 32 covering the four surfaces is exposed and is electrically connected to the first copper plating 30 together with the second copper plating part in the through hole 33 for the inner layer connection, Higher connection reliability can be obtained as compared with the embodiment.

【0043】図5は、本発明のさらに他の実施例よりな
る多層プリント配線基板を示す断面図である。本実施例
について、図1及び図2に示す実施例と相違する点のみ
説明する。
FIG. 5 is a sectional view showing a multilayer printed wiring board according to still another embodiment of the present invention. This embodiment will be described only with respect to differences from the embodiment shown in FIGS.

【0044】該多層プリント配線基板は、内層基板であ
る両面コア材25に複数個の内層接続用スルーホールを
形成し、該内層接続用スルーホールに対応する位置にス
ルーホール34を形成するものと形成しないものとを混
在させることによりインナーバイアホール(IVH)3
7付きの多層プリント配線基板を実現することができ
る。
The multilayer printed wiring board has a plurality of through holes for connection to the inner layer formed in the double-sided core material 25 which is an inner layer substrate, and a through hole 34 formed at a position corresponding to the through hole for connection to the inner layer. The inner via hole (IVH) 3
A multilayer printed wiring board with 7 can be realized.

【0045】なお、上記実施例においては、4層プリン
ト配線基板を用いて説明したが、本発明は上記実施例に
限らず、例えば内層基板や接着材層の数を適宜増減した
り、内層基板を片面コア材とすることにより、3層、5
層、6層、それ以上の層数の多層プリント配線板にも応
用できる。
Although the above embodiment has been described using a four-layer printed wiring board, the present invention is not limited to the above-described embodiment. For example, the number of inner layers and the number of adhesive layers may be appropriately increased or decreased, or By using a single-sided core material,
The present invention can also be applied to a multilayer printed wiring board having six, six, or more layers.

【0046】また、外層コア材を両面コア材とし上記実
施例の両面コア材と同構成としても良い。
The outer core material may be a double-sided core material and may have the same structure as the double-sided core material of the above embodiment.

【0047】さらに、上記実施例において、片面コア材
22,27に代わって外層導体パターン22,26のみ
の構成としても良い。
Further, in the above embodiment, only the outer conductor patterns 22, 26 may be used instead of the single-sided core members 22, 27.

【0048】[0048]

【発明の効果】以上説明したように、本発明は、あらか
じめ内層基板に設けられた内層接続用スルーホールの内
壁表面に、内層導体パターンと外層導体パターンとの接
続用のスルーホールが重なる構造であるので、内層回路
とスルーホールとの接続面積が大幅に増加し、内層導体
パターンの厚みを薄くした場合においても高い接続信頼
性が得られる。また、内層ベース基材,外層ベース基材
等の孔加工時に内層導体パターン断面,外層導体パター
ン断面等にスミアが発生しても、層間の接続信頼性が損
なわれることが無い。
As described in the foregoing, the present onset Ming, the inner wall surface of the inner connecting through hole provided in advance inner layer board, the through hole for connection to the innerlayer conductor pattern and the outer layer conductor pattern overlaps structure Therefore, the connection area between the inner layer circuit and the through hole is greatly increased, and high connection reliability can be obtained even when the thickness of the inner layer conductor pattern is reduced. Also, even if smears occur in the inner layer conductor pattern cross section, the outer layer conductor pattern cross section, or the like at the time of drilling holes in the inner layer base material, the outer layer base material, etc., the connection reliability between the layers is not impaired.

【0049】このため、内層回路のファインパターン化
や、多層プリント配線基板の薄型化、スルーホールの小
径化に対応してなる多層プリント配線基板が得られる。
Therefore, a multilayer printed wiring board corresponding to a fine pattern of the inner layer circuit, a thinner multilayer printed wiring board, and a smaller through hole diameter can be obtained.

【0050】さらに、本発明の請求項記載の多層プリ
ント配線基板は、内層導体パターンの表面を被覆する第
2金属メッキが第1貫通孔内に露出することになり、さ
らに高い接続信頼性が得られる。
Further, in the multilayer printed wiring board according to the third aspect of the present invention, the second metal plating covering the surface of the inner conductor pattern is exposed in the first through hole, so that higher connection reliability is achieved. can get.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例よりなる多層プリント配線基
板の構造及びその製造工程の後半工程を示す断面図であ
る。
FIG. 1 is a sectional view showing a structure of a multilayer printed wiring board according to an embodiment of the present invention and a latter half of a manufacturing process thereof.

【図2】同じく多層プリント配線基板の製造工程の前半
工程を示す断面図である。
FIG. 2 is a cross-sectional view showing a first half of a manufacturing process of the multilayer printed wiring board.

【図3】図1に示す実施例においてスミア発生時の状態
を説明するための断面図である。
FIG. 3 is a cross-sectional view for explaining a state when smear occurs in the embodiment shown in FIG. 1;

【図4】本発明の他の実施例よりなる多層プリント配線
基板を示す断面図である。
FIG. 4 is a sectional view showing a multilayer printed wiring board according to another embodiment of the present invention.

【図5】本発明のさらに他の実施例よりなる多層プリン
ト配線基板を示す断面図である。
FIG. 5 is a sectional view showing a multilayer printed wiring board according to still another embodiment of the present invention.

【図6】従来の多層プリント配線基板の製造工程の前半
工程を示す断面図である。
FIG. 6 is a cross-sectional view showing the first half of a conventional multi-layer printed wiring board manufacturing process.

【図7】同じく多層プリント配線基板の構造及びその製
造工程の後半工程を示す断面図である。
FIG. 7 is a sectional view showing the structure of the multilayer printed wiring board and the latter half of the manufacturing process.

【図8】図7に示す従来の多層プリント配線基板におい
てスミア発生時の状態を説明するための斜視図である。
8 is a perspective view for explaining a state when smear occurs in the conventional multilayer printed wiring board shown in FIG. 7;

【符号の説明】[Explanation of symbols]

21,26 外層導体パターン 22,27 片面コア材(外層基板) 22′,27′ 外層ベース基材 23,24 内層導体パターン 25 両面コア材(内層基板) 25′ 内層ベース基材 28 接着剤層(絶縁層) 29 第1貫通孔 30 第1金属メッキ 31 第2貫通孔 32 第2金属メッキ 33 内層接続用スルーホール 21, 26 Outer conductor pattern 22, 27 Single-sided core material (outer substrate) 22 ', 27' Outer base material 23, 24 Inner conductor pattern 25 Double-sided core material (inner substrate) 25 'Inner base material 28 Adhesive layer ( Insulating layer) 29 first through hole 30 first metal plating 31 second through hole 32 second metal plating 33 through hole for inner layer connection

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 内層ベース基材の少なくとも一表面に内
層導体パターンが形成されてなる内層基板と、該内層基
板の表裏面に絶縁層を介して積層される外層導体パター
ンと、これらを貫通する第1貫通孔と、該第1貫通孔表
面及び前記外層導体パターン表面を覆う第1金属メッキ
とを備えてなる多層プリント配線基板において、 前記内層基板は、連続した銅箔が表面に積層された内層
ベース基材に前記第1貫通孔と略同心状の第2貫通孔が
形成された後に、該第2貫通孔内壁表面及び前記内層ベ
ース基材表面の銅箔表面全体に無電解及び電解メッキが
施されて第2金属メッキが形成されてから、前記内層ベ
ース基材表面の銅箔及び該銅箔表面に形成された第2金
属メッキがエッチングにより内層導体パターンに形成さ
れ、 該内層基板表面の内層導体パターンに絶縁層を介して外
層パターンとなる銅箔が積層された後に、前記第2貫通
孔内壁表面及び前記外層パターンとなる銅箔表面全体に
無電解及び電解メッキが施されて第1金属メッキが形成
されてから、前記外層パターンとなる銅箔及び該銅箔表
面に形成された第1金属メッキがエッチングにより外層
導体パターンに形成されてなる ことを特徴とする多層プ
リント配線基板。
1. An inner layer substrate in which an inner layer conductor pattern is formed on at least one surface of an inner layer base substrate, an outer layer conductor pattern laminated on front and back surfaces of the inner layer substrate via an insulating layer, and penetrates these. In a multilayer printed wiring board comprising: a first through hole; and a first metal plating covering a surface of the first through hole and a surface of the outer layer conductor pattern, the inner layer substrate has a continuous copper foil laminated on a surface thereof. Inner layer
A second through hole substantially concentric with the first through hole is formed in the base material.
After being formed, the inner wall surface of the second through hole and the inner layer base are formed.
Electroless and electrolytic plating on the entire copper foil surface
After forming the second metal plating, the inner layer base is formed.
Copper foil on the base material surface and second gold formed on the copper foil surface
Metal plating is formed on the inner conductor pattern by etching.
And the outer conductor pattern on the inner substrate surface is interposed via an insulating layer.
After the copper foil serving as the layer pattern is laminated, the second penetration
On the inner wall surface of the hole and the entire surface of the copper foil to be the outer layer pattern
Electroless and electrolytic plating applied to form first metal plating
After that, the copper foil to be the outer layer pattern and the copper foil table
The first metal plating formed on the surface is etched to form an outer layer
A multilayer printed wiring board formed on a conductor pattern .
【請求項2】 前記第2貫通孔及びその表面を覆う第2
金属メッキとからなる内層接続用スルーホールの孔径を
前記第1貫通孔の孔径と略同径としてなること特徴とす
る請求項1記載の多層プリント配線基板。
2. A second cover for covering the second through hole and its surface.
The hole diameter of the through hole for inner layer connection consisting of metal plating
2. The multilayer printed wiring board according to claim 1, wherein the diameter of the first through hole is substantially the same as the diameter of the first through hole .
【請求項3】 前記第2貫通孔及びその表面を覆う第2
金属メッキとからなる内層接続用スルーホールの孔径を
前記第1貫通孔の孔径よりも小径としてなること特徴と
する請求項1記載の多層プリント配線基板。
3. A second cover for covering the second through-hole and the surface thereof.
The hole diameter of the through hole for inner layer connection consisting of metal plating
2. The multilayer printed wiring board according to claim 1, wherein the diameter of the first through hole is smaller than the diameter of the first through hole .
【請求項4】 連続した銅箔が内層ベース基材の表裏面
に積層された内層両面コア材に貫通孔を形成し、 該貫通孔内壁表面及び前記内層ベース基材表裏面の銅箔
表面全体に無電解及び電解銅メッキを施し、 前記内層ベース基材表裏面の銅箔及び該銅箔表面に形成
された銅メッキをエッチングにより内層導体パターンに
形成し、 前記内層両面コア材に形成された貫通孔と同心状の貫通
部を有する接着シートと、連続した銅箔が外層ベース基
材の表面に積層され前記内層両面コア材に形成された貫
通孔と同心状の貫通部を有する外層コア材とを、前記内
層両面コア材の内層導体パターン側に順次積層した後、
加熱しながら圧力を加えて積層板を形成し、 前記内層両面コア材に形成された貫通孔と前記接着シー
トの貫通部と前記外層コア材の貫通部との内壁表面及び
前記外層ベース基材表面の銅箔表面全体に無電解及び電
解銅メッキを施し、 前記外層ベース基材表面の銅箔及び該銅箔表面に形成さ
れた銅メッキをエッチングにより外層導体パターンに形
成することを特徴とする多層プリント配線基板の製造方
4. A continuous copper foil is formed on both sides of an inner layer base material.
A through-hole is formed in an inner-layer double-sided core material laminated on the substrate, and a copper foil on the inner wall surface of the through-hole and the front and back surfaces of the inner-layer base material
Electroless and electrolytic copper plating on the entire surface to form on the copper foil on the front and back surfaces of the inner layer base material and on the surface of the copper foil
Etched copper plating into inner layer conductor pattern
Formed and penetrated concentrically with the through holes formed in the inner layer double-sided core material
Adhesive sheet with a continuous section and a continuous copper foil
Formed on the inner layer double-sided core material laminated on the surface of the material.
A through hole and an outer layer core material having a concentric through portion;
After sequentially laminating on the inner layer conductor pattern side of the layer double-sided core material,
A laminate is formed by applying pressure while heating, and the through holes formed in the inner layer double-sided core material and the adhesive sheet are formed.
Inner wall surfaces of the through portion of the outer core material and the through portion of the outer layer core material;
Electroless and electroless over the entire copper foil surface on the outer layer base substrate surface
Copper plating is applied to form a copper foil on the surface of the outer layer base material and a surface of the copper foil.
Etched copper plating into outer layer conductor pattern by etching
Manufacturing method of multilayer printed wiring board characterized by comprising
Law .
JP6812695A 1995-03-27 1995-03-27 Multilayer printed wiring board and method of manufacturing the same Expired - Fee Related JP3165617B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6812695A JP3165617B2 (en) 1995-03-27 1995-03-27 Multilayer printed wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6812695A JP3165617B2 (en) 1995-03-27 1995-03-27 Multilayer printed wiring board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH08264952A JPH08264952A (en) 1996-10-11
JP3165617B2 true JP3165617B2 (en) 2001-05-14

Family

ID=13364752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6812695A Expired - Fee Related JP3165617B2 (en) 1995-03-27 1995-03-27 Multilayer printed wiring board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3165617B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6731708B1 (en) 1997-12-17 2004-05-04 Nec Corporation Clock signal control device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140073757A (en) * 2012-12-07 2014-06-17 타이코에이엠피(유) Printed circuit board and manufacture method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6731708B1 (en) 1997-12-17 2004-05-04 Nec Corporation Clock signal control device

Also Published As

Publication number Publication date
JPH08264952A (en) 1996-10-11

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