JP2763020B2 - Semiconductor package and semiconductor device - Google Patents

Semiconductor package and semiconductor device

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Publication number
JP2763020B2
JP2763020B2 JP7103812A JP10381295A JP2763020B2 JP 2763020 B2 JP2763020 B2 JP 2763020B2 JP 7103812 A JP7103812 A JP 7103812A JP 10381295 A JP10381295 A JP 10381295A JP 2763020 B2 JP2763020 B2 JP 2763020B2
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semiconductor
conductive protrusions
semiconductor package
surface
package
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JPH08306743A (en
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一隆 庄司
修一 松田
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日本電気株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/0555Shape
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    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13006Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
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    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体パッケージ、特に、半導体導体チップの一表面と実質上等しいサイズを有するチップサイズパッケージに関すると共に、半導体パッケージに半導体チップを実装した半導体装置、及び、プリント基板に実装するための実装構造、並びに、 The present invention relates to a semiconductor package, in particular, with about the chip size package having one surface and substantially equal size of the semiconductor conductor chip, a semiconductor device mounting the semiconductor chip in the semiconductor package, and the printed circuit board mounting structure for mounting to, and,
実装方法に関する。 On how to implement.

【0002】 [0002]

【従来の技術】一般に、この種の半導体パッケージは、 In general, semiconductor packages of this type,
特願平6−110857号に記載されているように、当該パッケージに搭載、実装される半導体チップと実質的に同様なサイズを有しており、半導体パッケージを半導体チップに取り付けることにより、半導体装置を構成している。 As described in Japanese Patent Application No. Hei 6-110857, mounted on the package, has a semiconductor chip substantially the same size to be mounted, by mounting the semiconductor package on a semiconductor chip, a semiconductor device constitute a. 具体的に述べると、半導体パッケージを有する半導体装置は、ポリイミド等によって形成された絶縁フィルムを接着剤を介して、半導体チップの電極パッド部分を除く表面を覆うと共に、絶縁フィルムに設けられた配線には、半導体チップの電極パッドと電気的に接続された導電性突起物(以下、バンプと呼ぶ)が設けられている。 To be specific, a semiconductor device having a semiconductor package, an insulating film formed of polyimide or the like via an adhesive, covers the surface except the electrode pads of the semiconductor chip, the wiring provided in the insulating film the electrode pads electrically connected to the conductive protrusions of the semiconductor chip (hereinafter, referred to as bumps) are provided. 尚、絶縁フィルム上の配線は、カバーコートによって被覆されている。 The wiring on the insulating film is covered by a cover coat.

【0003】これらバンプは、マトリックス状に絶縁フィルムの配線上に、カバーコートから突出する形で配列されている。 [0003] These bumps, on the wiring of the matrix on the insulating film, are arranged in a manner projecting from the cover coat.

【0004】このような半導体パッケージを有する半導体装置は、実際上、半導体チップと同じ面積で、マザーボード等の基板上に実装できるため、小さな面積の基板に多数の半導体装置を実装できるという利点がある。 [0004] The semiconductor device having such a semiconductor package is effectively the same area as the semiconductor chip, it is possible to mount on a substrate such as a motherboard, can be advantageously implemented a number of semiconductor devices on a substrate of a small area .

【0005】 [0005]

【発明が解決しようとする課題】一方、半導体パッケージを有する半導体装置においても、将来、半導体チップ上の電極パッドの数を増加させることにより、多ピン化が図られることが予測される。 [SUMMARY OF THE INVENTION Meanwhile, in the semiconductor device having a semiconductor package, the future, by increasing the number of electrode pads on the semiconductor chip, the number of pins can be achieved is predicted. このような電極パッドの数の増加に対処するためには、バンプの数を増加させること、並びに、バンプのサイズを極力小さくすることが必要であり、また、半導体チップ上の電極パッド部を結ぶ配線も、微細化する必要がある。 To address the increase in the number of such electrode pads, increasing the number of bumps, as well, it is necessary to minimize the size of the bump, also connects the electrode pad portion of the semiconductor chip wiring must also be miniaturized.

【0006】このように、多ピン化のためにバンプのサイズを小さくすると、バンプと、絶縁フィルム上に設けられるランドとの間の接合強度が低下すること、及び、 [0006] Thus, reducing the size of the bumps for the number of pins, the bonding strength between the bump and the land provided on the insulating film is reduced, and,
配線の微細化により、ノイズが発生することも予測される。 The miniaturization of the wiring, is also predicted that noise is generated.

【0007】また、半導体パッケージ上にバンプが突出した状態の半導体装置が完成すると、バンプの表面は自然に酸化され、表面にナチュラルオキサイド膜(自然酸化膜)が形成される。 Further, when the semiconductor device in a state where the bumps are projected on the semiconductor package is completed, the surface of the bump is oxidized naturally, natural oxide film on the surface (natural oxide film) is formed. このように、ナチュラルオキサイド膜が形成された状態で、配線の正常性を試験するために、通常、プローブを各バンプに接触させることにより電気試験、即ち、導通試験が行われている。 Thus, in a state in which natural oxide film is formed, in order to test the normality of the wiring, usually electrical test by contacting a probe on each of the bumps, i.e., the continuity test is being performed. この電気試験の場合、各バンプ上に形成されたナチュラルオキサイド膜をプローブによって破ることが必要になるが、バンプの大きさが小さくなると、プローブを個々のプローブに接触させることが難しくなり、結果的に、正確に電気試験を行うことが困難になってしまう。 For the electrical test, the natural oxide film formed on the bumps it is necessary to break the probe, the size of the bump is reduced, it becomes difficult to contact the probe to the individual probes, resulting in, it becomes difficult to perform an accurate electrical test. また、正確な電気試験を行うために、小さなバンプにプローブを必要以上に強く接触させた場合、バンプが大きく変形するという問題が発生する。 Further, in order to perform an accurate electrical test, when contacted strongly than necessary to probe a small bump, bump is a problem that greatly deformed.

【0008】更に、半導体パッケージを有する半導体装置をプリント基板上に実装する場合、バンプをリフローさせ、プリント基板上の導体層と接合させている。 Furthermore, when mounting the semiconductor device having a semiconductor package on a printed circuit board, the bump is reflowed, thereby bonding the conductor layer on the printed circuit board. このリフロー後に行う温度サイクル試験、及び、実際に製品として使用されている間に、バンプのサイズが小さくなるにしたがって、基板と絶縁フィルムとの間の熱膨張率の違いのため、バンプが絶縁フィルム上のランドとの接合部で破断する可能性が高くなってしまう。 Temperature cycle test performed after the reflow, and, while it is actually used as a product, according to the size of the bump is reduced, because of the difference in thermal expansion coefficient between the substrate and the insulating film, bumps insulating film possibility of breakage at the junction of the land above increases.

【0009】また、バンプを突出させた半導体装置を基板上に実装する場合、実装後、半導体装置と基板との間の接合強度を強化するために、実装された半導体装置と基板との間に接着樹脂を注入し、バンプの周囲をこの接着樹脂によって囲むことも行われているが、接着樹脂の注入後、半導体チップの不良、或いは、異常が検出されても、不良、異常の検出された半導体チップだけを取り替えることはできない状況にある。 [0009] In the case of mounting a semiconductor device with protruding bumps on the substrate, after mounting, in order to enhance the bonding strength between the semiconductor device and the substrate, between the mounted semiconductor device and the substrate the adhesive resin is injected, it has also been possible to surround the bump by the adhesive resin, after injection of the adhesive resin, defective semiconductor chip, or even abnormal is detected, failure was anomaly detection there is a situation where it is not possible to replace only the semiconductor chip.

【0010】本発明の目的は、半導体パッケージを有する半導体装置において、バンプの多数化に対処でき、且つ、バンプの多数化に伴う上記した諸問題を解決できる半導体パッケージ、半導体パッケージを有する半導体装置、並びに、半導体装置の実装構造を提供することである。 An object of the present invention is to provide a semiconductor device having a semiconductor package, can cope with a large number of bumps, and a semiconductor package, a semiconductor device having a semiconductor package which can solve the problems mentioned above due to the large number of bumps, and to provide a mounting structure of a semiconductor device.

【0011】本発明の他の目的は、バンプが小さくなっても正確に、バンプを変形させることなく、電気試験を行うことができるプローブ装置を提供することである。 Another object of the present invention, exactly even bump is reduced, without deforming the bump is to provide a probe device which can perform electrical tests.

【0012】本発明の更に他の目的は、微細化した半導体パッケージが使用されても、リフロー後に行う温度サイクル試験、及び、実際に製品として使用されている間に、バンプの破断等が生じない半導体装置を提供することである。 Still another object of the present invention may be used a semiconductor package is miniaturized, the temperature cycle test carried out after reflow, and, while it is actually used as a product, breakage of the bumps do not occur it is to provide a semiconductor device.

【0013】本発明の他の目的は、一旦、基板等に実装され、接着樹脂が注入された後でも、半導体チップを取り替えることができる半導体装置の実装方法を提供することである。 Another object of the present invention, once mounted on a substrate or the like, even after the adhesive resin is injected, is to provide a mounting method of a semiconductor device which can replace the semiconductor chip.

【0014】 [0014]

【課題を解決するための手段】本発明の一態様によれば、半導体チップの一表面と実質上等しいサイズを有し、前記半導体チップの前記一表面を覆うように取り付けられる半導体パッケージにおいて、それぞれビアホールを有すると共に、配線を施された複数枚の絶縁フィルムと、各絶縁フィルム上の配線を電気的に接続するためのビアホール配線と、前記複数枚の絶縁フィルムの最外層から突出した導電性突起物とを有し、前記複数枚の絶 According to one aspect of the present invention According to an aspect of having a one surface and substantially equal size of the semiconductor chip, in the semiconductor package that is attached to cover the one surface of the semiconductor chip, respectively and having a via hole, and a plurality of insulating films having been subjected to wire, wire and electrically via hole wirings for connecting on respective insulating films, conductive protrusions protruding from the outermost layer of the plurality of insulating films and a goods, absolute of said plurality
縁フィルムの内、少なくとも一枚の絶縁フィルム上に Among edge film, at least one of the insulating films on the
は、当該絶縁フィルムに隣接した半導体チップ及び絶縁 The semiconductor chip and the insulating adjacent to the insulating film
フィルムのいずれか一方上の独立した複数の配線と、前 A plurality of wires independent of the one of the film, before
記複数のビアホール配線を介して、電気的に接続される Serial through a plurality of via holes wires are electrically connected
と共に、残りのビアホールに施された配線とは電気的に With, the rest of the via hole decorated with wiring electrically
絶縁されている単一の配線が施されており、前記単一の And a single wire is subjected is insulated, the single
配線には、同一の電位が与えられる半導体パッケージが得られる。 Wiring a semiconductor package in which the same potential is applied can be obtained.

【0015】本発明の他の態様によれば、一方向に突出した導電性突起物を有する半導体パッケージと、前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、前記半導体パッケージが取り付けられた半導体装置を前記導電性突起物を基板に接触させることにより実装した半導体装置の実装構造において、前記基板と前記半導体パッケージとの間には、前記導電性突起物を囲むように、熱可塑性樹脂層が設けられており、該熱可塑性樹脂層を形成する熱可塑性樹脂は前記導電性突起物と実質的に等しい溶解温度を有している半導体装置の実装構造が得られる。 According to another aspect of the invention, includes a semiconductor package having a conductive protrusions protruding in one direction, and a semiconductor chip having a first surface having said semiconductor package substantially the same area, the on one surface, wherein the mounting structure of the semiconductor device mounted by a semiconductor device in which a semiconductor package is mounted contacting the conductive protrusions on the substrate, between the substrate and the semiconductor package, the as surround the conductive protrusions, the thermoplastic resin layer is provided, the semiconductor device thermoplastic resin forming the thermoplastic resin layer having the conductive protrusions is substantially equal to the dissolution temperature mounting structure is obtained.

【0016】更に、本発明の別の態様によれば、一方向に突出した導電性突起物を有する半導体パッケージと、 Furthermore, according to another aspect of the present invention, a semiconductor package having a conductive protrusions protruding in one direction,
前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、 Wherein a semiconductor chip having a first surface having a semiconductor package substantially the same area, on the one surface,
前記半導体パッケージが取り付けられた半導体装置を前記導電性突起物を基板に接触させることにより実装する半導体装置の実装方法において、前記導電性突起物を囲むように、前記導電性突起物と実質的に等しい溶解温度を有する熱可塑性樹脂によって、前記半導体パッケージの表面を覆っておき、前記基板に実装する際、前記導電性突起物のリフローと同時に、前記熱可塑性樹脂を溶解させることにより、前記導電性突起物の前記基板への実装と、前記半導体パッケージの前記基板への接着とを同時的に行う半導体装置の実装方法が得られる。 In the above method for mounting a semiconductor device to be implemented by a semiconductor device in which a semiconductor package is mounted contacting the conductive protrusions on the substrate, so as to surround the conductive protrusions, the conductive protrusions and substantially a thermoplastic resin having an equal dissolution temperature in advance to cover the surface of the semiconductor package, when mounted on the substrate, simultaneously with the reflow of the conductive protrusions, by dissolving the thermoplastic resin, the conductive implementation and to the substrate of the projection, the mounting method of the semiconductor package of the adhesive and the semiconductor device which performs simultaneously the to the substrate is obtained.

【0017】また、本発明のもう一つの態様によれば、 [0017] Also, according to another aspect of the present invention,
一方向に突出した導電性突起物を有する半導体パッケージと、前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、前記半導体パッケージが取り付けられた半導体装置を試験するためのプローブ装置において、単一の前記導電性突起物に対して、複数箇所において接触できるような微小突起を備えているプローブ装置が得られる。 It includes a semiconductor package having a conductive protrusions protruding in one direction, and a semiconductor chip having a first surface having said semiconductor package substantially the same area, on the one surface, wherein the semiconductor package is attached a probe apparatus for testing a semiconductor device, for a single said conductive protrusions, the probe apparatus is obtained and a microprotrusions that allows contact at a plurality of locations.

【0018】 [0018]

【実施例】以下、図面を参照して、本発明の実施例について説明する。 EXAMPLES Hereinafter, with reference to the drawings, a description will be given of an embodiment of the present invention.

【0019】図1を参照すると、本発明の一実施例に係る半導体パッケージ20は、半導体チップ21の一表面と実質上同じ面積を有しており、半導体チップ21の一表面に被着して使用される。 Referring to FIG. 1, a semiconductor package 20 according to an embodiment of the present invention has substantially the same area as a surface of the semiconductor chip 21, and applied to one surface of the semiconductor chip 21 used. 図示された例では、半導体チップ21の一表面上には、複数の電極パッド22が設けられており、これら電極パッド22以外の半導体チップ21の表面は接着剤層23によって覆われており、半導体パッケージ20は、接着剤層23を介して、半導体チップ21の表面上に被着されている。 In the illustrated example, on one surface of the semiconductor chip 21, a plurality of electrode pads 22 are provided, the surface of the semiconductor chip 21 other than these electrode pads 22 is covered with an adhesive layer 23, a semiconductor package 20 via an adhesive layer 23, it is deposited on the surface of the semiconductor chip 21.

【0020】図示された半導体パッケージ20は、ポリイミドの絶縁フィルム層25を備え、図示された絶縁フィルム層25は複数層(ここでは、3層)の絶縁フィルム25a、25b(図2及び図3参照)、及び25cによって形成されている。 The semiconductor package 20 illustrated comprises a polyimide insulating film layer 25 (here, three layers) multiple layer insulating film layer 25 which is shown insulating film 25a of, 25b (see FIGS. 2 and 3 ), and it is formed by 25c. 各絶縁フィルム25a〜25c Each of the insulating film 25a~25c
には、それぞれビアホール27が形成されると共に、配線29が形成されている。 The, the via hole 27 respectively are formed, the wiring 29 is formed. これら配線29は、ビアホール配線、接地配線、信号配線、及び電源配線に区分することができ、このうち、接地配線及び電源配線は、半導体チップ21の複数の電極パッド22に電気的に接続されているが、最終的には、共通にしても良い。 These wires 29, a via hole wiring, can be classified into the ground wiring, the signal wiring, and power, of which, the ground wiring and power, are electrically connected to the plurality of electrode pads 22 of the semiconductor chip 21 there is, in the end, it may be in common.

【0021】図示された例では、接着剤層23上に設けられた第1層の絶縁フィルム25aに、配線29が施されており、この配線29は、半導体チップ21上の各電極パッド22に対して、ビアホール配線を介して電気的に接続されている。 [0021] In the illustrated example, the insulating film 25a of the first layer provided on the adhesive layer 23, the wiring 29 is subjected, the wiring 29, the respective electrode pads 22 on the semiconductor chip 21 in contrast, it is electrically connected through a via hole interconnect. 更に、第2層の絶縁フィルム25b Furthermore, the second layer insulation film 25b
には、第1層の絶縁フィルム25aの各配線29に接続された配線29と、ビアホール配線とを有している。 , The wiring 29 connected to the wires 29 of the insulating film 25a of the first layer, and a via-hole wiring. また、絶縁フィルム層25の最外層である第3層の絶縁フィルム25cには、第2層の絶縁フィルム25b上の配線29に電気的に接続された導電性突起物、即ち、バンプ31が形成され、これらバンプ31はプリント基板(図示せず)等に、直接、ボンディングされ、所望の半導体機器を構成することができる。 Also, the insulating film 25c of the third layer is the outermost layer of the insulating film layer 25, electrically connected to conductive protrusions on the wiring 29 on the insulating film 25b of the second layer, i.e., the bump 31 is formed is, these bumps 31 (not shown) printed circuit board or the like, directly, are bonded, can form a desired semiconductor device.

【0022】ここで、半導体チップ21上の電極パッド22の数が多くなると、それに応じて、バンプ31の数も増加させる必要があるが、バンプ31は、基板との接続の関係上、ある程度の間隔(例えば、500ミクロン)をおいて配列する必要がある。 [0022] Here, the number of electrode pads 22 on the semiconductor chip 21 is increased, accordingly, the number of bumps 31 also needs to be increased, the bumps 31, the connection between the substrate relationship, a certain interval (e.g., 500 microns) is required to be arranged at a. したがって、電極パッドの数に比較して、バンプの数を減少させることが望ましい。 Therefore, compared with the number of electrode pads, it is desirable to reduce the number of bumps.

【0023】この実施例では、絶縁フィルム25を多層構造にすることによって、バンプ31の数を電極パッド22の数に比較して少なくすることができる。 [0023] In this embodiment, it is possible by the insulating film 25 in the multilayer structure, reduced by comparing the number of bumps 31 on the number of the electrode pads 22.

【0024】図2及び図3を参照すると、図1の実施例を更に具体的に説明するための平面図であり、図2には、第1層の絶縁フィルム25aの上の配線が示されており、他方、図3には、第2層の絶縁フィルム25b上の配線が示されている。 Referring to FIGS. 2 and 3 are plan views for explaining an embodiment in more detail in FIG. 1, FIG. 2, the wiring on the insulating film 25a of the first layer is shown and, on the other hand, in FIG. 3, the wiring on the insulating film 25b of the second layer is shown.

【0025】図2において、第1層の絶縁フィルム25 [0025] In FIG. 2, the first layer insulation film 25
a上の配線には、4つの接地配線29gが含まれており、各接地配線29gは、接地電極パッドによって終端されている。 The wiring on a, contains four ground wiring 29g, the ground wiring 29g is terminated by the ground electrode pads. また、図示された配線25a中には、4つの電源配線29dが設けられており、これら電源配線2 Further, during the wiring 25a which is illustrated, it is provided with four power wires 29d, these power lines 2
9dは電源電極パッドによって終端されている。 9d is terminated by the power supply electrode pads. 残りの配線は、各種信号の送受を行うための信号配線である。 The remaining wires are signal lines for transmitting and receiving various signals.

【0026】図3に示された配線は、図2に示された配線と対応しており、ここでは、第2層の絶縁フィルム2 The interconnection shown in FIG. 3 corresponds to the wiring shown in FIG. 2, where, in the second layer insulation film 2
5b上の全体に亘って形成された接地配線層29g1によって構成されている。 It is constituted by the ground wiring layer 29g1 formed throughout on 5b. この場合、第1層の絶縁フィルム25a上の各接地配線29gとビアホール配線(破線)を介して電気的に接続されており、この接地配線層29g1は、図2の信号配線及び電源配線29dのビアホール位置に対応した位置には、形成されていない。 In this case, are electrically connected via the respective ground wires 29g and the via-hole wiring on the insulating film 25a of the first layer (dashed line), the ground wiring layer 29g1 are signal wiring and power 29d in FIG. 2 at positions corresponding to the via hole position is not formed. この結果、第2層の絶縁フィルム25b上には、信号配線用のビアホール配線29v1及び電源配線用ビアホール配線29v2とが露出した状態となっている。 As a result, on the insulating film 25b of the second layer, in a state where the via hole interconnect 29v1 and power wiring via hole wiring for signal lines 29v2 exposed.

【0027】したがって、第2層の絶縁フィルム25b [0027] Thus, the second layer insulation film 25b
上の電極パッド数は第1層の絶縁フィルム25a上の電極パッド数に比較して少なくできる。 Electrode pads number of above can be reduced compared to the number of the electrode pads on the insulating film 25a of the first layer.

【0028】また、第3層の絶縁フィルム25c上に、 Further, on the insulating film 25c of the third layer,
図3と同様にして、電極配線層を形成すれば、電源配線に必要な電極パッド数をも減少させることができ、したがって、最上層上に突出されるバンプの数を大幅に減らすことが可能である。 In the same way as in FIG. 3, by forming the electrode wiring layer, it can also reduce the number of electrode pads required power wiring, therefore, possible to reduce the number of bumps protruding on the uppermost layer significantly it is. 更に、図3に示すように、接地配線層29g1を含ませることにより、半導体チップ21 Furthermore, as shown in FIG. 3, by including a grounding wiring layer 29G1, the semiconductor chip 21
を電磁気的にシールドするシールド効果も持たせることが可能になる。 The it is possible to electromagnetically shield shielding effect have.

【0029】以上述べたことからも明らかなように、半導体パッケージ20は、絶縁フィルムを多層にすることにより、半導体チップ21の電極パッド数が増加しても、半導体パッケージ20から突出するバンプの数は、 [0029] As is clear from what has been said above, the semiconductor package 20, by an insulating film in a multilayer, even the electrode pad number of the semiconductor chips 21 is increased, the number of bumps projecting from the semiconductor package 20 It is,
電極パッド数よりも少なくでき、半導体チップ20の多ピン化に対応できる。 It can be reduced than the number of electrode pads, can respond to multiple pins of the semiconductor chip 20. 更に、必要な配線を多層に分けることができるため、配線の自由度を上げることができ、 Furthermore, it is possible to divide the wiring necessary multilayer, it is possible to increase the degree of freedom of the wiring,
結果として、配線密度を下げることができる。 As a result, it is possible to reduce the wiring density.

【0030】図4を参照すると、本発明の他の実施例に係る半導体パッケージは、パッケージ上に形成されるバンプの構造によって特徴づけられる。 Referring to FIG 4, the semiconductor package according to another embodiment of the present invention is characterized by the structure of the bumps formed on the package. 図4において、半導体パッケージの一部を形成する絶縁フィルム25の外側表面に、銅等の電極パッド35が形成されており、この電極パッド35は、周辺部において絶縁性のカバーコート36によって部分的に覆われている。 4, on the outer surface of the insulating film 25 which forms part of a semiconductor package, electrode pads 35 of copper or the like have been formed, the electrode pad 35 is, in part by a cover coat 36 of insulation at the periphery It is covered in. したがって、 Therefore,
電極パッド35上に直接バンプを取り付けた場合、電極パッド35との接続部において、バンプの径は小さくなってしまい、結果として、バンプが電極パッド35との接続部で破断してしまう現象が観測された。 If mounted directly bump to the electrode pad 35 on, the connection between the electrode pads 35, the diameter of the bump becomes small, as a result, bumps observed phenomenon that broken at the connecting portion between the electrode pad 35 It has been.

【0031】この実施例は、上記したバンプの破断を防止するためのものである。 [0031] This embodiment is intended to prevent breakage of the bumps as described above. まず、この実施例では、カバーコート36を選択的に除去することにより、電極パッド35の中央部を露出させた後、レジストを塗布する。 First, in this embodiment, by selectively removing the cover coat 36, after exposing the central portion of the electrode pad 35, a resist is applied.
続いて、このレジストを部分的に除去して、電極パッド35及びこの電極パッド35の周辺におけるカバーコート36を部分的に露出させる。 Subsequently, the resist is partially removed to expose the cover coat 36 in the vicinity of the electrode pads 35 and the electrode pad 35 partially. このレジスト除去領域は、電極パッド35の露出領域より広い面積を有している。 The resist removal region has a larger area than the exposed region of the electrode pads 35. 具体的には、電極パッド35の径が80μmの場合、レジスト除去領域の径は200〜300μmであることが望ましい。 Specifically, when the diameter of the electrode pads 35 is 80 [mu] m, the diameter of the resist removal area is preferably a 200-300 [mu] m.

【0032】次に、レジスト除去領域には、無電解メッキ、又は、蒸着により、銅の下地層38が被着され、レジストが残された状態になる。 Next, the resist removal area, electroless plating, or by vapor deposition, an underlayer 38 of copper is deposited, a state where the resist is left. 以後、必要な処理が施された後、最終的に、半田バンプ40が形成される。 Thereafter, after the necessary processing has been performed, and finally, the solder bumps 40 are formed. この例では、半田片を下地層38にのせて加熱して溶解させ、表面張力によりボール状の半田バンプ40を形成する方法が採用されている。 In this example, was dissolved by heating to put the solder pieces on the base layer 38, a method of forming a ball-shaped solder bumps 40 are employed by the surface tension. 尚、半田バンプ40は、錫又は鉛によって形成され、200〜300μmの径を有すると共に、100〜250μmの高さを有している。 The solder bump 40 is formed by a tin or lead, which has a diameter of 200-300 [mu] m, and has a height of 100 to 250 [mu] m.

【0033】上記したことからも明らかな通り、この実施例は、下地層38によって半田バンプ40のランドを拡大したことと等価である。 [0033] As clear from the above, this embodiment is equivalent to the enlarged land of the solder bumps 40 by the underlying layer 38.

【0034】図5を参照して、本発明の更に他の実施例に係る半導体パッケージのバンプ構造を説明する。 [0034] With reference to FIG. 5, illustrating a further bump structure of a semiconductor package according to another embodiment of the present invention. 図5 Figure 5
に示されたバンプ構造は、半導体パッケージの一部を形成する絶縁フィルム25の外側表面に、周辺を部分的に、カバーコート36によって覆われた電極パッド35 Bump structure shown, the outside surface of the insulating film 25 which forms part of a semiconductor package, a peripheral partially, the electrode pads 35 covered by the cover coat 36
が設けられていることは、図4の例と同様である。 It is similar to the example of FIG. 4 which is provided. この例では、銅の下地層38´が半球形を有している点で、 In this example, in that the copper underlayer 38 'has a semi-spherical,
図4と異なっており、このような半球形の下地層38´ 4 and are different, the base layer of such a hemispherical 38 '
も、電解メッキによって容易に形成できる。 It can also be easily formed by electroplating. また、半球形の下地層38´上には、図4の場合と同様に、最終工程において、錫また鉛の半田バンプ40が半田片を加熱、溶融する方法によって形成されている。 Further, on the underlying layer 38 'of the hemispherical, as in the case of FIG. 4, in the final step, the tin also heat the solder bumps 40 are solder pieces of lead are formed by a method of melt.

【0035】図4及び図5に示された実施例では、半田バンプ40の電極パッド38との接触面を実質上拡大できるため、半導体パッケージの温度サイクル試験で、半田バンプ40が破断するのを防止できた。 [0035] In the embodiment shown in FIGS. 4 and 5, it is possible to substantially enlarge the contact surface between the electrode pads 38 of the solder bumps 40, a temperature cycle test of a semiconductor package, solder bumps 40 from being broken It could be prevented. したがって、 Therefore,
半導体パッケージの耐温度サイクル性を向上させることができた。 It was possible to improve the temperature cycle resistance of the semiconductor package.

【0036】尚、半田バンプ40のピッチが500μm [0036] In addition, the pitch of the solder bump 40 is 500μm
の時、半田バンプ40の径は100〜300μmの範囲で自由に選択できるという利点もある。 When, the diameter of the solder bump 40 is also an advantage that can be freely selected in the range of 100 to 300 [mu] m. また、図4及び図5の実施例は、半田バンプ40をプリント基板等に実装後、樹脂封止しない半導体機器に特に適している。 Further, the embodiment of FIGS. 4 and 5, after mounting the solder bump 40 on a printed circuit board or the like, are particularly suitable for a semiconductor device which is not resin sealing.

【0037】図6(A)及び(B)を参照して、本発明の他の実施例に係る半導体装置及びその実装方法について説明する。 [0037] with reference to FIGS. 6 (A) and (B), a description will be given of a semiconductor device and a mounting method thereof according to another embodiment of the present invention. 図示された半導体装置は、半導体チップ2 The semiconductor device shown, the semiconductor chip 2
1、及び、半導体チップ21の一表面と実質的に同じサイズを有し、当該一表面に接着剤によって取り付けられた半導体パッケージ20とによって構成されている。 1, and has a first surface substantially the same size of the semiconductor chip 21 is constituted by the semiconductor package 20 mounted by adhesive to the one surface. 半導体チップ21上には、電極パッド35が形成されており、半導体パッケージ20は、半導体チップ21の表面に接着剤により被着された絶縁フィルム25を有している。 On the semiconductor chip 21 has electrode pads 35 are formed, the semiconductor package 20 includes a deposition has been insulated film 25 with an adhesive to the surface of the semiconductor chip 21.

【0038】また、電極パッド35には、図の下方向に向けられた半田バンプ40が取り付けられている点では、他の実施例と同様である。 Further, the electrode pads 35, in that the solder bumps 40 directed downward in FIG attached is similar to the other embodiments.

【0039】このように、電極パッド35に、直接、半田バンプ40を取り付けただけでは、半田バンプ40の付け根部分における応力が非常に弱いことが確認された。 [0039] Thus, the electrode pads 35, directly, just fitted with a solder bump 40, it was confirmed stresses at the base portion of the solder bumps 40 is very weak.

【0040】このため、この実施例では、図6(A)に示すように、半田バンプ40の付け根部分に樹脂層45 [0040] Therefore, in this embodiment, as shown in FIG. 6 (A), the resin layer at the base portion of the solder bumps 40 45
を塗布して、半田バンプ40の付け根部分における接合強度を補強している。 The by coating, reinforces the bonding strength in the base portion of the solder bumps 40.

【0041】この樹脂層45を形成する樹脂としては、 [0041] As the resin for forming the resin layer 45,
熱硬化性樹脂、及び、熱可塑性樹脂のいずれでも良い。 Thermosetting resin, and it may be either a thermoplastic resin.
このように、電極パッド35との接合部分を樹脂層45 Thus, resin bonding portion between the electrode pad 35 layer 45
によって補強された半導体装置は、図6(B)に示すように、半田バンプ40によりプリント基板46上にボンディングされた場合、プリント基板46上の導体層(図示せず)に、強い接合強度でボンディングされると共に、半導体パッケージ20側における半田バンプ40の破断等も観測されなかった。 Semiconductor device reinforced by, as shown in FIG. 6 (B), when it is bonded on the printed circuit board 46 by solder bumps 40, the conductor layer on the printed circuit board 46 (not shown), a strong bonding strength while being bonded, breakage of the solder bumps 40 of the semiconductor package 20 side was observed.

【0042】ここで、樹脂層45を形成する樹脂として、加熱によってリフローする熱可塑性樹脂が使用された場合、半導体装置を加熱して樹脂層45を半田バンプ40共にリフローさせることにより、半導体パッケージ20を半田バンプ40から機械的に切り離すことができる。 [0042] Here, as the resin for forming the resin layer 45, if the thermoplastic resin reflow by heating is used, by heating the semiconductor device to the resin layer 45 solder bump 40 together reflow, the semiconductor package 20 can be mechanically disconnected from the solder bump 40. これは、図示された例の場合、半田バンプ40だけで、半導体パッケージ20とプリント基板46との間の電気的接続並びに機械的接合が行われているためである。 This is the case of the illustrated example, only the solder bumps 40, because the electric connection and mechanical bonding between the semiconductor package 20 and the printed circuit board 46 is performed.

【0043】このことは、半導体装置がプリント基板4 [0043] This semiconductor device is a printed circuit board 4
6上に搭載された後、半導体チップ21の不良が検出された場合、半導体チップ21を正常なチップと取替え、 After being mounted on the 6, if the defective semiconductor chip 21 is detected, replace the semiconductor chip 21 and the normal chip,
半導体チップのリペアが可能であることを意味している。 Which means that the semiconductor chip of the repair is possible. このように、半導体チップを取替えてリペアできることは、プリント基板46上に搭載される半導体装置の数が多くなればなる程、非常に有効である。 Thus, it can be repaired by replacing the semiconductor chip, as the number of semiconductor devices mounted on the printed circuit board 46 is The more, is very effective.

【0044】図7(A)〜(G)を参照して、上記した半導体チップの実装動作および取替え動作を説明する。 [0044] With reference to FIG. 7 (A) ~ (G), explaining the mounting operation and replacement operation of the semiconductor chip as described above.
まず、図7(A)に示された半導体装置は、図6(A) First, the semiconductor device shown in FIG. 7 (A), FIG. 6 (A)
と同様に、半導体チップ21、絶縁フィルム25、半田バンプ40、及び、半田バンプ40の周辺に被覆された樹脂層45とを有している。 Similarly, the semiconductor chip 21, the insulating film 25, the solder bumps 40, and a resin layer 45 coated on the periphery of the solder bumps 40 and. この実施例では、樹脂層4 In this embodiment, the resin layer 4
5は、単に、半田バンプ40を補強するだけでなく、接着材としても作用している。 5 is simply not only reinforce the solder bumps 40, which also acts as an adhesive. また、樹脂層45は、キュア前の状態では、高い流動性を持ち、キュア後の状態では、−40〜125℃の温度範囲で、接着力を有し、且つ、半田の溶融温度では接着力が低下する樹脂によって形成されている。 Further, the resin layer 45, in the cure state before has a high fluidity, in the state after the curing, a temperature range of -40 to 125 ° C., have an adhesive strength, and adhesive strength in solder melting temperature There is formed of a resin to decrease. このような樹脂には、熱可塑性ポリイミド系、またはフッ素系樹脂がある。 Such resins, thermoplastic polyimide or fluororesin.

【0045】図7(A)に示された半導体装置は、図7 The semiconductor device shown in FIG. 7 (A), FIG. 7
(B)に示すように、プリント基板46上の導体層48 (B), the conductive layer 48 on the printed circuit board 46
上に半田バンプ40が位置するように戴置される。 Solder bumps 40 are the placing to be positioned above. その後、半田の溶融温度、且つ、熱可塑性樹脂の接着力が低下する温度まで加熱される。 Thereafter, solder melting temperature, and the adhesive force of the thermoplastic resin is heated to a temperature to decrease. そうすると、半田バンプ4 Then, solder bump 4
0が溶融し、プリント基板46上の導体層48とボンディングされると同時に、プリント基板46と絶縁フィルム25とが熱可塑性樹脂45によって接着される。 0 is melted at the same time being bonded to the conductor layer 48 on the printed circuit board 46 are adhered by the insulating film 25 are thermally plastic resin 45 and the printed circuit board 46.

【0046】つまり、1度の加熱で、半田バンプ40のボンディングと絶縁フィルム25の接着とを同時に行うことができる。 [0046] That is, in one degree of heating, it is possible to perform the bonding of the solder bumps 40 and the adhesive of the insulating film 25 at the same time.

【0047】その後、プリント基板46上にボンディングされた状態で、半導体チップ21の不良が検出されると、図7(C)に示すように、半導体チップ21の裏面に、加熱・吸着治具51が配置され、半田バンプ40の溶融温度近傍まで加熱される。 [0047] Then, in a state of being bonded on the printed circuit board 46, the defective semiconductor chip 21 is detected, as shown in FIG. 7 (C), the back surface of the semiconductor chip 21, heat-suction jig 51 There is disposed, is heated to melting temperature near the solder bumps 40. 加熱の結果、樹脂層45 Result of the heating, the resin layer 45
はリフローして、絶縁フィルム25との接着力が低下し、且つ、半田バンプ40の半導体パッケージとの接着力も低下する。 Is reflowed, it reduces the adhesive force between the insulation film 25, and the adhesive strength of the semiconductor package of the solder bump 40 is also reduced. 結果として、半田バンプ40は、半導体パッケージから容易に取り外すことができる状態になる。 As a result, the solder bump 40 is ready to be removed easily from the semiconductor package. また、この状態では、プリント基板46側に、樹脂が溶融、移動して、プリント基板46の表面と接触する一方、半田バンプ40の頂部は、露出した状態になる。 In this state, the printed circuit board 46 side, the resin is melted, moves while in contact with the surface of the printed circuit board 46, the top portion of the solder bump 40 is formed on the exposed state.

【0048】この状態では、図7(D)に示すように、 [0048] In this state, as shown in FIG. 7 (D),
半導体チップ21は絶縁フィルム25と共に半田バンプ40から簡単に取り外すことができる。 The semiconductor chip 21 may be easily removed from the solder bump 40 with the insulating film 25.

【0049】次に、図7(A)に示した半導体装置と同様な構成を有し、且つ、図7(E)に示すように、取り替えられるべき半導体装置を用意する。 Next, a semiconductor device and a structure similar to that shown in FIG. 7 (A), and, as shown in FIG. 7 (E), providing a semiconductor device to be replaced. ここで、取り替えられるべき半導体装置は、図7(A)と同様に、半導体チップ21a、絶縁フィルム25a、半田バンプ40 Here, the semiconductor device to be replaced, as in FIG. 7 (A), the semiconductor chip 21a, the insulating film 25a, the solder bumps 40
a、及び、半田バンプ40aを囲むように被着された樹脂層45aとを有している。 a, and, and a resin layer 45a which is deposited to surround the solder bumps 40a. この樹脂層45aも樹脂層45と同様に、キュア前の状態では、高い流動性を持ち、キュア後の状態では、−40〜125℃の温度範囲で、接着力を有し、且つ、半田の溶融温度では接着力が低下する樹脂によって形成されている。 Similar to the resin layer 45a even resin layer 45, the curing state before, has a high fluidity, in the state after the curing, a temperature range of -40 to 125 ° C., have an adhesive strength, and solder of the melting temperature is formed by a resin adhesive force decreases.

【0050】図7(E)に示すように、取り替えられるべき半導体装置の半田バンプ40aは、プリント基板4 [0050] As shown in FIG. 7 (E), the solder bumps 40a of the semiconductor device to be replaced, the printed circuit board 4
6上に残されている半田バンプ40上に搭載され、この状態で加熱される。 Is mounted on the solder bumps 40 on which is left on the 6, is heated in this state. この加熱によって、半田バンプ40 This heating, solder bump 40
と40a及び樹脂層45と45aとはリフローして、一体化される。 The a 40a and the resin layer 45 and 45a by reflowing, are integrated. このように、この実施例では、プリント基板46にマウントされた後、出荷検査時やユーザーが使用していて、半導体チップ21に不良が見付かった場合にも、良品の半導体チップ21aに取り替えることができるという利点がある。 Thus, in this embodiment, after being mounted on a printed circuit board 46, and are used by shipment inspection or when users, even when a defective is found in the semiconductor chip 21, be replaced by a semiconductor chip 21a of good there is an advantage that it can be.

【0051】換言すれば、樹脂層45、45aを形成する樹脂を半田バンプの溶融温度との関係で選択することにより、半導体チップをリペアできる。 [0051] In other words, by selecting the resin forming the resin layer 45,45a in relation to the melting temperature of the solder bumps can be repaired semiconductor chip.

【0052】図8を参照して、本発明の他の実施例に係る半田バンプ検査用プローブを説明する。 [0052] With reference to FIG. 8, the solder bump inspection probe according to another embodiment of the present invention. まず、半導体パッケージに使用される半田バンプ40は上記したように、100〜300μmの径を有し、且つ、500μm First, solder bumps 40 used for the semiconductor package as described above, has a diameter of 100 to 300 [mu] m, and, 500 [mu] m
のピッチで配列されている。 They are arranged at a pitch. また、半田バンプ40自身は、大気中に晒されるため、必然的にその表面は、薄い自然酸化膜(ナチュラルオキサイド膜)によって被覆された状態にある。 Further, the solder bump 40 itself, due to exposure to the atmosphere, inevitably its surface is in a state of being covered by a thin natural oxide film (natural oxide film). このため、半導体チップ21の特性を正確に測定するには、半田バンプ21上の自然酸化膜を破って半田バンプ40の導体部分に接触できるプローブが検査用として必要である。 Therefore, to accurately measure the characteristics of the semiconductor chip 21, a probe can contact the natural oxide film conductor portions of the solder bumps 40 to beat on the solder bump 21 is required for the inspection.

【0053】このため、通常、尖った先端を有するプローブが使用されているが、半田バンプ40のサイズ及びピッチが小さくなると、プローブを半田バンプ上に正確に位置決めするのが難しくなってしまう。 [0053] Therefore, usually a probe having a sharpened tip is used, the size and pitch of the solder bumps 40 is reduced, it becomes difficult to accurately position the probe on the solder bumps. また、平坦な先端を有するプローブでは、半田バンプ上の自然酸化膜を破れない場合が生じ、正確な測定ができないという欠点がある。 Further, the probe having a flat tip, occur may not break the natural oxide film on the solder bumps, there is a disadvantage that can not be accurately measured.

【0054】上記した点を考慮して、この実施例では、 [0054] In view of the above problems, in this embodiment,
半田バンプ検査用プローブとして、半田バンプ40の径の1/3以下のピッチで配列された複数の突起電極55 As the solder bump inspection probe, a plurality of projecting electrodes 55 which are arranged in one-third or less of the pitch diameter of the solder bumps 40
を直線上或いは十字型に配列したプローブを使用する。 Using probes arranged in a straight line or cross a.
ここで、各突起電極55は、半球状の断面形状を有している。 Here, each projection electrode 55 has a hemispherical cross-sectional shape.

【0055】このようなプローブを使用して半田バンプ40を検査する場合、プローブには、半田バンプ40よりも狭いピッチで、突起電極55が配列されているため、検査の際には、単一の半田バンプ40に対して3〜 [0055] When inspecting the solder bumps 40 by use of such a probe in the probe, a narrower pitch than the solder bumps 40, since the projection electrodes 55 are arranged, upon inspection, single 3 to the solder bump 40 of the
5個の突起電極55が接触することになる。 Five projection electrodes 55 are brought into contact. したがって、プローブと半田バンプ40との導通が確実に行われ、且つ、半田バンプ40と突起電極55とは点接触するため、確実に自然酸化膜を破ることができる。 Therefore, conduction between the probe and the solder bumps 40 is performed reliably, and, the solder bump 40 and the bump electrode 55 to point contact, can break reliably natural oxide film. また、 Also,
プローブの突起電極55は、半田バンプ40よりも広い範囲に設けられているため、位置合わせ精度が低くても、突起電極55と半田バンプ40との間の導通を確実に取ることができる。 Protrusion electrodes 55 of the probe, because it is provided in the range wider than the solder bump 40, even at low alignment accuracy can take to ensure conduction between the protrusion electrodes 55 and the solder bumps 40.

【0056】 [0056]

【発明の効果】本発明では、半導体チップの電極パッドの増加にも対処できる半導体パッケージが得られると共に、半導体装置をプリント基板に実装する際の半田バンプの半導体パッケージ側における破損等を防止できる半導体装置及びその実装方法が得られる。 In the present invention, can be prevented with a semiconductor package that can deal with an increase of the electrode pads of the semiconductor chip is obtained, a breakage in the semiconductor package side of the solder bumps when the semiconductor device is mounted on a printed circuit board semiconductor apparatus and mounting method thereof are obtained. また、実装後、 In addition, after the implementation,
不良半導体チップをリペアできる半導体装置及びその実装方法も得られる。 The semiconductor device and a mounting method thereof repairing a defective semiconductor chip can be obtained. 更に、半田バンプの導通試験を確実に行うことができるプローブも得られる。 Further, the probe can be obtained which can be reliably continuity test of the solder bumps. このように、 in this way,
本発明では、半導体パッケージの半田バンプに伴う諸問題を全て解消できるという利点がある。 In the present invention, it has the advantage of eliminating all the problems associated with solder bumps of the semiconductor package.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例に係る半導体装置の概略構成を説明するために使用される断面図である。 1 is a cross-sectional view used for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention.

【図2】図1に示された本発明の実施例をより詳細に説明するための平面図である。 2 is a plan view for explaining an embodiment in greater detail of the present invention shown in FIG.

【図3】図2とは異なる面上の配線を説明するための平面図である。 And [3] FIG. 2 is a plan view illustrating a wiring on different planes.

【図4】本発明の他の実施例に係る半導体装置を説明するための断面図である。 4 is a sectional view for explaining a semiconductor device according to another embodiment of the present invention.

【図5】図4の実施例を変形した例を示す断面図である。 5 is a sectional view showing an example in which a modification of the embodiment of FIG.

【図6】Aは本発明の他の実施例に係る半導体装置を示す断面図である。 [6] A is a sectional view showing a semiconductor device according to another embodiment of the present invention. Bは図6(A)に示された半導体装置の実装状態を示す断面図である。 B is a sectional view showing a mounting state of the semiconductor device shown in FIG. 6 (A).

【図7】A〜Fは本発明の他の実施例に係る半導体装置の実装方法を説明するための図である。 [7] A~F is a diagram for explaining a mounting method of a semiconductor device according to another embodiment of the present invention.

【図8】本発明の更に他の実施例に係る半導体装置検査用プローブを説明するための図図である。 8 is a further diagram view for explaining a semiconductor device inspection probe according to another embodiment of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

20 半導体パッケージ 21 半導体チップ 22、35 電極パッド 23 接着剤層 25 絶縁フィルム 29 配線 36 カバーコート 38 下地層 40 半田バンプ 45 樹脂層 46 プリント基板 48 導体層 51 加熱・吸着装置 55 突起電極 20 semiconductor package 21 semiconductor chips 22 and 35 electrode pads 23 adhesive layer 25 the insulating film 29 wirings 36 cover coat 38 underlayer 40 solder bump 45 resin layer 46 printed circuit board 48 conductive layer 51 heating and suction device 55 protruding electrodes

フロントページの続き (56)参考文献 特開 平8−236586(JP,A) 特開 平5−36889(JP,A) 特開 平4−37148(JP,A) 特開 平6−120296(JP,A) 特開 平2−253627(JP,A) 特開 平2−62056(JP,A) 特開 平6−69280(JP,A) (58)調査した分野(Int.Cl. 6 ,DB名) H01L 21/60 311 H01L 23/12 Following (56) references of the front page Patent flat 8-236586 (JP, A) JP flat 5-36889 (JP, A) JP flat 4-37148 (JP, A) JP flat 6-120296 (JP , a) JP flat 2-253627 (JP, a) JP flat 2-62056 (JP, a) JP flat 6-69280 (JP, a) (58 ) investigated the field (Int.Cl. 6, DB name) H01L 21/60 311 H01L 23/12

Claims (9)

    (57)【特許請求の範囲】 (57) [the claims]
  1. 【請求項1】 半導体チップの一表面と実質上等しいサイズを有し、前記半導体チップの前記一表面を覆うように取り付けられる半導体パッケージにおいて、それぞれビアホールを有すると共に、配線を施された複数枚の絶縁フィルムと、各絶縁フィルム上の配線を電気的に接続するためのビアホール配線と、前記複数枚の絶縁フィルムの最外層から突出した導電性突起物とを有し、前記複数枚の絶縁フィルムの内、少なくとも一枚の絶縁フィルム上には、 単一の配線が施されており、当該単一の配線 1. A having one surface and substantially equal size of the semiconductor chip, the semiconductor package mounted to cover the one surface of the semiconductor chip, which has a via hole, respectively, a plurality of which has been subjected to wire an insulating film, and the via-hole wirings for electrically connecting the wiring on the insulating film, and a conductive protrusions protruding from the outermost layer of the plurality of insulating films, the plurality of insulating films among them, at least one of the insulating films on, and a single wire is subjected, the single wire
    は、当該絶縁フィルムに隣接し、且つ、同一の電位が与 It is adjacent to the insulating film, and the same potential is given
    えられる互いに独立した複数の配線に対して 、前記複数のビアホール配線を介して、電気的に接続されると共に、残りのビアホールに施された配線とは電気的に絶縁されていることを特徴とする半導体パッケージ。 Erareru to a plurality of wirings mutually independent, through a plurality of via holes wirings is electrically connected, and characterized in that the decorated with lines to the rest of the via hole are electrically insulated semiconductor package to be.
  2. 【請求項2】 請求項1において、前記複数枚の絶縁フィルム上の配線に、シールド配線を含んでいることを特徴とする半導体パッケージ。 2. The method of claim 1, the semiconductor package, wherein the the plurality of insulating films on the wiring includes a shield wiring.
  3. 【請求項3】 請求項1において、前記絶縁フィルムの最外層から突出した導電性突起物は、前記最外層に設けられ、絶縁性のカバーコートによって部分的に覆われた電極パッド上に形成されており、且つ、前記電極パッドからカバーコート上に至る範囲に亘って被覆され、前記電極パッドの面積より広い面積を有する下地層と、該下地層上に形成された突起部とによって構成されていることを特徴とする半導体パッケージ。 3. The method of claim 1, conductive protrusions protruding from the outermost layer of the insulating film, the provided on the outermost layer, is formed on the partially covered on the electrode pads by covercoat insulating and, and, from said electrode pad is coated over a range extending on the cover coat, the underlying layer having a larger area than the area of ​​the electrode pad, is constituted by a protrusion formed on the underlayer semiconductor package, characterized in that there.
  4. 【請求項4】 請求項1において、前記導電性突起物は、樹脂によって囲まれていることを特徴とする半導体パッケージ。 4. The method of claim 1, wherein the conductive protrusions are, the semiconductor package characterized in that it is surrounded by resin.
  5. 【請求項5】 一方向に突出した導電性突起物を有する半導体パッケージと、前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、前記半導体パッケージが取り付けられた半導体装置を前記導電性突起物を基板に接触させることにより実装した半導体装置の実装構造において、前記基板と前記半導体パッケージとの間には、前記導電性突起物を囲むように、熱可塑性樹脂層が設けられており、該熱可塑性樹脂層を形成する熱可塑性樹脂は前記導電性突起物と実質的に等しい溶解温度を有していることを特徴とする半導体装置の実装構造。 A semiconductor package having a 5. A conductive protrusions protruding in one direction, and a semiconductor chip having a first surface having a substantially equal area and the semiconductor package, on the one surface, the semiconductor in the mounting structure of a semiconductor device mounted by allowing the semiconductor device package is mounted in contact with the conductive protrusions on the substrate, between the substrate and the semiconductor package, so as to surround the conductive protrusions , the thermoplastic resin layer is provided, the mounting structure of the semiconductor device thermoplastic resin forming the thermoplastic resin layer is characterized by having the conductive protrusions is substantially equal to the dissolution temperature .
  6. 【請求項6】 一方向に突出した導電性突起物を有する半導体パッケージと、前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、前記半導体パッケージが取り付けられた半導体装置を前記導電性突起物を基板に接触させることにより実装する半導体装置の実装方法において、前記導電性突起物を囲むように、前記導電性突起物と実質的に等しい溶解温度を有する熱可塑性樹脂によって、前記半導体パッケージの表面を覆っておき、前記基板に実装する際、前記導電性突起物のリフローと同時に、前記熱可塑性樹脂を溶解させることにより、前記導電性突起物の前記基板への実装と、前記半導体パッケージの前記基板への接着とを同時的に行うことを特徴とする半導体装置の実装方法。 A semiconductor package having a 6. A conductive protrusions protruding in one direction, and a semiconductor chip having a first surface having a substantially equal area and the semiconductor package, on the one surface, the semiconductor in the mounting method of a semiconductor device to be implemented by causing the semiconductor device package is mounted in contact with the conductive protrusions on the substrate, so as to surround the conductive protrusions is substantially equal lysis and the conductive protrusions a thermoplastic resin having a temperature in advance to cover the surface of the semiconductor package, when mounted on the substrate, simultaneously with the reflow of the conductive protrusions, by dissolving the thermoplastic resin, the conductive protrusions implementation of implementation and to the substrate, a semiconductor device which is characterized in that the adhesion to the substrate of the semiconductor package simultaneously.
  7. 【請求項7】 一方向に突出した導電性突起物を有する半導体パッケージと、前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、前記半導体パッケージが取り付けられた半導体装置を試験するためのプローブ装置において、単一の前記導電性突起物に対して、複数箇所において接触できるような微小突起を備えていることを特徴とするプローブ装置。 A semiconductor package having a 7. A conductive protrusions protruding in one direction, and a semiconductor chip having a first surface having a substantially equal area and the semiconductor package, on the one surface, the semiconductor a probe apparatus for testing a semiconductor device package is mounted, the probe device characterized by for a single of said conductive protrusions is provided with a small protrusion that can contact at a plurality of locations.
  8. 【請求項8】 半導体チップの一表面と実質上等しいサイズを有し、前記半導体チップの前記一表面を覆うように取り付けられる半導体パッケージにおいて、ビアホールを有すると共に、配線を施された絶縁フィルムと、前記絶縁フィルム上の配線を電気的に接続するためのビアホール配線と、前記絶縁フィルムから突出した導電性突起物とを有し、前記導電性突起物は、絶縁性のカバーコートによって部分的に覆われた電極パッド上に形成されており、且つ、前記電極パッドからカバーコート上に至る範囲に亘って被覆され、前記電極パッドの面積より広い面積を有する下地層と、該下地層上に形成された突起部とによって構成されていることを特徴とする半導体パッケージ。 8. having one surface and substantially equal size of the semiconductor chip, in the semiconductor package that is attached to cover the one surface of the semiconductor chip, an insulating film with, having been subjected to wiring with a via hole, and via-hole wirings for electrically connecting the wiring on the insulating film, wherein and a conductive protrusions projecting from the insulating film, the conductive protrusions are partly covered by the cover coating insulating It is formed on Broken electrode pads, and, from said electrode pad is coated over a range extending on the cover coat, the underlying layer having a larger area than the area of ​​the electrode pads, are formed on the underlayer semiconductor package, characterized in that it is constituted by the protruding portions.
  9. 【請求項9】 一方向に突出した導電性突起物を有する半導体パッケージと、前記半導体パッケージと実質上等しい面積を有する一表面を備えた半導体チップとを備え、当該一表面上には、前記半導体パッケージが取り付けられた半導体装置を前記導電性突起物を基板に接触させ、且つ、前記基板と前記半導体パッケージとの間には、前記導電性突起物を囲むように、前記導電性突起物と実質的に等しい溶解温度の熱可塑性樹脂層が設けられた半導体装置の実装構造を加熱することより、前記半導体チップを前記基板から取り外し、別の半導体チップに置き換えることにより、前記半導体チップのリペアすることを特徴とするリペア方法。 A semiconductor package having a 9. A conductive protrusions protruding in one direction, and a semiconductor chip having a first surface having a substantially equal area and the semiconductor package, on the one surface, the semiconductor the semiconductor device package is mounted in contact with the conductive protrusions on the substrate, and, between the substrate and the semiconductor package, so as to surround the conductive protrusions, the conductive protrusions and substantially than to the thermoplastic resin layer of equal dissolution thermally heats the mounting structure of the semiconductor device provided, remove the semiconductor chip from the substrate, by substituting a different semiconductor chips, to repair the semiconductor chip repair method according to claim.
JP7103812A 1995-04-27 1995-04-27 Semiconductor package and semiconductor device Expired - Fee Related JP2763020B2 (en)

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