JP2001217514A - Multi-layered wiring board - Google Patents

Multi-layered wiring board

Info

Publication number
JP2001217514A
JP2001217514A JP2000026346A JP2000026346A JP2001217514A JP 2001217514 A JP2001217514 A JP 2001217514A JP 2000026346 A JP2000026346 A JP 2000026346A JP 2000026346 A JP2000026346 A JP 2000026346A JP 2001217514 A JP2001217514 A JP 2001217514A
Authority
JP
Japan
Prior art keywords
insulating layer
wiring board
multilayer wiring
mounting surface
layer located
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000026346A
Other languages
Japanese (ja)
Inventor
Susumu Echigo
将 愛知後
Tadao Suzuki
忠男 鈴木
Yasuaki Matsunaga
泰明 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2000026346A priority Critical patent/JP2001217514A/en
Publication of JP2001217514A publication Critical patent/JP2001217514A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the connection reliability of a solder joint part by suppressing curvature deformation accompanying heating and cooling as to a multi-layered wiring board having surface-mounted components soldered on its mount surface. SOLUTION: The multi-layered wiring board 11 has on both the top and reverse sides of a core base material 14 a built-up layer formed by stacking two insulating layers 15a and 15b, and a built-up layer 16 formed by stacking two insulating layers 16a and 16b. A conductor pattern 17 is provided between both the top and reverse sides of the multi-layered wiring board 11 and the insulating layers and lands 17a corresponding to solder bumps 13 of a surface- mounted component 12 are provided on the mount surface. The surface-mounted component 12 is mounted on the lands 17a coated with solder paste so that the solder bumps 13 are mounted, and then soldered by solder flow heating. At this time, the insulating layers 15a and 15b on the mount surface side are formed of resin materials which have a larger modulus of elasticity or a smaller coefficient of thermal expansion than the insulating layers 16a and 16b on the opposite surface side.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、樹脂材料を主体と
した多層の絶縁層を有すると共に、表面及び前記絶縁層
間に導体パターンを有してなり、その表面を表面実装部
品が半田付けされる実装面とした多層配線基板に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a multilayer insulating layer mainly composed of a resin material, a conductor pattern between the surface and the insulating layer, and the surface is soldered to a surface mount component. The present invention relates to a multilayer wiring board having a mounting surface.

【0002】[0002]

【発明が解決しようとする課題】例えば携帯電話機等の
小型電子機器に組込まれる実装基板においては、図5に
示すように、多層配線基板(多層プリント配線板)1の
実装面(図で上面)に、例えばCSP(Chip Size Pack
age )タイプやBGA(Ball Grid Array )タイプとい
った小型,高密度の表面実装部品2をリフロー半田付け
により表面実装する構造が採用される。
For example, as shown in FIG. 5, in a mounting board incorporated in a small electronic device such as a mobile phone, a mounting surface (upper surface in the figure) of a multilayer wiring substrate (multilayer printed wiring board) 1 is used. In addition, for example, CSP (Chip Size Pack)
age) type or BGA (Ball Grid Array) type, a structure in which a small and high-density surface mount component 2 is surface mounted by reflow soldering.

【0003】前記多層配線基板1は、中心に位置するコ
ア基材3の表(上)側に、例えば2層の絶縁層4aから
なるビルドアップ層4を有すると共に、コア基材3の下
側にも、この場合2層の絶縁層5aからなるビルドアッ
プ層5を有して構成される。このとき、前記各絶縁層4
a,5aは、例えばガラスクロスを含有したエポキシ樹
脂から構成され、全て同等の材質及び厚みを有するもの
とされている。また、多層配線基板1の上下両面側及び
絶縁層間には、導体パターン6が形成されているのであ
るが、そのうち、多層配線基板1の実装面(図で上面)
には、前記表面実装部品2の底面の電極2aに設けられ
た半田バンプ7に対応したランド6aが形成されてい
る。
The multilayer wiring board 1 has a build-up layer 4 composed of, for example, two insulating layers 4a on the front (upper) side of the core substrate 3 located at the center. Also, in this case, it is configured to include the build-up layer 5 including the two insulating layers 5a. At this time, each of the insulating layers 4
a and 5a are made of, for example, epoxy resin containing glass cloth, and all have the same material and thickness. The conductor pattern 6 is formed between the upper and lower surfaces of the multilayer wiring board 1 and between the insulating layers. Of these, the mounting surface (the upper surface in the figure) of the multilayer wiring board 1 is included.
Are formed with lands 6a corresponding to the solder bumps 7 provided on the electrodes 2a on the bottom surface of the surface mount component 2.

【0004】この多層配線基板1に前記表面実装部品2
を実装するにあたっては、まず、多層配線基板1の実装
面のランド6aに、図示しない半田ペーストを例えばス
クリーン印刷により印刷塗布することが行なわれ、次い
で、図5(a)に示すように、多層配線基板1上に、表
面実装部品2が、その半田バンプ7が各ランド6aに合
致するようにマウントされる。そして、その多層配線基
板1をリフロー炉を通すことにより、前記半田ペースト
が溶融後硬化されて半田バンプ7のランド6aに対する
半田接合が行なわれるのである。
[0004] The surface mount component 2 is mounted on the multilayer wiring board 1.
Is mounted on the land 6a on the mounting surface of the multilayer wiring board 1 by, for example, screen-printing a solder paste (not shown), and then, as shown in FIG. The surface mount component 2 is mounted on the wiring board 1 such that the solder bumps 7 of the component 2 match the lands 6a. Then, by passing the multilayer wiring board 1 through a reflow furnace, the solder paste is melted and hardened, and solder bonding of the solder bumps 7 to the lands 6a is performed.

【0005】しかしながら、前記リフロー半田付けの工
程では、多層配線基板1が常温から次第に加熱されるプ
リヒート過程、ピーク温度(例えば230℃)まで加熱
されるリフロー過程、その後常温まで次第に冷却される
冷却過程が順に経られるのであるが、上記多層配線基板
1は、その構成要素(絶縁層4a,5aと導体パターン
6)間で熱膨張係数と弾性率が相違し、実装面側と反対
面側との間で導体パターン6の面積や形状,配置が不均
一である等の理由により、このリフロー工程において、
加熱膨張、冷却収縮に伴い、多層配線基板1に反り変形
といった変形挙動が発生する。例えば、加熱時におい
て、多層配線基板1に下方に凸状となるような反り変形
が発生し、冷却時に、それとは逆方向(戻り方向)であ
る上方に凸状となるような反り変形が発生する。
However, in the reflow soldering step, a preheating step in which the multilayer wiring board 1 is gradually heated from room temperature, a reflow step in which the multilayer wiring board 1 is heated to a peak temperature (for example, 230 ° C.), and a cooling step in which the multilayer wiring board 1 is gradually cooled to room temperature thereafter The multilayer wiring board 1 has different thermal expansion coefficients and elastic moduli between its constituent elements (insulating layers 4a, 5a and the conductor pattern 6), and the multilayer wiring board 1 has a difference between the mounting surface side and the opposite surface side. In the reflow process, the area, shape, and arrangement of the conductor pattern 6 are not uniform between
A deformation behavior such as a warp deformation occurs in the multilayer wiring board 1 due to the heating expansion and cooling contraction. For example, when the multilayer wiring board 1 is heated, a warp deformation that causes a downward convex shape is generated, and when the multilayer wiring board 1 is cooled, a warp deformation that causes an upwardly convex shape that is the opposite direction (return direction) occurs. I do.

【0006】このとき、前記半田ペーストは、冷却過程
の初期(例えば183℃以下)において硬化するので、
半田接合部による接合状態、つまり各ランド6aに対す
る各半田バンプ7の位置が拘束された状態で、図5
(b)に誇張して示すように、多層配線基板1に実装面
側に凸状となる方向の反り変形挙動が生ずる。そのた
め、冷却過程において、外側に位置する半田接合部に大
きな引張り応力が加わる問題がある。
At this time, the solder paste is hardened at an early stage of the cooling process (for example, at 183 ° C. or lower).
FIG. 5 shows a state in which the solder bumps 7 are joined by the solder joints, that is, the positions of the solder bumps 7 with respect to the lands 6a are restricted.
As shown in (b) in an exaggerated manner, the multilayer wiring board 1 has a warp deformation behavior in a direction convex toward the mounting surface side. Therefore, there is a problem that a large tensile stress is applied to the outer solder joints in the cooling process.

【0007】このように半田接合部に大きな応力が加わ
ると、半田接合部自身の破壊や、半田バンプ7と表面実
装部品2の電極2aとの界面、あるいは半田とランド6
aとの界面にて剥離が生ずる虞があり、ひいては接続信
頼性が低下する不具合があった。尚、このような多層配
線基板1の反り変形は、リフロー半田付け時に限らず、
実使用時にもその使用環境(温度変化が大きな環境)に
よって生ずる場合がある。
When a large stress is applied to the solder joint, the solder joint itself is destroyed, the interface between the solder bump 7 and the electrode 2a of the surface mount component 2, or the solder and the land 6 are damaged.
There is a possibility that peeling may occur at the interface with a, and as a result, there is a problem that connection reliability is reduced. Note that such warpage deformation of the multilayer wiring board 1 is not limited to reflow soldering,
Even during actual use, it may occur depending on the use environment (environment in which the temperature change is large).

【0008】本発明は上記事情に鑑みてなされたもの
で、その目的は、実装面に表面実装部品が半田付けされ
るものにあって、加熱,冷却に伴う反り変形を抑制し、
ひいては半田接合部の接続信頼性を向上させることがで
きる多層配線基板を提供するにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a device in which a surface mount component is soldered to a mounting surface, and suppress warpage deformation caused by heating and cooling.
It is another object of the present invention to provide a multilayer wiring board capable of improving the connection reliability of a solder joint.

【0009】[0009]

【課題を解決するための手段】表面及び多層の絶縁層間
に導体パターンを有する多層配線基板における、加熱、
冷却に伴う反り変形は、加熱時に絶縁層を構成する樹脂
材料のガラス転移点を越えた温度となることにより、絶
縁層の弾性率が大幅に低下し、その状態で、導体パター
ンの面積密度による熱膨張,収縮の大小が大きく支配す
るものと考えられる。またこのとき、半田接合部に対す
る引張り応力が問題となるのは、主として、冷却過程に
おいて、実装面側に凸状となる反り変形である。本発明
者等は、そのような絶縁層の弾性率に着目し、次の3つ
の手段により、実装面側とそれとは反対面側との間で絶
縁層の特性、特に弾性率を変化させることにより、反り
を抑制することが可能となることを確認し、本発明を成
し遂げたのである。
SUMMARY OF THE INVENTION In a multilayer wiring board having a conductor pattern between a surface and a multilayer insulating layer, heating,
The warping deformation accompanying cooling is caused by the temperature exceeding the glass transition point of the resin material constituting the insulating layer at the time of heating, whereby the elastic modulus of the insulating layer is significantly reduced, and in that state, the area density of the conductor pattern is reduced. It is considered that the degree of thermal expansion and contraction is dominant. Further, at this time, the problem of the tensile stress on the solder joint portion is mainly the warpage deformation which becomes convex on the mounting surface side in the cooling process. The present inventors pay attention to the elastic modulus of such an insulating layer, and change the characteristics of the insulating layer, particularly the elastic modulus, between the mounting surface side and the opposite surface side by the following three means. As a result, it has been confirmed that warpage can be suppressed, and the present invention has been accomplished.

【0010】即ち、第1の手段は、実装面側に位置する
絶縁層と、それとは反対側に位置する絶縁層との間で、
特性の異なる樹脂材料を採用したことを特徴としている
(請求項1の発明)。これによれば、導体パターンの面
積密度による熱膨張,収縮の大きい側の絶縁層と、熱膨
張,収縮の小さい側の絶縁層との間で、樹脂材料の特性
を変化させることによって、熱膨張,収縮の小さい側
を、熱膨張,収縮が大きくなる側に追従させ、反りの発
生を抑えることが可能となる。この結果、加熱,冷却に
伴う反り変形を抑制し、ひいては半田接合部の接続信頼
性を向上させることが可能となる。
That is, the first means is that an insulating layer located on the mounting surface side and an insulating layer located on the opposite side thereof have
It is characterized in that resin materials having different characteristics are employed (the invention of claim 1). According to this, by changing the characteristics of the resin material between the insulating layer on the side where thermal expansion and contraction is large due to the area density of the conductor pattern and the insulating layer on the side where thermal expansion and contraction is small, thermal expansion is achieved. , The side with a small contraction follows the side with a large thermal expansion and contraction, thereby suppressing the occurrence of warpage. As a result, it is possible to suppress the warp deformation due to heating and cooling, and to improve the connection reliability of the solder joint.

【0011】この場合、実装面側に位置する絶縁層を構
成する樹脂材料を、それとは反対側に位置する絶縁層よ
りも、弾性率の大きいもの又は熱膨張係数の大きいもの
とすることができる(請求項2の発明)。これにより、
実装面とは反対面側で熱膨張,収縮が大きい場合であっ
ても、その熱膨張,収縮に実装面側を追従させることが
でき、冷却収縮時における実装面側に凸状となる反り変
形を抑制することができる。ちなみに、本発明者等の研
究によれば、実装面側の絶縁層の弾性率を、反対面側の
絶縁層の弾性率の1.5倍以上、より好ましくは3倍以
上とすることにより、反り変形防止効果に優れたものと
なる。
In this case, the resin material constituting the insulating layer located on the mounting surface side can be one having a higher elastic modulus or a larger thermal expansion coefficient than the insulating layer located on the opposite side. (Invention of claim 2). This allows
Even if the thermal expansion and shrinkage is large on the side opposite to the mounting surface, the mounting surface can follow the thermal expansion and shrinkage, and the warping deformation becomes convex toward the mounting surface during cooling and shrinking. Can be suppressed. Incidentally, according to the study of the present inventors, by setting the elastic modulus of the insulating layer on the mounting surface side to 1.5 times or more, more preferably 3 times or more, the elastic modulus of the insulating layer on the opposite surface side, It is excellent in the effect of preventing warpage deformation.

【0012】前記実装面に表面実装部品をリフロー半田
付けするものにあっては、実装面側に位置する絶縁層
に、ガラス転移点がリフローピーク温度よりも高い樹脂
材料を採用することができる(請求項3の発明)。これ
により、リフロー半田付け工程の全温度領域において、
実装面側の絶縁層の弾性率が低下することがなくなり、
反り変形の抑制に効果的となる。
In the case where the surface mounting component is reflow-soldered to the mounting surface, a resin material having a glass transition point higher than a reflow peak temperature can be adopted for the insulating layer located on the mounting surface side ( The invention of claim 3). Thereby, in the entire temperature range of the reflow soldering process,
The elastic modulus of the insulating layer on the mounting surface side does not decrease,
This is effective in suppressing warpage deformation.

【0013】また、第2の手段は、実装面側に位置する
絶縁層と、それとは反対側に位置する絶縁層との間で、
それら絶縁層の厚みを異ならせたことを特徴としている
(請求項4の発明)。これによれば、熱膨張,収縮の大
きい側の絶縁層と、熱膨張,収縮の小さい側の絶縁層と
の間で、その厚みを変化させることによって、反り変形
量を少なく抑えることができ、この結果、半田接合部に
加わる応力を低減し、ひいては半田接合部の接続信頼性
を向上させることが可能となる。
[0013] The second means is that an insulating layer located on the mounting surface side and an insulating layer located on the opposite side are disposed between the insulating layer and the insulating layer.
It is characterized in that the thicknesses of these insulating layers are different (the invention of claim 4). According to this, by changing the thickness between the insulating layer on the side where thermal expansion and contraction is large and the insulating layer on the side where thermal expansion and contraction is small, the amount of warpage deformation can be reduced, As a result, it is possible to reduce the stress applied to the solder joint, and to improve the connection reliability of the solder joint.

【0014】このとき、実装面側に位置する絶縁層を、
それとは反対側に位置する絶縁層よりも、厚みを大きく
構成することができる(請求項5の発明)。これによ
り、実装面とは反対面側で熱膨張,収縮が大きい場合で
あっても、その熱膨張,収縮に実装面側を追従させるこ
とができ、冷却収縮時における実装面側に凸状となる反
り変形を抑制することができる。
At this time, the insulating layer located on the mounting surface side is
The thickness can be made larger than that of the insulating layer located on the opposite side (the invention of claim 5). As a result, even if the thermal expansion and contraction are large on the side opposite to the mounting surface, the mounting surface can follow the thermal expansion and contraction. Warp deformation can be suppressed.

【0015】さらに、第3の手段は、実装面側に位置す
る絶縁層と、それとは反対側に位置する絶縁層との間
で、樹脂材料中に含有されるガラスクロスの量を異なら
せたところを特徴としている(請求項6の発明)。これ
によれば、樹脂材料中に含有されるガラスクロスの量に
よって絶縁層の弾性率を変化させることができるから、
熱膨張,収縮の小さい側を、熱膨張,収縮が大きくなる
側に追従させ、反りの発生を抑えることが可能となる。
この結果、加熱,冷却に伴う反り変形を抑制し、ひいて
は半田接合部の接続信頼性を向上させることが可能とな
る。
Further, in the third means, the amount of glass cloth contained in the resin material differs between the insulating layer located on the mounting surface side and the insulating layer located on the opposite side. However, it is characterized (the invention of claim 6). According to this, the elastic modulus of the insulating layer can be changed by the amount of glass cloth contained in the resin material,
The side where the thermal expansion and contraction is small follows the side where the thermal expansion and contraction becomes large, so that the occurrence of warpage can be suppressed.
As a result, it is possible to suppress the warp deformation caused by heating and cooling, and to improve the connection reliability of the solder joint.

【0016】この場合、実装面側に位置する絶縁層を、
それとは反対側に位置する絶縁層よりも、ガラスクロス
の含有量が多くなるように構成することができる(請求
項7の発明)。これにより、実装面とは反対面側で熱膨
張,収縮が大きい場合であっても、その熱膨張,収縮に
実装面側を追従させることができ、冷却収縮時における
実装面側に凸状となる反り変形を抑制することができ
る。尚、同様の反り変形の制御は、絶縁層の樹脂中に、
高弾性率または低熱膨張係数の無機フィラー例えばシリ
カ(SiO2)粉末などを混入したものを、実装面側に
配置することによっても可能である。
In this case, the insulating layer located on the mounting surface side is
It can be configured so that the content of the glass cloth is larger than that of the insulating layer located on the opposite side (the invention of claim 7). As a result, even if the thermal expansion and contraction are large on the side opposite to the mounting surface, the mounting surface can follow the thermal expansion and contraction. Warp deformation can be suppressed. In addition, the same control of the warpage deformation is performed in the resin of the insulating layer.
It is also possible to dispose an inorganic filler having a high elastic modulus or a low coefficient of thermal expansion, such as silica (SiO2) powder, on the mounting surface side.

【0017】[0017]

【発明の実施の形態】以下、本発明を具体化した第1の
実施例(請求項1,2,3に対応)について、図1及び
図2を参照しながら説明する。図1は、本実施例に係る
多層配線基板11の表面の実装面(図で上面)に、例え
ばCSP(Chip Size Package )タイプの表面実装部品
12を実装した様子を模式的に示している。周知のよう
に、前記表面実装部品12は、矩形状のパッケージ12
aの下面の電極12bに半田バンプ13を有して構成さ
れている。この半田バンプ13(電極12b)は多数個
がアレイ状に設けられている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment (corresponding to claims 1, 2 and 3) embodying the present invention will be described with reference to FIGS. FIG. 1 schematically shows a state in which, for example, a CSP (Chip Size Package) type surface mounting component 12 is mounted on a mounting surface (upper surface in the figure) of a surface of a multilayer wiring board 11 according to the present embodiment. As is well known, the surface mount component 12 is a rectangular package 12.
The electrode 12b on the lower surface of FIG. Many solder bumps 13 (electrodes 12b) are provided in an array.

【0018】これに対し、前記多層配線基板11は、樹
脂材料からなるコア基材14の表側(上側)に、例えば
2層の絶縁層15a,15bからなるビルドアップ層1
5を有すると共に、コア基材14の下側にも、この場合
2層の絶縁層16a,16bからなるビルドアップ層1
6を有して構成される。そのうち、ビルドアップ層15
(絶縁層15b)の表面側(図で上面側)が実装面とさ
れている。前記各絶縁層15a,15b及び16a,1
6bは、樹脂材料を主体として構成されるのであるが、
その材料については後述する。
On the other hand, the multilayer wiring board 11 has a build-up layer 1 composed of, for example, two insulating layers 15a and 15b on the front side (upper side) of a core base 14 composed of a resin material.
5 and also on the lower side of the core base material 14, in this case, the build-up layer 1 composed of two insulating layers 16a and 16b.
6. Among them, build-up layer 15
The surface side (the upper side in the figure) of the (insulating layer 15b) is a mounting surface. Each of the insulating layers 15a, 15b and 16a, 1
6b is mainly composed of a resin material,
The material will be described later.

【0019】そして、多層配線基板11の上下両面側及
び絶縁層間には、例えば銅箔にめっきを施してなる導体
パターン17が形成されている。そのうち、多層配線基
板11の実装面には、前記表面実装部品12の底面に設
けられた半田バンプ13に対応したランド17aが形成
されている。また、この多層配線基板11の表面は、必
要部分(前記ランド17a部分)を除いて図示しないソ
ルダレジストにより覆われている。尚、前記導体パター
ン17は、実装面側(ビルドアップ層15側)において
面積密度が小さく、それとは反対面側(ビルドアップ層
16側)において面積密度がそれよりも大きく形成され
ている。
A conductive pattern 17 formed by plating copper foil, for example, is formed between the upper and lower surfaces of the multilayer wiring board 11 and between the insulating layers. A land 17 a corresponding to the solder bump 13 provided on the bottom surface of the surface mount component 12 is formed on the mounting surface of the multilayer wiring board 11. The surface of the multilayer wiring board 11 is covered with a solder resist (not shown) except for a necessary part (the land 17a). The conductor pattern 17 is formed to have a small area density on the mounting surface side (the build-up layer 15 side) and a larger area density on the opposite surface side (the build-up layer 16 side).

【0020】後の作用説明でも述べるように、前記表面
実装部品12の多層配線基板11に対する実装は、前記
多層配線基板11の実装面のランド17a部分に図示し
ない半田ペーストを塗布し、その各ランド17a上に各
半田バンプ13が載置されるように、表面実装部品12
を位置決め状態で搭載(仮接合)し、その後、リフロー
炉を通してリフロー加熱することにより行なわれる。
尚、本実施例では、前記半田ペーストとして、一般的に
使用されるSn/Pb重量比が63/37の共晶はんだ
が採用されており、リフローピーク温度が230〜24
0℃とされ、また183℃以下で凝固するようになって
いる。
As will be described later, the mounting of the surface mount component 12 on the multilayer wiring board 11 is performed by applying a solder paste (not shown) to the lands 17a on the mounting surface of the multilayer wiring board 11, 17a so that each solder bump 13 is placed on the surface mount component 12a.
Is mounted (temporary joining) in a positioning state, and then reflow heating is performed through a reflow furnace.
In this embodiment, a commonly used eutectic solder having a Sn / Pb weight ratio of 63/37 is adopted as the solder paste, and the reflow peak temperature is 230 to 24.
It is set to 0 ° C. and solidifies at 183 ° C. or less.

【0021】さて、本実施例では、前記多層配線基板1
1を構成している絶縁層において、実装面側に位置する
絶縁層15a,15bと、それとは反対側に位置する絶
縁層16a,16bとの間で、特性の異なる樹脂材料が
採用されており、この場合、実装面側の絶縁層15a,
15bを構成する樹脂材料は、反対面側の絶縁層16
a,16bを構成する樹脂材料よりも弾性率の大きいも
のとされている。
In this embodiment, the multilayer wiring board 1
In the insulating layer that constitutes No. 1, resin materials having different characteristics are employed between the insulating layers 15a and 15b located on the mounting surface side and the insulating layers 16a and 16b located on the opposite side. In this case, the insulating layer 15a on the mounting surface side,
15b is formed of the insulating layer 16 on the opposite side.
The elastic material has a higher elastic modulus than the resin material constituting the a and 16b.

【0022】より具体的には、実装面側に位置する絶縁
層15a,15bには、ガラス転移点がリフローピーク
温度(230〜240℃)よりも高い樹脂材料、例えば
ポリアミドイミド樹脂が採用されている。あるいは、全
芳香族ポリエステル樹脂などを採用することもできる。
一方、反対面側の絶縁層16a,16bには、リフロー
ピーク温度以下にガラス転移点が存在する樹脂材料、例
えば通常用いられる、アミン系硬化剤またはフェノール
ノボラック,クレゾールノボラック等の硬化剤を添加し
てなるビスフェノールA型エポキシ樹脂が採用されてい
る。あるいは、ポリエチレン樹脂、ポリブチレンテレフ
タレート樹脂などを採用することもできる。尚、このと
き、本発明者等の研究によれば、実装面側の絶縁層15
a,15bの弾性率を、反対面側の絶縁層16a,16
bの弾性率の1.5倍以上、より好ましくは3倍以上と
することが望ましい。
More specifically, a resin material having a glass transition point higher than the reflow peak temperature (230 to 240 ° C.), for example, a polyamideimide resin is employed for the insulating layers 15 a and 15 b located on the mounting surface side. I have. Alternatively, a wholly aromatic polyester resin or the like can be employed.
On the other hand, a resin material having a glass transition point below the reflow peak temperature, for example, a commonly used amine-based curing agent or a curing agent such as phenol novolak or cresol novolac is added to the insulating layers 16a and 16b on the opposite surface side. Bisphenol A type epoxy resin is used. Alternatively, a polyethylene resin, a polybutylene terephthalate resin, or the like can be employed. At this time, according to the study by the present inventors, the insulating layer 15 on the mounting surface side is used.
The elastic moduli of the insulating layers 16a, 16b on the opposite side
It is desirable that the elastic modulus of b is 1.5 times or more, more preferably 3 times or more.

【0023】次に、上記構成の作用について、図2も参
照して述べる。表面実装部品12を多層配線基板11の
実装面に実装するにあたっては、上述のように、まず、
多層配線基板11(ランド17a)上に半田ペーストを
塗布する半田ペースト塗布工程が周知の方法(スクリー
ン印刷等)により実行される。次に、半田ペーストが塗
布された多層配線基板11上に、前記表面実装部品12
を、その各半田バンプ13が前記各ランド17a上に配
置されるように搭載するマウント工程が実行される。こ
の場合、このマウント工程は、例えば高速チップマウン
タ等を用いて行なわれ、例えば視覚認識装置を用いた制
御により、高精度な位置決め状態で行なわれる。
Next, the operation of the above configuration will be described with reference to FIG. When mounting the surface mount component 12 on the mounting surface of the multilayer wiring board 11, first, as described above,
A solder paste application step of applying a solder paste on the multilayer wiring board 11 (land 17a) is performed by a known method (screen printing or the like). Next, the surface mount component 12 is placed on the multilayer wiring board 11 to which the solder paste has been applied.
Is mounted so that the solder bumps 13 are arranged on the lands 17a. In this case, this mounting step is performed using, for example, a high-speed chip mounter, and is performed in a highly accurate positioning state by, for example, control using a visual recognition device.

【0024】そして、表面実装部品12がマウントされ
た多層配線基板11を、リフロー加熱するリフロー工程
が実行される。このリフロー工程は、多層配線基板11
を、図示しないリフロー炉内を所定速度で通すことによ
り行なわれるのであるが、このとき、リフロー炉内は、
その温度分布によってプリヒートゾーン、リフローゾー
ン、冷却ゾーン等が設けられており、それら各温度ゾー
ンを順に通過することにより、多層配線基板11上の半
田ペーストの溶融、硬化が行なわれて、表面実装部品1
2の半田バンプ13が、多層配線基板11上のランド1
7aに半田接合され、電気的及び機械的な接続が行なわ
れるのである。
Then, a reflow step of reflow heating the multilayer wiring board 11 on which the surface mount components 12 are mounted is executed. This reflow process is performed in the multilayer wiring board 11
Is carried out at a predetermined speed through a not-shown reflow furnace. At this time, the inside of the reflow furnace is
A preheat zone, a reflow zone, a cooling zone, and the like are provided according to the temperature distribution, and the solder paste on the multilayer wiring board 11 is melted and hardened by passing through each of the temperature zones in turn, so that the surface mount component is formed. 1
The two solder bumps 13 correspond to the lands 1 on the multilayer wiring board 11.
7a, and electrical and mechanical connections are made.

【0025】このリフロー工程においては、例えば多層
配線基板11の種類や厚み、表面実装部品12の種類、
半田ペーストの種類(凝固点)などに応じて、例えば図
2に示すような適切な温度プロファイルが採用される。
この場合、表面実装部品12がマウントされた多層配線
基板11は、常温(時点A)からプリヒートゾーンにて
所定のカーブをもって加熱されていき、リフローゾーン
においてピーク温度(時点B;例えば230℃)まで加
熱されて半田ペーストが溶融し、その後の冷却ゾーンに
おいて所定のカーブをもって冷却されていくことによ
り、半田ペーストが硬化されるようになっている。
In the reflow process, for example, the type and thickness of the multilayer wiring board 11, the type of the surface mount component 12,
For example, an appropriate temperature profile as shown in FIG. 2 is adopted according to the type (solidification point) of the solder paste.
In this case, the multilayer wiring board 11 on which the surface mount components 12 are mounted is heated from a normal temperature (time A) with a predetermined curve in the preheating zone, and reaches a peak temperature (time B; for example, 230 ° C.) in the reflow zone. The solder paste is melted by being heated, and is cooled with a predetermined curve in a subsequent cooling zone, so that the solder paste is hardened.

【0026】しかして、上記リフロー工程においては、
上記多層配線基板11は、その構成要素(絶縁層15
a,15b,16a,16bと導体パターン17)間で
熱膨張係数が相違し、また多層配線基板11と表面実装
部品12との間での熱膨張係数が相違する事情もあっ
て、実装面側と反対面側との間で導体パターン17の面
積や形状,配置(面積密度)が不均一である等の要因に
より、導体パターン17の面積密度が大きい側(ビルド
アップ層16側)で、実装面側(ビルドアップ層15
側)よりも熱膨張,収縮が大きくなり、多層配線基板1
1に反り変形やその回復方向の変形といった変形挙動が
発生する。
Thus, in the reflow process,
The multilayer wiring board 11 has its components (insulating layer 15
a, 15b, 16a, 16b and the conductor pattern 17) have different coefficients of thermal expansion, and the multilayer circuit board 11 and the surface mount component 12 have different coefficients of thermal expansion. Due to factors such as unevenness in the area, shape, and arrangement (area density) of the conductor pattern 17 between the conductor pattern 17 and the opposite side, mounting is performed on the side where the area density of the conductor pattern 17 is large (the build-up layer 16 side). Surface side (Build-up layer 15
Side), the thermal expansion and contraction are greater than that of the multilayer wiring board 1
In FIG. 1, deformation behavior such as warpage deformation and deformation in the recovery direction occurs.

【0027】このとき、半田ペーストは、冷却過程の初
期(例えば183℃以下となる時点C)において硬化す
るので、半田接合部により各ランド17aに対する各半
田バンプ13の位置が拘束された状態で、多層配線基板
11に内側が上方に凸となる方向の反りが発生し、この
ため、外側に位置する半田接合部に大きな引張り応力が
加わる問題がある。このように半田接合部に大きな応力
が加わると、半田接合部自身の破壊や、半田と半田バン
プ13との界面、あるいは半田とランド17aとの界面
にて剥離が生ずる虞がある。
At this time, the solder paste is hardened at the beginning of the cooling process (for example, at a time point C when the temperature is 183 ° C. or less), so that the position of each solder bump 13 with respect to each land 17a is restricted by the solder joint. The multilayer wiring board 11 is warped in a direction in which the inside becomes convex upward, and therefore, there is a problem that a large tensile stress is applied to the solder joint portion located on the outside. When a large stress is applied to the solder joint as described above, there is a possibility that the solder joint itself is destroyed, or separation occurs at the interface between the solder and the solder bump 13 or at the interface between the solder and the land 17a.

【0028】ところが、本実施例では、熱膨張,収縮が
小さい側であるビルドアップ層15側の絶縁層15a,
15bを、弾性率の大きい樹脂材料から構成したので、
熱膨張,収縮が大きくなる側であるビルドアップ層16
側の熱膨張,収縮に追従させることができ、反りの発生
を抑えることが可能となるのである。このとき、絶縁層
15a,15bに、ガラス転移点がリフローピーク温度
よりも高い樹脂材料を採用したことにより。リフロー工
程の全温度領域において、実装面側の絶縁層15a,1
5bの弾性率が低下することがなくなり、反り変形の抑
制効果に極めて優れたものとなるのである。
However, in the present embodiment, the insulating layers 15a, 15b on the side of the build-up layer 15 on the side where the thermal expansion and contraction are small.
Since 15b is made of a resin material having a large elastic modulus,
Build-up layer 16 on the side where thermal expansion and contraction increase
It is possible to follow the thermal expansion and contraction of the side, thereby suppressing the occurrence of warpage. At this time, a resin material having a glass transition point higher than the reflow peak temperature is used for the insulating layers 15a and 15b. In the entire temperature range of the reflow process, the insulating layers 15a, 15
The elastic modulus of 5b does not decrease, and the effect of suppressing the warpage is extremely excellent.

【0029】従って、本実施例によれば、実装面に表面
実装部品12がリフロー半田付けされるものにあって、
実装面側に位置する絶縁層15a,15bを構成する樹
脂材料を、それとは反対側に位置する絶縁層16a,1
6bよりも、弾性率の大きいものとしたことにより、リ
フロー工程の冷却収縮時における実装面側に凸状となる
反り変形を抑制することができる。この結果、半田接合
部に応力が加わることを効果的に防止し、半田接合部の
接続信頼性を向上させることができるという優れた効果
を奏するものである。また、実装後の製品の使用時にお
いても、製品の使用環境下で加わる熱応力に対する耐久
性の向上を図ることができる。
Therefore, according to this embodiment, the surface mounting component 12 is mounted on the mounting surface by reflow soldering.
The resin material constituting the insulating layers 15a and 15b located on the mounting surface side is replaced with the insulating layers 16a and 1 located on the opposite side.
By setting the elastic modulus to be larger than 6b, it is possible to suppress the warp deformation that becomes convex on the mounting surface side during the cooling shrinkage in the reflow step. As a result, an excellent effect of effectively preventing stress from being applied to the solder joint and improving the connection reliability of the solder joint can be obtained. Further, even when the product after mounting is used, it is possible to improve the durability against the thermal stress applied in the usage environment of the product.

【0030】図3は、本発明の第2の実施例(請求項
4,5に対応)を示すものである。この第2の実施例に
係る多層配線基板21が、上記第1の実施例の多層配線
基板11と異なるところは、実装面側に位置する絶縁層
と反対面側に位置する絶縁層との間で、構成する樹脂材
料を異ならせることに代えて、それら絶縁層の厚みを異
ならせるようにした点にある。
FIG. 3 shows a second embodiment (corresponding to claims 4 and 5) of the present invention. The difference between the multilayer wiring board 21 according to the second embodiment and the multilayer wiring board 11 according to the first embodiment is that the multilayer wiring board 21 is located between the insulating layer located on the mounting surface side and the insulating layer located on the opposite side. Therefore, instead of using different resin materials, the thicknesses of the insulating layers are different.

【0031】即ち、この多層配線基板21は、コア基材
14の表側(上側)に、例えば2層の絶縁層22a,2
2bからなるビルドアップ層22を有すると共に、コア
基材14の下側にも、この場合2層の絶縁層23a,2
3bからなるビルドアップ層23を有して構成される。
そのうち、実装面側のビルドアップ層22を構成する絶
縁層22a,22bの厚みが、反対面側のビルドアップ
層23を構成する絶縁層23a,23bの厚みよりも大
きくされているのである。
That is, the multilayer wiring board 21 has, for example, two insulating layers 22a, 22a on the front side (upper side) of the core base material 14.
2b, and also in this case, two insulating layers 23a, 23
3b.
Among them, the thickness of the insulating layers 22a and 22b forming the build-up layer 22 on the mounting surface side is larger than the thickness of the insulating layers 23a and 23b forming the build-up layer 23 on the opposite surface side.

【0032】これによれば、実装面側に位置する絶縁層
22a,22bを、それとは反対側に位置する絶縁層2
3a,23bよりも、厚みを大きくしたことにより、上
記第1の実施例と同様に、リフロー工程あるいは実使用
時の熱膨張,収縮に伴う反り変形量を少なく抑えること
ができ、この結果、半田接合部に加わる応力を低減し、
ひいては半田接合部の接続信頼性を向上させることが可
能となる。
According to this, the insulating layers 22a and 22b located on the mounting surface side are replaced with the insulating layers 2a located on the opposite side.
By making the thickness larger than 3a and 23b, the amount of warping deformation due to thermal expansion and contraction during the reflow step or actual use can be reduced, as in the first embodiment. Reduce the stress applied to the joint,
As a result, the connection reliability of the solder joint can be improved.

【0033】図4は、本発明の第3の実施例(請求項
6,7に対応)を示すものである。この第3の実施例に
係る多層配線基板31が、上記第1の実施例の多層配線
基板11と異なるところは、実装面側に位置する絶縁層
と反対面側に位置する絶縁層との間で、構成する樹脂材
料を異ならせることに代えて、樹脂材料中に含有される
ガラスクロスの量を異ならせるようにした点にある。
FIG. 4 shows a third embodiment (corresponding to claims 6 and 7) of the present invention. The difference between the multilayer wiring board 31 according to the third embodiment and the multilayer wiring board 11 of the first embodiment is that the multilayer wiring board 31 is located between the insulating layer located on the mounting surface side and the insulating layer located on the opposite side. Thus, instead of using different resin materials, the amount of glass cloth contained in the resin material is changed.

【0034】即ち、この多層配線基板31は、コア基材
14の表側(上側)に、例えば2層の絶縁層32a,3
2bからなるビルドアップ層32を有すると共に、コア
基材14の下側にも、この場合2層の絶縁層33a,3
3bからなるビルドアップ層33を有して構成される。
そのうち、実装面側のビルドアップ層32を構成する絶
縁層32a,32bには、例えば樹脂含有率が49.3
%のガラスクロス入りのエポキシ樹脂のプリプレグシー
トが採用され、反対面側のビルドアップ層33を構成す
る絶縁層33a,33bには、例えば樹脂含有率が6
1.5%のガラスクロス入りのエポキシ樹脂のプリプレ
グシートが採用される。
That is, the multilayer wiring board 31 is provided on the front side (upper side) of the core base material 14, for example, with two insulating layers 32a, 32
2b, and also in this case, two insulating layers 33a, 3
It has a build-up layer 33 made of 3b.
The insulating layers 32a and 32b constituting the build-up layer 32 on the mounting surface side have, for example, a resin content of 49.3.
% Of an epoxy resin containing glass cloth, and the insulating layers 33a and 33b constituting the build-up layer 33 on the opposite side have a resin content of, for example, 6%.
An epoxy resin prepreg sheet containing 1.5% glass cloth is employed.

【0035】これによれば、実装面側に位置する絶縁層
32a,32bを、それとは反対側に位置する絶縁層3
3a,33bよりも、弾性率の大きいものとすることが
でき、従って、上記第1の実施例と同様に、リフロー工
程や実使用時の熱膨張,収縮時の反り変形を抑制するこ
とができる。この結果、半田接合部に応力が加わること
を効果的に防止し、半田接合部の接続信頼性を向上させ
ることができるものである。
According to this, the insulating layers 32a and 32b located on the mounting surface side are replaced with the insulating layer 3 located on the opposite side.
3a and 33b, the elastic modulus can be made larger than that of the first embodiment. Therefore, similarly to the first embodiment, it is possible to suppress the warping during the reflow process and the thermal expansion and contraction during actual use. . As a result, it is possible to effectively prevent stress from being applied to the solder joint and improve the connection reliability of the solder joint.

【0036】尚、上記第1〜第3の実施例では、熱膨
張,収縮に伴う反り変形を抑制するための手段として、
実装面側と反対面側とで、絶縁層を構成する樹脂材料の
特性(弾性率)を異ならせる、絶縁層の厚みを異ならせ
る、絶縁層のガラスクロスの含有量を異ならせる、とい
う3つの手段を夫々独立して採用したものとしたが、そ
のうちの2つの手段を組合わせたり、あるいは3つ全て
の手段を組合わせる構成として実施することもできる。
また、絶縁層の層の数や厚み等についても様々なものが
考えられ、絶縁層毎に弾性率が順番に変化(傾斜)する
ような構成としても良い。
In the first to third embodiments, the means for suppressing the warp deformation accompanying the thermal expansion and contraction is as follows.
There are three ways to change the characteristics (elastic modulus) of the resin material that forms the insulating layer, change the thickness of the insulating layer, and change the glass cloth content of the insulating layer between the mounting surface side and the opposite surface side. Although the means are independently adopted, two of them may be combined or all three may be combined.
Further, the number and thickness of the insulating layers may be varied, and the elastic modulus may be sequentially changed (inclined) for each insulating layer.

【0037】その他、本発明は上記した実施例に限定さ
れるものではなく、例えば表面実装部品としては、CS
Pタイプのものに限らず、例えばQFPタイプ,BGA
タイプ,MCMタイプ等の各種パッケージの表面実装部
品全般に本発明を適用することができ、また、半田ペー
ストの材質としても、鉛フリー半田等であっても良く、
さらには、配線基板を構成する絶縁層や導体パターンの
材質等についても、様々なものが採用できる等、要旨を
逸脱しない範囲内で適宜変更して実施し得るものであ
る。
In addition, the present invention is not limited to the above-described embodiment.
Not limited to P type, for example, QFP type, BGA
The present invention can be applied to all surface mount components of various types of packages such as type and MCM type, and the material of the solder paste may be lead-free solder.
Further, the material and the like of the insulating layer and the conductor pattern constituting the wiring board may be appropriately changed and changed without departing from the gist, for example, various materials may be adopted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例を示すもので、多層配線
基板に表面実装部品を実装した様子を模式的に示す縦断
面図
FIG. 1 shows a first embodiment of the present invention, and is a longitudinal sectional view schematically showing a state in which surface mount components are mounted on a multilayer wiring board.

【図2】リフロー加熱における温度−時間曲線及び基板
の変形挙動の様子を模式的に示す図
FIG. 2 is a diagram schematically showing a state of a temperature-time curve and a deformation behavior of a substrate in reflow heating.

【図3】本発明の第2の実施例を示す図1相当図FIG. 3 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

【図4】本発明の第3の実施例を示す図1相当図FIG. 4 is a view corresponding to FIG. 1, showing a third embodiment of the present invention;

【図5】従来例を示すもので、多層配線基板に表面実装
部品をマウントした様子(a)及び反りが発生した様子
(b)を示す縦断面図
FIG. 5 is a longitudinal sectional view showing a conventional example, showing a state in which surface-mounted components are mounted on a multilayer wiring board (a) and a state in which warpage occurs (b).

【符号の説明】[Explanation of symbols]

図面中、11,21,31は多層配線基板、12は表面
実装部品、13は半田バンプ、14はコア基材、15,
16,22,23,32,33はビルドアップ層、15
a,15b,16a,16b,22a,22b,23
a,23b,32a,32b,33a,33bは絶縁
層、17は導体パターン、17aはランドを示す。
In the drawings, 11, 21 and 31 are multilayer wiring boards, 12 is a surface mount component, 13 is a solder bump, 14 is a core base material,
16, 22, 23, 32 and 33 are build-up layers, 15
a, 15b, 16a, 16b, 22a, 22b, 23
a, 23b, 32a, 32b, 33a, 33b are insulating layers, 17 is a conductor pattern, and 17a is a land.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H01L 23/12 N (72)発明者 松永 泰明 愛知県刈谷市昭和町1丁目1番地 株式会 社デンソー内 Fターム(参考) 5E319 AA03 AA07 AB05 AC02 BB04 BB05 BB07 CC33 GG11 GG20 5E343 AA16 AA17 AA18 BB54 ER54 GG20 5E346 AA12 AA38 CC04 CC08 CC09 CC10 CC12 CC13 CC40 FF45 HH11 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 3/46 H01L 23/12 N (72) Inventor Yasuaki Matsunaga 1-1-1 Showa-cho, Kariya-shi, Aichi Stock F term in DENSO (reference) 5E319 AA03 AA07 AB05 AC02 BB04 BB05 BB07 CC33 GG11 GG20 5E343 AA16 AA17 AA18 BB54 ER54 GG20 5E346 AA12 AA38 CC04 CC08 CC09 CC10 CC12 CC13 CC40 FF45 HH11

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 樹脂材料を主体とした多層の絶縁層を有
すると共に、表面及び前記絶縁層間に導体パターンを有
してなり、その表面を表面実装部品が半田付けされる実
装面とした多層配線基板であって、 前記実装面側に位置する絶縁層と、それとは反対側に位
置する絶縁層との間で、特性の異なる樹脂材料が採用さ
れていることを特徴とする多層配線基板。
1. A multilayer wiring comprising a multilayer insulating layer mainly composed of a resin material, a conductor pattern between the surface and the insulating layer, and the surface having a mounting surface to which a surface mount component is soldered. A multilayer wiring board, wherein a resin material having different characteristics is adopted between an insulating layer located on the mounting surface side and an insulating layer located on the opposite side.
【請求項2】 前記実装面側に位置する絶縁層を構成す
る樹脂材料は、それとは反対側に位置する絶縁層より
も、弾性率の大きいもの又は熱膨張係数が大きいものが
採用されていることを特徴とする請求項1記載の多層配
線基板。
2. A resin material constituting the insulating layer located on the mounting surface side has a higher elastic modulus or a larger coefficient of thermal expansion than the insulating layer located on the opposite side. The multilayer wiring board according to claim 1, wherein:
【請求項3】 前記実装面に表面実装部品をリフロー半
田付けするものであって、前記実装面側に位置する絶縁
層に、ガラス転移点がリフローピーク温度よりも高い樹
脂材料を採用することを特徴とする請求項2記載の多層
配線基板。
3. A method for reflow soldering a surface mount component to the mounting surface, wherein a resin material having a glass transition point higher than a reflow peak temperature is used for an insulating layer located on the mounting surface side. 3. The multilayer wiring board according to claim 2, wherein:
【請求項4】 樹脂材料を主体とした多層の絶縁層を有
すると共に、表面及び前記絶縁層間に導体パターンを有
してなり、その表面を表面実装部品が半田付けされる実
装面とした多層配線基板であって、 前記実装面側に位置する絶縁層と、それとは反対側に位
置する絶縁層との間で、それら絶縁層の厚みが異なって
いることを特徴とする多層配線基板。
4. A multilayer wiring comprising a multilayer insulating layer mainly composed of a resin material, a conductor pattern between the surface and the insulating layer, and the surface having a mounting surface to which a surface mount component is soldered. A multilayer wiring board, wherein the thickness of the insulating layer is different between the insulating layer located on the mounting surface side and the insulating layer located on the opposite side.
【請求項5】 前記実装面側に位置する絶縁層は、それ
とは反対側に位置する絶縁層よりも、厚みが大きくされ
ていることを特徴とする請求項4記載の多層配線基板。
5. The multilayer wiring board according to claim 4, wherein the insulating layer located on the mounting surface side is thicker than the insulating layer located on the opposite side.
【請求項6】 樹脂材料を主体とした多層の絶縁層を有
すると共に、表面及び前記絶縁層間に導体パターンを有
してなり、その表面を表面実装部品が半田付けされる実
装面とした多層配線基板であって、 前記実装面側に位置する絶縁層と、それとは反対側に位
置する絶縁層との間で、樹脂材料中に含有されるガラス
クロスの量が異なっていることを特徴とする多層配線基
板。
6. A multilayer wiring comprising a multilayer insulating layer mainly composed of a resin material, a conductor pattern between the surface and the insulating layer, and the surface having a mounting surface to which a surface mount component is soldered. A substrate, wherein the amount of glass cloth contained in the resin material is different between the insulating layer located on the mounting surface side and the insulating layer located on the opposite side. Multilayer wiring board.
【請求項7】 前記実装面側に位置する絶縁層は、それ
とは反対側に位置する絶縁層よりも、ガラスクロスの含
有量が多くされていることを特徴とする請求項6記載の
多層配線基板。
7. The multilayer wiring according to claim 6, wherein the insulating layer located on the mounting surface side has a larger glass cloth content than the insulating layer located on the opposite side. substrate.
JP2000026346A 2000-02-03 2000-02-03 Multi-layered wiring board Pending JP2001217514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000026346A JP2001217514A (en) 2000-02-03 2000-02-03 Multi-layered wiring board

Publications (1)

Publication Number Publication Date
JP2001217514A true JP2001217514A (en) 2001-08-10

Family

ID=18552091

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001217514A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143583A (en) * 1988-11-25 1990-06-01 Mitsubishi Electric Corp Memory module
JPH05229062A (en) * 1992-02-26 1993-09-07 Shin Kobe Electric Mach Co Ltd Metal foil clad laminated plate and printed circuit board
JPH05259641A (en) * 1992-03-13 1993-10-08 Matsushita Electric Works Ltd Multilayer printed wiring board
JPH09133710A (en) * 1995-11-10 1997-05-20 Hitachi Chem Co Ltd Jig for inspection of semiconductor device
JPH1154927A (en) * 1997-06-03 1999-02-26 Toshiba Corp Composite wiring board, flexible board, semiconductor device and manufacture of composite wiring board
JPH1168025A (en) * 1997-08-20 1999-03-09 Toppan Printing Co Ltd Multi-chip module substrate
JPH11163529A (en) * 1997-11-28 1999-06-18 Ibiden Co Ltd Multilayer printed board and its manufacture

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143583A (en) * 1988-11-25 1990-06-01 Mitsubishi Electric Corp Memory module
JPH05229062A (en) * 1992-02-26 1993-09-07 Shin Kobe Electric Mach Co Ltd Metal foil clad laminated plate and printed circuit board
JPH05259641A (en) * 1992-03-13 1993-10-08 Matsushita Electric Works Ltd Multilayer printed wiring board
JPH09133710A (en) * 1995-11-10 1997-05-20 Hitachi Chem Co Ltd Jig for inspection of semiconductor device
JPH1154927A (en) * 1997-06-03 1999-02-26 Toshiba Corp Composite wiring board, flexible board, semiconductor device and manufacture of composite wiring board
JPH1168025A (en) * 1997-08-20 1999-03-09 Toppan Printing Co Ltd Multi-chip module substrate
JPH11163529A (en) * 1997-11-28 1999-06-18 Ibiden Co Ltd Multilayer printed board and its manufacture

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