JPH02143583A - Memory module - Google Patents

Memory module

Info

Publication number
JPH02143583A
JPH02143583A JP63298609A JP29860988A JPH02143583A JP H02143583 A JPH02143583 A JP H02143583A JP 63298609 A JP63298609 A JP 63298609A JP 29860988 A JP29860988 A JP 29860988A JP H02143583 A JPH02143583 A JP H02143583A
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
memory module
solder
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63298609A
Other languages
Japanese (ja)
Inventor
Yoichi Kitamura
洋一 北村
Koichiro Nakanishi
幸一郎 仲西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63298609A priority Critical patent/JPH02143583A/en
Publication of JPH02143583A publication Critical patent/JPH02143583A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain a highly accurate memory module which is protected against warpage when it is completed by a method wherein the cross-sectional structure of the inner circuit of a multilayer printed wiring board is made asymmetrical about a vertical direction so as to make a side where a semiconductor memory element is mounted high in density. CONSTITUTION:In a printed wiring board, a power source layer 6d formed of a thick electrolytic copper foil large in area as compared with other inner layers is arranged near the surface on which semiconductor memories 1 are mounted, whereby the printed wiring board is made assymetrical in a cross-sectional structure. In result, in a solder reflow process, solder is fused as the printed wiring board is kept warped due to the linear expansion coefficient difference between a glass epoxy laminated board 5 and the inner layers when the printed wiring board is expanded due to heat applied, so that the warpage of a memory module is offset as a whole when the module is cooled down to a room temperature even if the shrinkage of the printed wiring board on a semiconductor memory mounted side is prevented due to the solidification of the solder, and consequently a flat memory module can be offered.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、複数の半導体メモリ素子を一枚のプリント配
vA板の片側の表面にのみ搭載することによって成るメ
モリモジュールにおいて、特に多層構造のプリント配線
板を用いるものに関するものである。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a memory module in which a plurality of semiconductor memory elements are mounted only on one surface of a single printed circuit board, and particularly to a memory module having a multilayer structure. This relates to a device using a printed wiring board.

〔従来の技術〕[Conventional technology]

メモリモジュールは、主プリント配線板(マザーボード
)上の限られた空間内にできるだけ多くの部品を搭載す
る実装方式、すなわち高田度実装を実現するために開発
されたもので、−枚の小形プリント配線板(ドータボー
ド)上に複数個の半導体メモリが実装されて成るメモリ
ボードの一種である。メモリモジュールはマザーボード
に用意されたソケットに挿入することによって実装する
方式や、マザーボード上のスルーホールに直接はんだ実
装する方式などがある。いずれの実装方式においてもメ
モリモジュールに反りやゆがみといった寸法誤差があっ
てはスムーズな実装が望めないため、できるだけ高精度
な仕上がりであることが求められる。
Memory modules were developed to realize Takada mounting, a mounting method that mounts as many components as possible in a limited space on the main printed wiring board (motherboard). It is a type of memory board in which multiple semiconductor memories are mounted on a board (daughter board). Memory modules can be mounted by inserting them into sockets provided on the motherboard, or solder directly into through-holes on the motherboard. In any mounting method, smooth mounting cannot be expected if the memory module has dimensional errors such as warping or distortion, so it is required that the finish be as precise as possible.

従来のメモリモジュールは例えばSem1con Ne
wsトリプルA(三菱電機側発行、!1h19.198
8年3月号)P6〜7に記載のような仕様のものがあり
、複数の半導体メモリ素子を一枚のプリント配線板の表
裏両面に搭載する両面実装と、プリント配線板の片側の
表面にのみ搭載する片面実装の2種類があるが、このう
ち片面実装のメモリモジュールは第4図に示すような断
面構造をしている0図において、1は半導体メモリ、2
は半導体メモリ1とプリント配線板を接続するためのは
んだ、5はガラス布基材エポキシ樹脂層(以下ガラスエ
ポキシ層と称する)、6aはプリント配線板表面の信号
層、6bは裏面の信号層、6Cは信号層、6dは電源層
、6eはアース層、6fは信号層、7は銅めっきスルー
ホール、10は以上を集めてなる多層プリント配線板で
ある。
Conventional memory modules are for example Sem1con Ne
ws triple A (issued by Mitsubishi Electric, !1h19.198
There are two-sided mounting methods, in which multiple semiconductor memory elements are mounted on both the front and back sides of a single printed wiring board, and two-sided mounting methods, in which multiple semiconductor memory elements are mounted on both the front and back surfaces of a single printed wiring board, and those with specifications as described on pages 6 and 7 (March 2008 issue). There are two types of single-sided mounting, in which memory modules are mounted only on one side. Among these, single-sided mounting memory modules have a cross-sectional structure as shown in Figure 4.
5 is a glass cloth base epoxy resin layer (hereinafter referred to as glass epoxy layer); 6a is a signal layer on the front side of the printed wiring board; 6b is a signal layer on the back side; 6C is a signal layer, 6d is a power layer, 6e is an earth layer, 6f is a signal layer, 7 is a copper-plated through hole, and 10 is a multilayer printed wiring board made up of the above.

このようなメモリモジュールは例えばプリント回路技術
便覧(社団法人日本プリント回路工業金線、日刊工業新
聞社刊、昭和62年2月発行)P2S5に記載のように
、第5図fa)〜(e)のような工程を経て製造される
。第5図Ta)は半導体メモリを搭載する多層プリント
配線板11、第5図(b)はスクリーン印刷法によって
ソルダクリーム12が多層プリント配線板11に印刷さ
れた状態、第5図(C)は表面実装タイプの半導体メモ
リ1を装着した状態、第5図(d)は気相はんだ付は装
置15によるはんだリフロー工程で、2aは溶融したは
んだを示す。
Such a memory module is, for example, as shown in Figure 5 fa) to (e) as described in Printed Circuit Technology Handbook (Japan Printed Circuit Industry Gold Wire, Nikkan Kogyo Shimbun, published February 1986) P2S5. It is manufactured through the following steps. FIG. 5 Ta) shows a multilayer printed wiring board 11 on which a semiconductor memory is mounted, FIG. FIG. 5(d) shows a state in which a surface mount type semiconductor memory 1 is mounted, and vapor phase soldering is a solder reflow process using the device 15, and 2a indicates molten solder.

また、第5図(e)は完成したメモリモジュール20で
2bは凝固したはんだである。
Further, FIG. 5(e) shows the completed memory module 20, and 2b is solidified solder.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のメモリモジュールは以上のような製造工程を経て
製作されており、半導体メモリ1を搭載するプリント配
線板11は第4図に示したようにその断面の内層回路が
ほぼ対称構造であるため、第5図(d+のはんだリフロ
ー工程において熱によりプリント配線板11が膨張した
状態ではんだ12が溶融し、その後の冷却工程において
プリント配線板11が十分収縮していない温度(通常は
180℃以上)ではんだが凝固すると、半導体メモリを
搭載した側の収縮が凝固したはんだ2bと半導体メモリ
1によるくさび効果によって機械的に阻止される結果、
室温まで冷却した状態では第2図(elに示すように、
メモリモジュール20に反りが生じ、メモリモジュール
20をマザーボードに実装する場合に装着が困難になる
という欠点があった。このような欠点は、メモリモジュ
ール20に搭載する半導体メモリ1が大容量化するに伴
って大形化し、同時にプリント配線板11の面積が増大
する傾向にあってますます顕著化してくる。
Conventional memory modules are manufactured through the manufacturing process described above, and the printed wiring board 11 on which the semiconductor memory 1 is mounted has an almost symmetrical structure in its cross-sectional inner layer circuit, as shown in FIG. FIG. 5 (d+ solder reflow process, the solder 12 melts when the printed wiring board 11 expands due to heat, and the temperature at which the printed wiring board 11 does not sufficiently contract in the subsequent cooling process (usually 180°C or higher) When the solder solidifies, the contraction of the side on which the semiconductor memory is mounted is mechanically prevented by the wedge effect between the solidified solder 2b and the semiconductor memory 1.
When cooled to room temperature, as shown in Figure 2 (el),
There is a drawback that the memory module 20 is warped, making it difficult to mount the memory module 20 on a motherboard. These drawbacks become more and more noticeable as the capacity of the semiconductor memory 1 mounted on the memory module 20 increases, and as the area of the printed wiring board 11 tends to increase at the same time.

この発明はこのような従来のメモリモジュールの構造上
の欠点を除去するために成されたもので、従来の製造プ
ロセスを変更することなしに完成時に反りが生じない、
高精度なメモリモジュールを提供することを目的とする
The present invention was made to eliminate the structural defects of such conventional memory modules, and it is possible to eliminate warping when completed without changing the conventional manufacturing process.
The purpose is to provide high-precision memory modules.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るメモリモジュールは、多層プリント配線
板の内層回路の断面構造を、上記半導体メモリ素子を実
装した側が高密度になるよう上下方向に非対称にしたも
のである。
In the memory module according to the present invention, the cross-sectional structure of the inner layer circuit of the multilayer printed wiring board is asymmetrical in the vertical direction so that the side on which the semiconductor memory element is mounted has a higher density.

〔作用〕[Effect]

本発明においては、メモリモジュール用多層プリント配
線板の内層板の断面構造を、半導体メモリが実装された
側が高密度になるような上下方向に非対称な構造とした
ので、はんだリフロー工程で従来の冷却工程で生じてい
た凸型の反りと逆方向の凹型の反りが生じるようになり
、その後の冷却工程において発生する反りを相殺でき、
完成時点における反りやゆがみを抑えることができる。
In the present invention, the cross-sectional structure of the inner layer board of the multilayer printed wiring board for memory modules is made vertically asymmetrical so that the side where semiconductor memory is mounted has a higher density. A concave warp occurs in the opposite direction to the convex warp that occurred during the process, and the warp that occurs during the subsequent cooling process can be offset.
It is possible to suppress warpage and distortion at the time of completion.

〔実施例〕〔Example〕

以下、この発明の一実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例によるメモリモジュールの
断面構造を示す図であり、特に、プリント配線板の要部
を6層配線板を例として示したものである。また、第2
図(al〜(elは第1図のメモリモジュールの製造方
法を示す図である0両図において、lは半導体メモリ、
2ははんだ、2aは溶融したはんだ、2bは凝固したは
んだ、5はガラスエポキシ層、6aはプリント配線板表
面の信号層、6bは裏面の信号層、6cは信号層、6d
は電源層、6eはアース層、6fは信号層、7は銅めっ
きスルーホール、10は以上を集めて成る多層プリント
配線板、12はソルダクリーム、15は気相はんだ付は
装置、20はメモリモジュールである。このような構造
において、電源層6dは例えば厚さ70μmの電解銅箔
を用いた厚い層で、それ以外の1i6a、6b、6c、
6e、6fは例えば厚さ35μmの電解f1箔を用いた
層である。
FIG. 1 is a diagram showing a cross-sectional structure of a memory module according to an embodiment of the present invention, and in particular, shows the main parts of a printed wiring board by taking a six-layer wiring board as an example. Also, the second
Figures (al to (el) are diagrams showing the manufacturing method of the memory module in Figure 1. In both figures, l is a semiconductor memory,
2 is solder, 2a is molten solder, 2b is solidified solder, 5 is glass epoxy layer, 6a is a signal layer on the front side of the printed wiring board, 6b is a signal layer on the back side, 6c is a signal layer, 6d
6e is a power layer, 6e is a ground layer, 6f is a signal layer, 7 is a copper-plated through hole, 10 is a multilayer printed wiring board consisting of the above, 12 is a solder cream, 15 is a vapor phase soldering device, 20 is a memory It is a module. In such a structure, the power supply layer 6d is a thick layer using electrolytic copper foil with a thickness of 70 μm, for example, and the other layers 1i6a, 6b, 6c,
6e and 6f are layers using electrolytic f1 foil having a thickness of 35 μm, for example.

本発明によるプリント配線板11は内層板の中では面積
が大きい電源層6dに、厚い電解銅箔を使用し、半導体
メモリ1搭載側の表面近くに配置することによって、プ
リント配線板11を非対称の断面構造としたもので、そ
の結果、次に述べるような効果を得ることができる。つ
まり本実施例では従来の第5図に示した工程のうち、特
に(d)及びtelの工程が第2図に示した(d)、及
び(e)のような工程になる。すなわち第2図fa)〜
(e)に示したはんだリフロー工程において、熱により
プリント配線板が膨張した状態ではプリント配線板11
のガラスエポキシ積層板5と内層板の非対称性に基づく
線膨張係数の違いによる反りが生じたままはんだが溶融
するため、その後の冷却工程において、はんだが凝固す
ることによる半導体メモリ搭載側のプリント配線板の収
縮が阻止されても、室温まで冷却した状態では第2図(
ill)に示した様に、メモリモジュール全体としての
反りが相殺されることとなり、平坦なメモリモジュール
を提供することができる。
The printed wiring board 11 according to the present invention uses thick electrolytic copper foil for the power supply layer 6d, which has a large area among the inner layers, and is arranged near the surface on the side where the semiconductor memory 1 is mounted, thereby making the printed wiring board 11 asymmetrical. It has a cross-sectional structure, and as a result, the following effects can be obtained. That is, in this embodiment, among the conventional steps shown in FIG. 5, the steps (d) and tel in particular become the steps (d) and (e) shown in FIG. 2. That is, Fig. 2 fa) ~
In the solder reflow process shown in (e), when the printed wiring board expands due to heat, the printed wiring board 11
As the solder melts while warping due to the difference in linear expansion coefficient due to the asymmetry between the glass epoxy laminate 5 and the inner layer, the printed wiring on the side where the semiconductor memory is mounted is caused by the solder solidifying in the subsequent cooling process. Even if the shrinkage of the plate is prevented, the condition shown in Figure 2 (
As shown in (ill), the warpage of the memory module as a whole is canceled out, and a flat memory module can be provided.

なお、上記実施例では内層板のうち電源N6dを厚くし
た例を示したが、内層板の中ではtB層6d同様、面積
の大きいアースJi6eを厚くしてもよい。ただしこの
場合は電源層6dとアース層6eの位置を上記実施例と
は逆にする必要がある。
In the above embodiment, an example was shown in which the power source N6d of the inner layer board was thickened, but the ground Ji6e, which has a large area, may be made thicker in the inner layer board, similar to the tB layer 6d. However, in this case, the positions of the power layer 6d and the earth layer 6e need to be reversed from those in the above embodiment.

また上記実施例では内層板に厚い銅箔を用いた例を示し
たが、特に厚い内層板を用いなくても電源層6dとアー
スN6eの双方を本発明の他の実施例の第3図に示すよ
うな断面構造に配置するようにしてもよく、また、さら
には電源層6dとアースj!i 6 eの双方に厚い銅
箔を使用したうえで第3図に示すような断面構造になる
ように配置してもよく、いずれの場合においても上記実
施例と同様な効果を奏する。
Furthermore, although the above embodiment shows an example in which a thick copper foil is used for the inner layer plate, both the power supply layer 6d and the ground N6e can be connected as shown in FIG. 3 of another embodiment of the present invention without using a particularly thick inner layer plate. They may be arranged in a cross-sectional structure as shown, and furthermore, the power layer 6d and the earth j! It is also possible to use thick copper foil on both sides of i 6 e and arrange them so as to have a cross-sectional structure as shown in FIG. 3, and in either case, the same effects as in the above embodiment can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明においては、多層プリント配線板の
内層回路の断面構造を、上下方向に非対称とし、半導体
メモリ素子を実装した上方側が高密度になるようにした
ので、はんだリフロー時に凹型の反りが生じることとな
り、従来に問題となっていた冷却時に生じる凸型の反り
に伴う寸法変化を相殺することができる。従って、反り
の無い平坦な高精度のメモリモジュールを得ることがで
き、さらにはメモリモジュールを実装する際ノ歩留りを
向上できる効果がある。
As described above, in the present invention, the cross-sectional structure of the inner layer circuit of the multilayer printed wiring board is asymmetrical in the vertical direction, and the upper side where the semiconductor memory element is mounted has a high density, so that concave warpage occurs during solder reflow. This can offset the dimensional change caused by the warpage of the convex shape that occurs during cooling, which has been a problem in the past. Therefore, it is possible to obtain a flat, high-precision memory module without warping, and furthermore, it is possible to improve the yield when mounting the memory module.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例によるメモリモジュールの断
面構造を示す図、第2図(a)〜(ill1は第1図の
メモリモジュールの製造工程を示す図、第3図は本発明
の他の実施例によるメモリモジュールの断面構造を示す
図、第4図は従来のメモリモジュールの断面構造を示す
図、第5図(a)〜(elは第4図のメモリモジュール
の製造工程を示す図である。 図において、1は半導体メモリ、2ははんだ、2aは溶
融したはんだ、2bは凝固したはんだ、5はガラスエポ
キシ層、6aはプリント配線板表面の信号層、6bは裏
面の信号層、6cは信号層、6dは電源層、6eはアー
ス層、6fは信号層、7は銅めっきスルーホール、10
は多層プリント配線板、12はソルダクリーム、15は
気相はんだ付は装置、20はメモリモジュールである。 なお図中同一符号は同−又は相当部分を示す。
1 is a diagram showing a cross-sectional structure of a memory module according to an embodiment of the present invention, FIGS. 2(a) to (ill1) are diagrams showing the manufacturing process of the memory module of FIG. 1, and FIG. A diagram showing a cross-sectional structure of a memory module according to another embodiment, FIG. 4 is a diagram showing a cross-sectional structure of a conventional memory module, and FIGS. In the figure, 1 is a semiconductor memory, 2 is solder, 2a is molten solder, 2b is solidified solder, 5 is a glass epoxy layer, 6a is a signal layer on the front side of the printed wiring board, and 6b is a signal layer on the back side. , 6c is a signal layer, 6d is a power layer, 6e is a ground layer, 6f is a signal layer, 7 is a copper plated through hole, 10
1 is a multilayer printed wiring board, 12 is a solder cream, 15 is a vapor phase soldering device, and 20 is a memory module. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)複数の半導体メモリ素子を多層プリント配線板の
片側の表面にのみ実装してなるメモリモジュールにおい
て、 上記多層プリント配線板の内層回路の断面構造を、上記
半導体メモリ素子を実装した側が高密度になるよう上下
方向に非対称としたことを特徴とするメモリモジュール
(1) In a memory module in which a plurality of semiconductor memory elements are mounted only on one surface of a multilayer printed wiring board, the cross-sectional structure of the inner layer circuit of the multilayer printed wiring board has a high density on the side where the semiconductor memory elements are mounted. A memory module characterized by being asymmetrical in the vertical direction so that
JP63298609A 1988-11-25 1988-11-25 Memory module Pending JPH02143583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63298609A JPH02143583A (en) 1988-11-25 1988-11-25 Memory module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63298609A JPH02143583A (en) 1988-11-25 1988-11-25 Memory module

Publications (1)

Publication Number Publication Date
JPH02143583A true JPH02143583A (en) 1990-06-01

Family

ID=17861942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63298609A Pending JPH02143583A (en) 1988-11-25 1988-11-25 Memory module

Country Status (1)

Country Link
JP (1) JPH02143583A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461774A (en) * 1994-03-25 1995-10-31 Motorola, Inc. Apparatus and method of elastically bowing a base plate
EP0735807A1 (en) * 1995-03-27 1996-10-02 Canon Kabushiki Kaisha Electric-circuit board for a display apparatus
EP0805492A2 (en) * 1996-04-03 1997-11-05 Jürgen Dr.-Ing. Schulz-Harder Curved metal ceramic substrate
JP2001217514A (en) * 2000-02-03 2001-08-10 Denso Corp Multi-layered wiring board
US6291775B1 (en) * 1998-04-21 2001-09-18 Matsushita Electric Industrial Co., Ltd. Flip chip bonding land waving prevention pattern
WO2007052422A1 (en) * 2005-11-01 2007-05-10 Murata Manufacturing Co., Ltd. Circuit device manufacturing method and circuit device
JP2007526584A (en) * 2004-03-03 2007-09-13 ハベル、インコーポレーテッド Midspan patch panel with data terminal equipment, power supply, and circuit isolation for data collection
JP2012099692A (en) * 2010-11-04 2012-05-24 Ngk Spark Plug Co Ltd Multilayer wiring board

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461774A (en) * 1994-03-25 1995-10-31 Motorola, Inc. Apparatus and method of elastically bowing a base plate
EP0735807A1 (en) * 1995-03-27 1996-10-02 Canon Kabushiki Kaisha Electric-circuit board for a display apparatus
US5912654A (en) * 1995-03-27 1999-06-15 Canon Kabushiki Kaisha Electric-circuit board for a display apparatus
EP0805492A2 (en) * 1996-04-03 1997-11-05 Jürgen Dr.-Ing. Schulz-Harder Curved metal ceramic substrate
EP0805492A3 (en) * 1996-04-03 1998-05-20 Jürgen Dr.-Ing. Schulz-Harder Curved metal ceramic substrate
US6291775B1 (en) * 1998-04-21 2001-09-18 Matsushita Electric Industrial Co., Ltd. Flip chip bonding land waving prevention pattern
JP2001217514A (en) * 2000-02-03 2001-08-10 Denso Corp Multi-layered wiring board
JP2007526584A (en) * 2004-03-03 2007-09-13 ハベル、インコーポレーテッド Midspan patch panel with data terminal equipment, power supply, and circuit isolation for data collection
WO2007052422A1 (en) * 2005-11-01 2007-05-10 Murata Manufacturing Co., Ltd. Circuit device manufacturing method and circuit device
JPWO2007052422A1 (en) * 2005-11-01 2009-04-30 株式会社村田製作所 Circuit device manufacturing method and circuit device
JP2012099692A (en) * 2010-11-04 2012-05-24 Ngk Spark Plug Co Ltd Multilayer wiring board

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