JPH02143583A - Memory module - Google Patents
Memory moduleInfo
- Publication number
- JPH02143583A JPH02143583A JP63298609A JP29860988A JPH02143583A JP H02143583 A JPH02143583 A JP H02143583A JP 63298609 A JP63298609 A JP 63298609A JP 29860988 A JP29860988 A JP 29860988A JP H02143583 A JPH02143583 A JP H02143583A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- memory module
- solder
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 229910000679 solder Inorganic materials 0.000 abstract description 23
- 238000000034 method Methods 0.000 abstract description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 239000004593 Epoxy Substances 0.000 abstract description 5
- 239000011889 copper foil Substances 0.000 abstract description 5
- 238000007711 solidification Methods 0.000 abstract 1
- 230000008023 solidification Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000001816 cooling Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 239000006071 cream Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数の半導体メモリ素子を一枚のプリント配
ｖＡ板の片側の表面にのみ搭載することによって成るメ
モリモジュールにおいて、特に多層構造のプリント配線
板を用いるものに関するものである。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a memory module in which a plurality of semiconductor memory elements are mounted only on one surface of a single printed circuit board, and particularly to a memory module having a multilayer structure. This relates to a device using a printed wiring board.
メモリモジュールは、主プリント配線板（マザーボード
）上の限られた空間内にできるだけ多くの部品を搭載す
る実装方式、すなわち高田度実装を実現するために開発
されたもので、−枚の小形プリント配線板（ドータボー
ド）上に複数個の半導体メモリが実装されて成るメモリ
ボードの一種である。メモリモジュールはマザーボード
に用意されたソケットに挿入することによって実装する
方式や、マザーボード上のスルーホールに直接はんだ実
装する方式などがある。いずれの実装方式においてもメ
モリモジュールに反りやゆがみといった寸法誤差があっ
てはスムーズな実装が望めないため、できるだけ高精度
な仕上がりであることが求められる。Memory modules were developed to realize Takada mounting, a mounting method that mounts as many components as possible in a limited space on the main printed wiring board (motherboard). It is a type of memory board in which multiple semiconductor memories are mounted on a board (daughter board). Memory modules can be mounted by inserting them into sockets provided on the motherboard, or solder directly into through-holes on the motherboard. In any mounting method, smooth mounting cannot be expected if the memory module has dimensional errors such as warping or distortion, so it is required that the finish be as precise as possible.
従来のメモリモジュールは例えばＳｅｍ１ｃｏｎ Ｎｅ
ｗｓトリプルＡ（三菱電機側発行、！１ｈ１９．１９８
８年３月号）Ｐ６〜７に記載のような仕様のものがあり
、複数の半導体メモリ素子を一枚のプリント配線板の表
裏両面に搭載する両面実装と、プリント配線板の片側の
表面にのみ搭載する片面実装の２種類があるが、このう
ち片面実装のメモリモジュールは第４図に示すような断
面構造をしている０図において、１は半導体メモリ、２
は半導体メモリ１とプリント配線板を接続するためのは
んだ、５はガラス布基材エポキシ樹脂層（以下ガラスエ
ポキシ層と称する）、６ａはプリント配線板表面の信号
層、６ｂは裏面の信号層、６Ｃは信号層、６ｄは電源層
、６ｅはアース層、６ｆは信号層、７は銅めっきスルー
ホール、１０は以上を集めてなる多層プリント配線板で
ある。Conventional memory modules are for example Sem1con Ne
ws triple A (issued by Mitsubishi Electric, !1h19.198
There are two-sided mounting methods, in which multiple semiconductor memory elements are mounted on both the front and back sides of a single printed wiring board, and two-sided mounting methods, in which multiple semiconductor memory elements are mounted on both the front and back surfaces of a single printed wiring board, and those with specifications as described on pages 6 and 7 (March 2008 issue). There are two types of single-sided mounting, in which memory modules are mounted only on one side. Among these, single-sided mounting memory modules have a cross-sectional structure as shown in Figure 4.
5 is a glass cloth base epoxy resin layer (hereinafter referred to as glass epoxy layer); 6a is a signal layer on the front side of the printed wiring board; 6b is a signal layer on the back side; 6C is a signal layer, 6d is a power layer, 6e is an earth layer, 6f is a signal layer, 7 is a copper-plated through hole, and 10 is a multilayer printed wiring board made up of the above.
このようなメモリモジュールは例えばプリント回路技術
便覧（社団法人日本プリント回路工業金線、日刊工業新
聞社刊、昭和６２年２月発行）Ｐ２Ｓ５に記載のように
、第５図ｆａ）〜（ｅ）のような工程を経て製造される
。第５図Ｔａ）は半導体メモリを搭載する多層プリント
配線板１１、第５図（ｂ）はスクリーン印刷法によって
ソルダクリーム１２が多層プリント配線板１１に印刷さ
れた状態、第５図（Ｃ）は表面実装タイプの半導体メモ
リ１を装着した状態、第５図（ｄ）は気相はんだ付は装
置１５によるはんだリフロー工程で、２ａは溶融したは
んだを示す。Such a memory module is, for example, as shown in Figure 5 fa) to (e) as described in Printed Circuit Technology Handbook (Japan Printed Circuit Industry Gold Wire, Nikkan Kogyo Shimbun, published February 1986) P2S5. It is manufactured through the following steps. FIG. 5 Ta) shows a multilayer printed wiring board 11 on which a semiconductor memory is mounted, FIG. FIG. 5(d) shows a state in which a surface mount type semiconductor memory 1 is mounted, and vapor phase soldering is a solder reflow process using the device 15, and 2a indicates molten solder.
また、第５図（ｅ）は完成したメモリモジュール２０で
２ｂは凝固したはんだである。Further, FIG. 5(e) shows the completed memory module 20, and 2b is solidified solder.
従来のメモリモジュールは以上のような製造工程を経て
製作されており、半導体メモリ１を搭載するプリント配
線板１１は第４図に示したようにその断面の内層回路が
ほぼ対称構造であるため、第５図（ｄ＋のはんだリフロ
ー工程において熱によりプリント配線板１１が膨張した
状態ではんだ１２が溶融し、その後の冷却工程において
プリント配線板１１が十分収縮していない温度（通常は
１８０℃以上）ではんだが凝固すると、半導体メモリを
搭載した側の収縮が凝固したはんだ２ｂと半導体メモリ
１によるくさび効果によって機械的に阻止される結果、
室温まで冷却した状態では第２図（ｅｌに示すように、
メモリモジュール２０に反りが生じ、メモリモジュール
２０をマザーボードに実装する場合に装着が困難になる
という欠点があった。このような欠点は、メモリモジュ
ール２０に搭載する半導体メモリ１が大容量化するに伴
って大形化し、同時にプリント配線板１１の面積が増大
する傾向にあってますます顕著化してくる。Conventional memory modules are manufactured through the manufacturing process described above, and the printed wiring board 11 on which the semiconductor memory 1 is mounted has an almost symmetrical structure in its cross-sectional inner layer circuit, as shown in FIG. FIG. 5 (d+ solder reflow process, the solder 12 melts when the printed wiring board 11 expands due to heat, and the temperature at which the printed wiring board 11 does not sufficiently contract in the subsequent cooling process (usually 180°C or higher) When the solder solidifies, the contraction of the side on which the semiconductor memory is mounted is mechanically prevented by the wedge effect between the solidified solder 2b and the semiconductor memory 1.
When cooled to room temperature, as shown in Figure 2 (el),
There is a drawback that the memory module 20 is warped, making it difficult to mount the memory module 20 on a motherboard. These drawbacks become more and more noticeable as the capacity of the semiconductor memory 1 mounted on the memory module 20 increases, and as the area of the printed wiring board 11 tends to increase at the same time.
この発明はこのような従来のメモリモジュールの構造上
の欠点を除去するために成されたもので、従来の製造プ
ロセスを変更することなしに完成時に反りが生じない、
高精度なメモリモジュールを提供することを目的とする
。The present invention was made to eliminate the structural defects of such conventional memory modules, and it is possible to eliminate warping when completed without changing the conventional manufacturing process.
The purpose is to provide high-precision memory modules.
この発明に係るメモリモジュールは、多層プリント配線
板の内層回路の断面構造を、上記半導体メモリ素子を実
装した側が高密度になるよう上下方向に非対称にしたも
のである。In the memory module according to the present invention, the cross-sectional structure of the inner layer circuit of the multilayer printed wiring board is asymmetrical in the vertical direction so that the side on which the semiconductor memory element is mounted has a higher density.
本発明においては、メモリモジュール用多層プリント配
線板の内層板の断面構造を、半導体メモリが実装された
側が高密度になるような上下方向に非対称な構造とした
ので、はんだリフロー工程で従来の冷却工程で生じてい
た凸型の反りと逆方向の凹型の反りが生じるようになり
、その後の冷却工程において発生する反りを相殺でき、
完成時点における反りやゆがみを抑えることができる。In the present invention, the cross-sectional structure of the inner layer board of the multilayer printed wiring board for memory modules is made vertically asymmetrical so that the side where semiconductor memory is mounted has a higher density. A concave warp occurs in the opposite direction to the convex warp that occurred during the process, and the warp that occurs during the subsequent cooling process can be offset.
It is possible to suppress warpage and distortion at the time of completion.
以下、この発明の一実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例によるメモリモジュールの
断面構造を示す図であり、特に、プリント配線板の要部
を６層配線板を例として示したものである。また、第２
図（ａｌ〜（ｅｌは第１図のメモリモジュールの製造方
法を示す図である０両図において、ｌは半導体メモリ、
２ははんだ、２ａは溶融したはんだ、２ｂは凝固したは
んだ、５はガラスエポキシ層、６ａはプリント配線板表
面の信号層、６ｂは裏面の信号層、６ｃは信号層、６ｄ
は電源層、６ｅはアース層、６ｆは信号層、７は銅めっ
きスルーホール、１０は以上を集めて成る多層プリント
配線板、１２はソルダクリーム、１５は気相はんだ付は
装置、２０はメモリモジュールである。このような構造
において、電源層６ｄは例えば厚さ７０μｍの電解銅箔
を用いた厚い層で、それ以外の１ｉ６ａ、６ｂ、６ｃ、
６ｅ、６ｆは例えば厚さ３５μｍの電解ｆ１箔を用いた
層である。FIG. 1 is a diagram showing a cross-sectional structure of a memory module according to an embodiment of the present invention, and in particular, shows the main parts of a printed wiring board by taking a six-layer wiring board as an example. Also, the second
Figures (al to (el) are diagrams showing the manufacturing method of the memory module in Figure 1. In both figures, l is a semiconductor memory,
2 is solder, 2a is molten solder, 2b is solidified solder, 5 is glass epoxy layer, 6a is a signal layer on the front side of the printed wiring board, 6b is a signal layer on the back side, 6c is a signal layer, 6d
6e is a power layer, 6e is a ground layer, 6f is a signal layer, 7 is a copper-plated through hole, 10 is a multilayer printed wiring board consisting of the above, 12 is a solder cream, 15 is a vapor phase soldering device, 20 is a memory It is a module. In such a structure, the power supply layer 6d is a thick layer using electrolytic copper foil with a thickness of 70 μm, for example, and the other layers 1i6a, 6b, 6c,
6e and 6f are layers using electrolytic f1 foil having a thickness of 35 μm, for example.
本発明によるプリント配線板１１は内層板の中では面積
が大きい電源層６ｄに、厚い電解銅箔を使用し、半導体
メモリ１搭載側の表面近くに配置することによって、プ
リント配線板１１を非対称の断面構造としたもので、そ
の結果、次に述べるような効果を得ることができる。つ
まり本実施例では従来の第５図に示した工程のうち、特
に（ｄ）及びｔｅｌの工程が第２図に示した（ｄ）、及
び（ｅ）のような工程になる。すなわち第２図ｆａ）〜
（ｅ）に示したはんだリフロー工程において、熱により
プリント配線板が膨張した状態ではプリント配線板１１
のガラスエポキシ積層板５と内層板の非対称性に基づく
線膨張係数の違いによる反りが生じたままはんだが溶融
するため、その後の冷却工程において、はんだが凝固す
ることによる半導体メモリ搭載側のプリント配線板の収
縮が阻止されても、室温まで冷却した状態では第２図（
ｉｌｌ）に示した様に、メモリモジュール全体としての
反りが相殺されることとなり、平坦なメモリモジュール
を提供することができる。The printed wiring board 11 according to the present invention uses thick electrolytic copper foil for the power supply layer 6d, which has a large area among the inner layers, and is arranged near the surface on the side where the semiconductor memory 1 is mounted, thereby making the printed wiring board 11 asymmetrical. It has a cross-sectional structure, and as a result, the following effects can be obtained. That is, in this embodiment, among the conventional steps shown in FIG. 5, the steps (d) and tel in particular become the steps (d) and (e) shown in FIG. 2. That is, Fig. 2 fa) ~
In the solder reflow process shown in (e), when the printed wiring board expands due to heat, the printed wiring board 11
As the solder melts while warping due to the difference in linear expansion coefficient due to the asymmetry between the glass epoxy laminate 5 and the inner layer, the printed wiring on the side where the semiconductor memory is mounted is caused by the solder solidifying in the subsequent cooling process. Even if the shrinkage of the plate is prevented, the condition shown in Figure 2 (
As shown in (ill), the warpage of the memory module as a whole is canceled out, and a flat memory module can be provided.
なお、上記実施例では内層板のうち電源Ｎ６ｄを厚くし
た例を示したが、内層板の中ではｔＢ層６ｄ同様、面積
の大きいアースＪｉ６ｅを厚くしてもよい。ただしこの
場合は電源層６ｄとアース層６ｅの位置を上記実施例と
は逆にする必要がある。In the above embodiment, an example was shown in which the power source N6d of the inner layer board was thickened, but the ground Ji6e, which has a large area, may be made thicker in the inner layer board, similar to the tB layer 6d. However, in this case, the positions of the power layer 6d and the earth layer 6e need to be reversed from those in the above embodiment.
また上記実施例では内層板に厚い銅箔を用いた例を示し
たが、特に厚い内層板を用いなくても電源層６ｄとアー
スＮ６ｅの双方を本発明の他の実施例の第３図に示すよ
うな断面構造に配置するようにしてもよく、また、さら
には電源層６ｄとアースｊ！ｉ ６ ｅの双方に厚い銅
箔を使用したうえで第３図に示すような断面構造になる
ように配置してもよく、いずれの場合においても上記実
施例と同様な効果を奏する。Furthermore, although the above embodiment shows an example in which a thick copper foil is used for the inner layer plate, both the power supply layer 6d and the ground N6e can be connected as shown in FIG. 3 of another embodiment of the present invention without using a particularly thick inner layer plate. They may be arranged in a cross-sectional structure as shown, and furthermore, the power layer 6d and the earth j! It is also possible to use thick copper foil on both sides of i 6 e and arrange them so as to have a cross-sectional structure as shown in FIG. 3, and in either case, the same effects as in the above embodiment can be achieved.
以上のように本発明においては、多層プリント配線板の
内層回路の断面構造を、上下方向に非対称とし、半導体
メモリ素子を実装した上方側が高密度になるようにした
ので、はんだリフロー時に凹型の反りが生じることとな
り、従来に問題となっていた冷却時に生じる凸型の反り
に伴う寸法変化を相殺することができる。従って、反り
の無い平坦な高精度のメモリモジュールを得ることがで
き、さらにはメモリモジュールを実装する際ノ歩留りを
向上できる効果がある。As described above, in the present invention, the cross-sectional structure of the inner layer circuit of the multilayer printed wiring board is asymmetrical in the vertical direction, and the upper side where the semiconductor memory element is mounted has a high density, so that concave warpage occurs during solder reflow. This can offset the dimensional change caused by the warpage of the convex shape that occurs during cooling, which has been a problem in the past. Therefore, it is possible to obtain a flat, high-precision memory module without warping, and furthermore, it is possible to improve the yield when mounting the memory module.
第１図は本発明の一実施例によるメモリモジュールの断
面構造を示す図、第２図（ａ）〜（ｉｌｌ１は第１図の
メモリモジュールの製造工程を示す図、第３図は本発明
の他の実施例によるメモリモジュールの断面構造を示す
図、第４図は従来のメモリモジュールの断面構造を示す
図、第５図（ａ）〜（ｅｌは第４図のメモリモジュール
の製造工程を示す図である。
図において、１は半導体メモリ、２ははんだ、２ａは溶
融したはんだ、２ｂは凝固したはんだ、５はガラスエポ
キシ層、６ａはプリント配線板表面の信号層、６ｂは裏
面の信号層、６ｃは信号層、６ｄは電源層、６ｅはアー
ス層、６ｆは信号層、７は銅めっきスルーホール、１０
は多層プリント配線板、１２はソルダクリーム、１５は
気相はんだ付は装置、２０はメモリモジュールである。
なお図中同一符号は同−又は相当部分を示す。1 is a diagram showing a cross-sectional structure of a memory module according to an embodiment of the present invention, FIGS. 2(a) to (ill1) are diagrams showing the manufacturing process of the memory module of FIG. 1, and FIG. A diagram showing a cross-sectional structure of a memory module according to another embodiment, FIG. 4 is a diagram showing a cross-sectional structure of a conventional memory module, and FIGS. In the figure, 1 is a semiconductor memory, 2 is solder, 2a is molten solder, 2b is solidified solder, 5 is a glass epoxy layer, 6a is a signal layer on the front side of the printed wiring board, and 6b is a signal layer on the back side. , 6c is a signal layer, 6d is a power layer, 6e is a ground layer, 6f is a signal layer, 7 is a copper plated through hole, 10
1 is a multilayer printed wiring board, 12 is a solder cream, 15 is a vapor phase soldering device, and 20 is a memory module. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
片側の表面にのみ実装してなるメモリモジュールにおい
て、 上記多層プリント配線板の内層回路の断面構造を、上記
半導体メモリ素子を実装した側が高密度になるよう上下
方向に非対称としたことを特徴とするメモリモジュール
。(1) In a memory module in which a plurality of semiconductor memory elements are mounted only on one surface of a multilayer printed wiring board, the cross-sectional structure of the inner layer circuit of the multilayer printed wiring board has a high density on the side where the semiconductor memory elements are mounted. A memory module characterized by being asymmetrical in the vertical direction so that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298609A JPH02143583A (en) | 1988-11-25 | 1988-11-25 | Memory module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298609A JPH02143583A (en) | 1988-11-25 | 1988-11-25 | Memory module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02143583A true JPH02143583A (en) | 1990-06-01 |
Family
ID=17861942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63298609A Pending JPH02143583A (en) | 1988-11-25 | 1988-11-25 | Memory module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02143583A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5461774A (en) * | 1994-03-25 | 1995-10-31 | Motorola, Inc. | Apparatus and method of elastically bowing a base plate |
| EP0735807A1 (en) * | 1995-03-27 | 1996-10-02 | Canon Kabushiki Kaisha | Electric-circuit board for a display apparatus |
| EP0805492A2 (en) * | 1996-04-03 | 1997-11-05 | Jürgen Dr.-Ing. Schulz-Harder | Curved metal ceramic substrate |
| JP2001217514A (en) * | 2000-02-03 | 2001-08-10 | Denso Corp | Multi-layered wiring board |
| US6291775B1 (en) * | 1998-04-21 | 2001-09-18 | Matsushita Electric Industrial Co., Ltd. | Flip chip bonding land waving prevention pattern |
| WO2007052422A1 (en) * | 2005-11-01 | 2007-05-10 | Murata Manufacturing Co., Ltd. | Circuit device manufacturing method and circuit device |
| JP2007526584A (en) * | 2004-03-03 | 2007-09-13 | ハベル、インコーポレーテッド | Midspan patch panel with data terminal equipment, power supply, and circuit isolation for data collection |
| JP2012099692A (en) * | 2010-11-04 | 2012-05-24 | Ngk Spark Plug Co Ltd | Multilayer wiring board |
-
1988
- 1988-11-25 JP JP63298609A patent/JPH02143583A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5461774A (en) * | 1994-03-25 | 1995-10-31 | Motorola, Inc. | Apparatus and method of elastically bowing a base plate |
| EP0735807A1 (en) * | 1995-03-27 | 1996-10-02 | Canon Kabushiki Kaisha | Electric-circuit board for a display apparatus |
| US5912654A (en) * | 1995-03-27 | 1999-06-15 | Canon Kabushiki Kaisha | Electric-circuit board for a display apparatus |
| EP0805492A2 (en) * | 1996-04-03 | 1997-11-05 | Jürgen Dr.-Ing. Schulz-Harder | Curved metal ceramic substrate |
| EP0805492A3 (en) * | 1996-04-03 | 1998-05-20 | Jürgen Dr.-Ing. Schulz-Harder | Curved metal ceramic substrate |
| US6291775B1 (en) * | 1998-04-21 | 2001-09-18 | Matsushita Electric Industrial Co., Ltd. | Flip chip bonding land waving prevention pattern |
| JP2001217514A (en) * | 2000-02-03 | 2001-08-10 | Denso Corp | Multi-layered wiring board |
| JP2007526584A (en) * | 2004-03-03 | 2007-09-13 | ハベル、インコーポレーテッド | Midspan patch panel with data terminal equipment, power supply, and circuit isolation for data collection |
| WO2007052422A1 (en) * | 2005-11-01 | 2007-05-10 | Murata Manufacturing Co., Ltd. | Circuit device manufacturing method and circuit device |
| JPWO2007052422A1 (en) * | 2005-11-01 | 2009-04-30 | 株式会社村田製作所 | Circuit device manufacturing method and circuit device |
| JP2012099692A (en) * | 2010-11-04 | 2012-05-24 | Ngk Spark Plug Co Ltd | Multilayer wiring board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5048166A (en) | Method of making rigid-flexible multilayer board system | |
| JPH02143583A (en) | Memory module | |
| JPS6158297A (en) | Multilayer printed circuit board | |
| GB2162694A (en) | Printed circuits | |
| US6555015B1 (en) | Multi-layer printed circuit board and method of making same | |
| JPH0787223B2 (en) | Printed circuit board and manufacturing method thereof | |
| JP2000261152A (en) | Printed wiring board assembly | |
| JPH08195566A (en) | Multilayer electronic board, method of manufacture and arithmetic processing board | |
| JPH10135648A (en) | Multilayer printed wiring board | |
| CN111629533B (en) | Warpage improving method of PCB | |
| JP2000261109A (en) | Wiring board | |
| JP2019204873A (en) | Module substrate | |
| JPS6134989A (en) | Substrate for placing electronic part and method of producing same | |
| JPH01225196A (en) | Manufacture of laminated hybrid integrated circuit | |
| JP2517315B2 (en) | Electronic circuit package | |
| JPS6362920B2 (en) | ||
| JPH01207992A (en) | Circuit wiring board | |
| JPH0350888A (en) | Restoration of conductor via | |
| JPH036096A (en) | Circuit board | |
| JPH03285382A (en) | Printed wiring board | |
| JPH0438160B2 (en) | ||
| JPH05347478A (en) | Printed wiring board | |
| JPS6356925A (en) | Integrated circuit | |
| JPH0582939A (en) | Manufacture of printed wiring board | |
| JP2007242674A (en) | Printed wiring board, electronic component mounting body, manufacturing process thereof, and electronic apparatus |